err.no Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  51
  52 /* enable NPT for AMD64 and X86 with PAE */
  53 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  54 static bool npt_enabled = true;
  55 #else
  56 static bool npt_enabled = false;
  57 #endif
  58 static int npt = 1;
  59
  60 module_param(npt, int, S_IRUGO);
  61
  62 static void kvm_reput_irq(struct vcpu_svm *svm);
  63
  64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  65 {
  66         return container_of(vcpu, struct vcpu_svm, vcpu);
  67 }
  68
  69 static unsigned long iopm_base;
  70
  71 struct kvm_ldttss_desc {
  72         u16 limit0;
  73         u16 base0;
  74         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  75         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  76         u32 base3;
  77         u32 zero1;
  78 } __attribute__((packed));
  79
  80 struct svm_cpu_data {
  81         int cpu;
  82
  83         u64 asid_generation;
  84         u32 max_asid;
  85         u32 next_asid;
  86         struct kvm_ldttss_desc *tss_desc;
  87
  88         struct page *save_area;
  89 };
  90
  91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  92 static uint32_t svm_features;
  93
  94 struct svm_init_data {
  95         int cpu;
  96         int r;
  97 };
  98
  99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 100
 101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 102 #define MSRS_RANGE_SIZE 2048
 103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 104
 105 #define MAX_INST_SIZE 15
 106
 107 static inline u32 svm_has(u32 feat)
 108 {
 109         return svm_features & feat;
 110 }
 111
 112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 113 {
 114         int word_index = __ffs(vcpu->arch.irq_summary);
 115         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 116         int irq = word_index * BITS_PER_LONG + bit_index;
 117
 118         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 119         if (!vcpu->arch.irq_pending[word_index])
 120                 clear_bit(word_index, &vcpu->arch.irq_summary);
 121         return irq;
 122 }
 123
 124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 125 {
 126         set_bit(irq, vcpu->arch.irq_pending);
 127         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 128 }
 129
 130 static inline void clgi(void)
 131 {
 132         asm volatile (SVM_CLGI);
 133 }
 134
 135 static inline void stgi(void)
 136 {
 137         asm volatile (SVM_STGI);
 138 }
 139
 140 static inline void invlpga(unsigned long addr, u32 asid)
 141 {
 142         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 143 }
 144
 145 static inline unsigned long kvm_read_cr2(void)
 146 {
 147         unsigned long cr2;
 148
 149         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 150         return cr2;
 151 }
 152
 153 static inline void kvm_write_cr2(unsigned long val)
 154 {
 155         asm volatile ("mov %0, %%cr2" :: "r" (val));
 156 }
 157
 158 static inline unsigned long read_dr6(void)
 159 {
 160         unsigned long dr6;
 161
 162         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 163         return dr6;
 164 }
 165
 166 static inline void write_dr6(unsigned long val)
 167 {
 168         asm volatile ("mov %0, %%dr6" :: "r" (val));
 169 }
 170
 171 static inline unsigned long read_dr7(void)
 172 {
 173         unsigned long dr7;
 174
 175         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 176         return dr7;
 177 }
 178
 179 static inline void write_dr7(unsigned long val)
 180 {
 181         asm volatile ("mov %0, %%dr7" :: "r" (val));
 182 }
 183
 184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 185 {
 186         to_svm(vcpu)->asid_generation--;
 187 }
 188
 189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 190 {
 191         force_new_asid(vcpu);
 192 }
 193
 194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 195 {
 196         if (!npt_enabled && !(efer & EFER_LMA))
 197                 efer &= ~EFER_LME;
 198
 199         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 200         vcpu->arch.shadow_efer = efer;
 201 }
 202
 203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 204                                 bool has_error_code, u32 error_code)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         svm->vmcb->control.event_inj = nr
 209                 | SVM_EVTINJ_VALID
 210                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 211                 | SVM_EVTINJ_TYPE_EXEPT;
 212         svm->vmcb->control.event_inj_err = error_code;
 213 }
 214
 215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 220 }
 221
 222 static int is_external_interrupt(u32 info)
 223 {
 224         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 225         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 226 }
 227
 228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 229 {
 230         struct vcpu_svm *svm = to_svm(vcpu);
 231
 232         if (!svm->next_rip) {
 233                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 234                 return;
 235         }
 236         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 237                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 238                        __func__,
 239                        svm->vmcb->save.rip,
 240                        svm->next_rip);
 241
 242         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = 1;
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         uint32_t eax, ebx, ecx, edx;
 251
 252         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 253                 printk(KERN_INFO "has_svm: not amd\n");
 254                 return 0;
 255         }
 256
 257         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 258         if (eax < SVM_CPUID_FUNC) {
 259                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 260                 return 0;
 261         }
 262
 263         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 264         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 265                 printk(KERN_DEBUG "has_svm: svm not available\n");
 266                 return 0;
 267         }
 268         return 1;
 269 }
 270
 271 static void svm_hardware_disable(void *garbage)
 272 {
 273         struct svm_cpu_data *svm_data
 274                 = per_cpu(svm_data, raw_smp_processor_id());
 275
 276         if (svm_data) {
 277                 uint64_t efer;
 278
 279                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 280                 rdmsrl(MSR_EFER, efer);
 281                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 282                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 283                 __free_page(svm_data->save_area);
 284                 kfree(svm_data);
 285         }
 286 }
 287
 288 static void svm_hardware_enable(void *garbage)
 289 {
 290
 291         struct svm_cpu_data *svm_data;
 292         uint64_t efer;
 293         struct desc_ptr gdt_descr;
 294         struct desc_struct *gdt;
 295         int me = raw_smp_processor_id();
 296
 297         if (!has_svm()) {
 298                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 299                 return;
 300         }
 301         svm_data = per_cpu(svm_data, me);
 302
 303         if (!svm_data) {
 304                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 305                        me);
 306                 return;
 307         }
 308
 309         svm_data->asid_generation = 1;
 310         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 311         svm_data->next_asid = svm_data->max_asid + 1;
 312
 313         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 314         gdt = (struct desc_struct *)gdt_descr.address;
 315         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 316
 317         rdmsrl(MSR_EFER, efer);
 318         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 319
 320         wrmsrl(MSR_VM_HSAVE_PA,
 321                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 322 }
 323
 324 static int svm_cpu_init(int cpu)
 325 {
 326         struct svm_cpu_data *svm_data;
 327         int r;
 328
 329         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 330         if (!svm_data)
 331                 return -ENOMEM;
 332         svm_data->cpu = cpu;
 333         svm_data->save_area = alloc_page(GFP_KERNEL);
 334         r = -ENOMEM;
 335         if (!svm_data->save_area)
 336                 goto err_1;
 337
 338         per_cpu(svm_data, cpu) = svm_data;
 339
 340         return 0;
 341
 342 err_1:
 343         kfree(svm_data);
 344         return r;
 345
 346 }
 347
 348 static void set_msr_interception(u32 *msrpm, unsigned msr,
 349                                  int read, int write)
 350 {
 351         int i;
 352
 353         for (i = 0; i < NUM_MSR_MAPS; i++) {
 354                 if (msr >= msrpm_ranges[i] &&
 355                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 356                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 357                                           msrpm_ranges[i]) * 2;
 358
 359                         u32 *base = msrpm + (msr_offset / 32);
 360                         u32 msr_shift = msr_offset % 32;
 361                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 362                         *base = (*base & ~(0x3 << msr_shift)) |
 363                                 (mask << msr_shift);
 364                         return;
 365                 }
 366         }
 367         BUG();
 368 }
 369
 370 static void svm_vcpu_init_msrpm(u32 *msrpm)
 371 {
 372         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 373
 374 #ifdef CONFIG_X86_64
 375         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 376         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 377         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 378         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 379         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 380         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 381 #endif
 382         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 383         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 384         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 385         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 386 }
 387
 388 static void svm_enable_lbrv(struct vcpu_svm *svm)
 389 {
 390         u32 *msrpm = svm->msrpm;
 391
 392         svm->vmcb->control.lbr_ctl = 1;
 393         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 394         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 395         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 396         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 397 }
 398
 399 static void svm_disable_lbrv(struct vcpu_svm *svm)
 400 {
 401         u32 *msrpm = svm->msrpm;
 402
 403         svm->vmcb->control.lbr_ctl = 0;
 404         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 405         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 406         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 407         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 408 }
 409
 410 static __init int svm_hardware_setup(void)
 411 {
 412         int cpu;
 413         struct page *iopm_pages;
 414         void *iopm_va;
 415         int r;
 416
 417         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 418
 419         if (!iopm_pages)
 420                 return -ENOMEM;
 421
 422         iopm_va = page_address(iopm_pages);
 423         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 424         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 425         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 426
 427         if (boot_cpu_has(X86_FEATURE_NX))
 428                 kvm_enable_efer_bits(EFER_NX);
 429
 430         for_each_online_cpu(cpu) {
 431                 r = svm_cpu_init(cpu);
 432                 if (r)
 433                         goto err;
 434         }
 435
 436         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 437
 438         if (!svm_has(SVM_FEATURE_NPT))
 439                 npt_enabled = false;
 440
 441         if (npt_enabled && !npt) {
 442                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 443                 npt_enabled = false;
 444         }
 445
 446         if (npt_enabled) {
 447                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 448                 kvm_enable_tdp();
 449         }
 450
 451         return 0;
 452
 453 err:
 454         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 455         iopm_base = 0;
 456         return r;
 457 }
 458
 459 static __exit void svm_hardware_unsetup(void)
 460 {
 461         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 462         iopm_base = 0;
 463 }
 464
 465 static void init_seg(struct vmcb_seg *seg)
 466 {
 467         seg->selector = 0;
 468         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 469                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 470         seg->limit = 0xffff;
 471         seg->base = 0;
 472 }
 473
 474 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 475 {
 476         seg->selector = 0;
 477         seg->attrib = SVM_SELECTOR_P_MASK | type;
 478         seg->limit = 0xffff;
 479         seg->base = 0;
 480 }
 481
 482 static void init_vmcb(struct vcpu_svm *svm)
 483 {
 484         struct vmcb_control_area *control = &svm->vmcb->control;
 485         struct vmcb_save_area *save = &svm->vmcb->save;
 486
 487         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 488                                         INTERCEPT_CR3_MASK |
 489                                         INTERCEPT_CR4_MASK;
 490
 491         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 492                                         INTERCEPT_CR3_MASK |
 493                                         INTERCEPT_CR4_MASK |
 494                                         INTERCEPT_CR8_MASK;
 495
 496         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 497                                         INTERCEPT_DR1_MASK |
 498                                         INTERCEPT_DR2_MASK |
 499                                         INTERCEPT_DR3_MASK;
 500
 501         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 502                                         INTERCEPT_DR1_MASK |
 503                                         INTERCEPT_DR2_MASK |
 504                                         INTERCEPT_DR3_MASK |
 505                                         INTERCEPT_DR5_MASK |
 506                                         INTERCEPT_DR7_MASK;
 507
 508         control->intercept_exceptions = (1 << PF_VECTOR) |
 509                                         (1 << UD_VECTOR) |
 510                                         (1 << MC_VECTOR);
 511
 512
 513         control->intercept =    (1ULL << INTERCEPT_INTR) |
 514                                 (1ULL << INTERCEPT_NMI) |
 515                                 (1ULL << INTERCEPT_SMI) |
 516                 /*
 517                  * selective cr0 intercept bug?
 518                  *      0:   0f 22 d8                mov    %eax,%cr3
 519                  *      3:   0f 20 c0                mov    %cr0,%eax
 520                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 521                  *      b:   0f 22 c0                mov    %eax,%cr0
 522                  * set cr3 ->interception
 523                  * get cr0 ->interception
 524                  * set cr0 -> no interception
 525                  */
 526                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 527                                 (1ULL << INTERCEPT_CPUID) |
 528                                 (1ULL << INTERCEPT_INVD) |
 529                                 (1ULL << INTERCEPT_HLT) |
 530                                 (1ULL << INTERCEPT_INVLPGA) |
 531                                 (1ULL << INTERCEPT_IOIO_PROT) |
 532                                 (1ULL << INTERCEPT_MSR_PROT) |
 533                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 534                                 (1ULL << INTERCEPT_SHUTDOWN) |
 535                                 (1ULL << INTERCEPT_VMRUN) |
 536                                 (1ULL << INTERCEPT_VMMCALL) |
 537                                 (1ULL << INTERCEPT_VMLOAD) |
 538                                 (1ULL << INTERCEPT_VMSAVE) |
 539                                 (1ULL << INTERCEPT_STGI) |
 540                                 (1ULL << INTERCEPT_CLGI) |
 541                                 (1ULL << INTERCEPT_SKINIT) |
 542                                 (1ULL << INTERCEPT_WBINVD) |
 543                                 (1ULL << INTERCEPT_MONITOR) |
 544                                 (1ULL << INTERCEPT_MWAIT);
 545
 546         control->iopm_base_pa = iopm_base;
 547         control->msrpm_base_pa = __pa(svm->msrpm);
 548         control->tsc_offset = 0;
 549         control->int_ctl = V_INTR_MASKING_MASK;
 550
 551         init_seg(&save->es);
 552         init_seg(&save->ss);
 553         init_seg(&save->ds);
 554         init_seg(&save->fs);
 555         init_seg(&save->gs);
 556
 557         save->cs.selector = 0xf000;
 558         /* Executable/Readable Code Segment */
 559         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 560                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 561         save->cs.limit = 0xffff;
 562         /*
 563          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 564          * be consistent with it.
 565          *
 566          * Replace when we have real mode working for vmx.
 567          */
 568         save->cs.base = 0xf0000;
 569
 570         save->gdtr.limit = 0xffff;
 571         save->idtr.limit = 0xffff;
 572
 573         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 574         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 575
 576         save->efer = MSR_EFER_SVME_MASK;
 577         save->dr6 = 0xffff0ff0;
 578         save->dr7 = 0x400;
 579         save->rflags = 2;
 580         save->rip = 0x0000fff0;
 581
 582         /*
 583          * cr0 val on cpu init should be 0x60000010, we enable cpu
 584          * cache by default. the orderly way is to enable cache in bios.
 585          */
 586         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 587         save->cr4 = X86_CR4_PAE;
 588         /* rdx = ?? */
 589
 590         if (npt_enabled) {
 591                 /* Setup VMCB for Nested Paging */
 592                 control->nested_ctl = 1;
 593                 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 594                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 595                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 596                                                 INTERCEPT_CR3_MASK);
 597                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 598                                                  INTERCEPT_CR3_MASK);
 599                 save->g_pat = 0x0007040600070406ULL;
 600                 /* enable caching because the QEMU Bios doesn't enable it */
 601                 save->cr0 = X86_CR0_ET;
 602                 save->cr3 = 0;
 603                 save->cr4 = 0;
 604         }
 605         force_new_asid(&svm->vcpu);
 606 }
 607
 608 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 609 {
 610         struct vcpu_svm *svm = to_svm(vcpu);
 611
 612         init_vmcb(svm);
 613
 614         if (vcpu->vcpu_id != 0) {
 615                 svm->vmcb->save.rip = 0;
 616                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 617                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 618         }
 619
 620         return 0;
 621 }
 622
 623 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 624 {
 625         struct vcpu_svm *svm;
 626         struct page *page;
 627         struct page *msrpm_pages;
 628         int err;
 629
 630         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 631         if (!svm) {
 632                 err = -ENOMEM;
 633                 goto out;
 634         }
 635
 636         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 637         if (err)
 638                 goto free_svm;
 639
 640         page = alloc_page(GFP_KERNEL);
 641         if (!page) {
 642                 err = -ENOMEM;
 643                 goto uninit;
 644         }
 645
 646         err = -ENOMEM;
 647         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 648         if (!msrpm_pages)
 649                 goto uninit;
 650         svm->msrpm = page_address(msrpm_pages);
 651         svm_vcpu_init_msrpm(svm->msrpm);
 652
 653         svm->vmcb = page_address(page);
 654         clear_page(svm->vmcb);
 655         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 656         svm->asid_generation = 0;
 657         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 658         init_vmcb(svm);
 659
 660         fx_init(&svm->vcpu);
 661         svm->vcpu.fpu_active = 1;
 662         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 663         if (svm->vcpu.vcpu_id == 0)
 664                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 665
 666         return &svm->vcpu;
 667
 668 uninit:
 669         kvm_vcpu_uninit(&svm->vcpu);
 670 free_svm:
 671         kmem_cache_free(kvm_vcpu_cache, svm);
 672 out:
 673         return ERR_PTR(err);
 674 }
 675
 676 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 677 {
 678         struct vcpu_svm *svm = to_svm(vcpu);
 679
 680         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 681         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 682         kvm_vcpu_uninit(vcpu);
 683         kmem_cache_free(kvm_vcpu_cache, svm);
 684 }
 685
 686 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 687 {
 688         struct vcpu_svm *svm = to_svm(vcpu);
 689         int i;
 690
 691         if (unlikely(cpu != vcpu->cpu)) {
 692                 u64 tsc_this, delta;
 693
 694                 /*
 695                  * Make sure that the guest sees a monotonically
 696                  * increasing TSC.
 697                  */
 698                 rdtscll(tsc_this);
 699                 delta = vcpu->arch.host_tsc - tsc_this;
 700                 svm->vmcb->control.tsc_offset += delta;
 701                 vcpu->cpu = cpu;
 702                 kvm_migrate_apic_timer(vcpu);
 703         }
 704
 705         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 706                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 707 }
 708
 709 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 710 {
 711         struct vcpu_svm *svm = to_svm(vcpu);
 712         int i;
 713
 714         ++vcpu->stat.host_state_reload;
 715         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 716                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 717
 718         rdtscll(vcpu->arch.host_tsc);
 719 }
 720
 721 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 722 {
 723 }
 724
 725 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 726 {
 727         struct vcpu_svm *svm = to_svm(vcpu);
 728
 729         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 730         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 731         vcpu->arch.rip = svm->vmcb->save.rip;
 732 }
 733
 734 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 735 {
 736         struct vcpu_svm *svm = to_svm(vcpu);
 737         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 738         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 739         svm->vmcb->save.rip = vcpu->arch.rip;
 740 }
 741
 742 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 743 {
 744         return to_svm(vcpu)->vmcb->save.rflags;
 745 }
 746
 747 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 748 {
 749         to_svm(vcpu)->vmcb->save.rflags = rflags;
 750 }
 751
 752 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 753 {
 754         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 755
 756         switch (seg) {
 757         case VCPU_SREG_CS: return &save->cs;
 758         case VCPU_SREG_DS: return &save->ds;
 759         case VCPU_SREG_ES: return &save->es;
 760         case VCPU_SREG_FS: return &save->fs;
 761         case VCPU_SREG_GS: return &save->gs;
 762         case VCPU_SREG_SS: return &save->ss;
 763         case VCPU_SREG_TR: return &save->tr;
 764         case VCPU_SREG_LDTR: return &save->ldtr;
 765         }
 766         BUG();
 767         return NULL;
 768 }
 769
 770 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 771 {
 772         struct vmcb_seg *s = svm_seg(vcpu, seg);
 773
 774         return s->base;
 775 }
 776
 777 static void svm_get_segment(struct kvm_vcpu *vcpu,
 778                             struct kvm_segment *var, int seg)
 779 {
 780         struct vmcb_seg *s = svm_seg(vcpu, seg);
 781
 782         var->base = s->base;
 783         var->limit = s->limit;
 784         var->selector = s->selector;
 785         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 786         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 787         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 788         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 789         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 790         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 791         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 792         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 793         var->unusable = !var->present;
 794 }
 795
 796 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 797 {
 798         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 799
 800         return save->cpl;
 801 }
 802
 803 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 804 {
 805         struct vcpu_svm *svm = to_svm(vcpu);
 806
 807         dt->limit = svm->vmcb->save.idtr.limit;
 808         dt->base = svm->vmcb->save.idtr.base;
 809 }
 810
 811 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 812 {
 813         struct vcpu_svm *svm = to_svm(vcpu);
 814
 815         svm->vmcb->save.idtr.limit = dt->limit;
 816         svm->vmcb->save.idtr.base = dt->base ;
 817 }
 818
 819 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 820 {
 821         struct vcpu_svm *svm = to_svm(vcpu);
 822
 823         dt->limit = svm->vmcb->save.gdtr.limit;
 824         dt->base = svm->vmcb->save.gdtr.base;
 825 }
 826
 827 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 828 {
 829         struct vcpu_svm *svm = to_svm(vcpu);
 830
 831         svm->vmcb->save.gdtr.limit = dt->limit;
 832         svm->vmcb->save.gdtr.base = dt->base ;
 833 }
 834
 835 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 836 {
 837 }
 838
 839 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 840 {
 841         struct vcpu_svm *svm = to_svm(vcpu);
 842
 843 #ifdef CONFIG_X86_64
 844         if (vcpu->arch.shadow_efer & EFER_LME) {
 845                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 846                         vcpu->arch.shadow_efer |= EFER_LMA;
 847                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 848                 }
 849
 850                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 851                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 852                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 853                 }
 854         }
 855 #endif
 856         if (npt_enabled)
 857                 goto set;
 858
 859         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 860                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 861                 vcpu->fpu_active = 1;
 862         }
 863
 864         vcpu->arch.cr0 = cr0;
 865         cr0 |= X86_CR0_PG | X86_CR0_WP;
 866         if (!vcpu->fpu_active) {
 867                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 868                 cr0 |= X86_CR0_TS;
 869         }
 870 set:
 871         /*
 872          * re-enable caching here because the QEMU bios
 873          * does not do it - this results in some delay at
 874          * reboot
 875          */
 876         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 877         svm->vmcb->save.cr0 = cr0;
 878 }
 879
 880 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 881 {
 882         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 883
 884         vcpu->arch.cr4 = cr4;
 885         if (!npt_enabled)
 886                 cr4 |= X86_CR4_PAE;
 887         cr4 |= host_cr4_mce;
 888         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 889 }
 890
 891 static void svm_set_segment(struct kvm_vcpu *vcpu,
 892                             struct kvm_segment *var, int seg)
 893 {
 894         struct vcpu_svm *svm = to_svm(vcpu);
 895         struct vmcb_seg *s = svm_seg(vcpu, seg);
 896
 897         s->base = var->base;
 898         s->limit = var->limit;
 899         s->selector = var->selector;
 900         if (var->unusable)
 901                 s->attrib = 0;
 902         else {
 903                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 904                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 905                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 906                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 907                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 908                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 909                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 910                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 911         }
 912         if (seg == VCPU_SREG_CS)
 913                 svm->vmcb->save.cpl
 914                         = (svm->vmcb->save.cs.attrib
 915                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 916
 917 }
 918
 919 /* FIXME:
 920
 921         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 922         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 923
 924 */
 925
 926 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 927 {
 928         return -EOPNOTSUPP;
 929 }
 930
 931 static int svm_get_irq(struct kvm_vcpu *vcpu)
 932 {
 933         struct vcpu_svm *svm = to_svm(vcpu);
 934         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 935
 936         if (is_external_interrupt(exit_int_info))
 937                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 938         return -1;
 939 }
 940
 941 static void load_host_msrs(struct kvm_vcpu *vcpu)
 942 {
 943 #ifdef CONFIG_X86_64
 944         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 945 #endif
 946 }
 947
 948 static void save_host_msrs(struct kvm_vcpu *vcpu)
 949 {
 950 #ifdef CONFIG_X86_64
 951         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 952 #endif
 953 }
 954
 955 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 956 {
 957         if (svm_data->next_asid > svm_data->max_asid) {
 958                 ++svm_data->asid_generation;
 959                 svm_data->next_asid = 1;
 960                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 961         }
 962
 963         svm->vcpu.cpu = svm_data->cpu;
 964         svm->asid_generation = svm_data->asid_generation;
 965         svm->vmcb->control.asid = svm_data->next_asid++;
 966 }
 967
 968 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 969 {
 970         return to_svm(vcpu)->db_regs[dr];
 971 }
 972
 973 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 974                        int *exception)
 975 {
 976         struct vcpu_svm *svm = to_svm(vcpu);
 977
 978         *exception = 0;
 979
 980         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 981                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 982                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 983                 *exception = DB_VECTOR;
 984                 return;
 985         }
 986
 987         switch (dr) {
 988         case 0 ... 3:
 989                 svm->db_regs[dr] = value;
 990                 return;
 991         case 4 ... 5:
 992                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 993                         *exception = UD_VECTOR;
 994                         return;
 995                 }
 996         case 7: {
 997                 if (value & ~((1ULL << 32) - 1)) {
 998                         *exception = GP_VECTOR;
 999                         return;
1000                 }
1001                 svm->vmcb->save.dr7 = value;
1002                 return;
1003         }
1004         default:
1005                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1006                        __func__, dr);
1007                 *exception = UD_VECTOR;
1008                 return;
1009         }
1010 }
1011
1012 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1013 {
1014         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1015         struct kvm *kvm = svm->vcpu.kvm;
1016         u64 fault_address;
1017         u32 error_code;
1018
1019         if (!irqchip_in_kernel(kvm) &&
1020                 is_external_interrupt(exit_int_info))
1021                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1022
1023         fault_address  = svm->vmcb->control.exit_info_2;
1024         error_code = svm->vmcb->control.exit_info_1;
1025         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1026 }
1027
1028 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1029 {
1030         int er;
1031
1032         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1033         if (er != EMULATE_DONE)
1034                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1035         return 1;
1036 }
1037
1038 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1039 {
1040         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1041         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1042                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1043         svm->vcpu.fpu_active = 1;
1044
1045         return 1;
1046 }
1047
1048 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1049 {
1050         /*
1051          * On an #MC intercept the MCE handler is not called automatically in
1052          * the host. So do it by hand here.
1053          */
1054         asm volatile (
1055                 "int $0x12\n");
1056         /* not sure if we ever come back to this point */
1057
1058         return 1;
1059 }
1060
1061 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1062 {
1063         /*
1064          * VMCB is undefined after a SHUTDOWN intercept
1065          * so reinitialize it.
1066          */
1067         clear_page(svm->vmcb);
1068         init_vmcb(svm);
1069
1070         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1071         return 0;
1072 }
1073
1074 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1075 {
1076         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1077         int size, down, in, string, rep;
1078         unsigned port;
1079
1080         ++svm->vcpu.stat.io_exits;
1081
1082         svm->next_rip = svm->vmcb->control.exit_info_2;
1083
1084         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1085
1086         if (string) {
1087                 if (emulate_instruction(&svm->vcpu,
1088                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1089                         return 0;
1090                 return 1;
1091         }
1092
1093         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1094         port = io_info >> 16;
1095         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1096         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1097         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1098
1099         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1100 }
1101
1102 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1103 {
1104         return 1;
1105 }
1106
1107 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1108 {
1109         svm->next_rip = svm->vmcb->save.rip + 1;
1110         skip_emulated_instruction(&svm->vcpu);
1111         return kvm_emulate_halt(&svm->vcpu);
1112 }
1113
1114 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1115 {
1116         svm->next_rip = svm->vmcb->save.rip + 3;
1117         skip_emulated_instruction(&svm->vcpu);
1118         kvm_emulate_hypercall(&svm->vcpu);
1119         return 1;
1120 }
1121
1122 static int invalid_op_interception(struct vcpu_svm *svm,
1123                                    struct kvm_run *kvm_run)
1124 {
1125         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1126         return 1;
1127 }
1128
1129 static int task_switch_interception(struct vcpu_svm *svm,
1130                                     struct kvm_run *kvm_run)
1131 {
1132         u16 tss_selector;
1133
1134         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1135         if (svm->vmcb->control.exit_info_2 &
1136             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1137                 return kvm_task_switch(&svm->vcpu, tss_selector,
1138                                        TASK_SWITCH_IRET);
1139         if (svm->vmcb->control.exit_info_2 &
1140             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1141                 return kvm_task_switch(&svm->vcpu, tss_selector,
1142                                        TASK_SWITCH_JMP);
1143         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1144 }
1145
1146 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1147 {
1148         svm->next_rip = svm->vmcb->save.rip + 2;
1149         kvm_emulate_cpuid(&svm->vcpu);
1150         return 1;
1151 }
1152
1153 static int emulate_on_interception(struct vcpu_svm *svm,
1154                                    struct kvm_run *kvm_run)
1155 {
1156         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1157                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1158         return 1;
1159 }
1160
1161 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1162 {
1163         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1164         if (irqchip_in_kernel(svm->vcpu.kvm))
1165                 return 1;
1166         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1167         return 0;
1168 }
1169
1170 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1171 {
1172         struct vcpu_svm *svm = to_svm(vcpu);
1173
1174         switch (ecx) {
1175         case MSR_IA32_TIME_STAMP_COUNTER: {
1176                 u64 tsc;
1177
1178                 rdtscll(tsc);
1179                 *data = svm->vmcb->control.tsc_offset + tsc;
1180                 break;
1181         }
1182         case MSR_K6_STAR:
1183                 *data = svm->vmcb->save.star;
1184                 break;
1185 #ifdef CONFIG_X86_64
1186         case MSR_LSTAR:
1187                 *data = svm->vmcb->save.lstar;
1188                 break;
1189         case MSR_CSTAR:
1190                 *data = svm->vmcb->save.cstar;
1191                 break;
1192         case MSR_KERNEL_GS_BASE:
1193                 *data = svm->vmcb->save.kernel_gs_base;
1194                 break;
1195         case MSR_SYSCALL_MASK:
1196                 *data = svm->vmcb->save.sfmask;
1197                 break;
1198 #endif
1199         case MSR_IA32_SYSENTER_CS:
1200                 *data = svm->vmcb->save.sysenter_cs;
1201                 break;
1202         case MSR_IA32_SYSENTER_EIP:
1203                 *data = svm->vmcb->save.sysenter_eip;
1204                 break;
1205         case MSR_IA32_SYSENTER_ESP:
1206                 *data = svm->vmcb->save.sysenter_esp;
1207                 break;
1208         /* Nobody will change the following 5 values in the VMCB so
1209            we can safely return them on rdmsr. They will always be 0
1210            until LBRV is implemented. */
1211         case MSR_IA32_DEBUGCTLMSR:
1212                 *data = svm->vmcb->save.dbgctl;
1213                 break;
1214         case MSR_IA32_LASTBRANCHFROMIP:
1215                 *data = svm->vmcb->save.br_from;
1216                 break;
1217         case MSR_IA32_LASTBRANCHTOIP:
1218                 *data = svm->vmcb->save.br_to;
1219                 break;
1220         case MSR_IA32_LASTINTFROMIP:
1221                 *data = svm->vmcb->save.last_excp_from;
1222                 break;
1223         case MSR_IA32_LASTINTTOIP:
1224                 *data = svm->vmcb->save.last_excp_to;
1225                 break;
1226         default:
1227                 return kvm_get_msr_common(vcpu, ecx, data);
1228         }
1229         return 0;
1230 }
1231
1232 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1233 {
1234         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1235         u64 data;
1236
1237         if (svm_get_msr(&svm->vcpu, ecx, &data))
1238                 kvm_inject_gp(&svm->vcpu, 0);
1239         else {
1240                 svm->vmcb->save.rax = data & 0xffffffff;
1241                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1242                 svm->next_rip = svm->vmcb->save.rip + 2;
1243                 skip_emulated_instruction(&svm->vcpu);
1244         }
1245         return 1;
1246 }
1247
1248 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1249 {
1250         struct vcpu_svm *svm = to_svm(vcpu);
1251
1252         switch (ecx) {
1253         case MSR_IA32_TIME_STAMP_COUNTER: {
1254                 u64 tsc;
1255
1256                 rdtscll(tsc);
1257                 svm->vmcb->control.tsc_offset = data - tsc;
1258                 break;
1259         }
1260         case MSR_K6_STAR:
1261                 svm->vmcb->save.star = data;
1262                 break;
1263 #ifdef CONFIG_X86_64
1264         case MSR_LSTAR:
1265                 svm->vmcb->save.lstar = data;
1266                 break;
1267         case MSR_CSTAR:
1268                 svm->vmcb->save.cstar = data;
1269                 break;
1270         case MSR_KERNEL_GS_BASE:
1271                 svm->vmcb->save.kernel_gs_base = data;
1272                 break;
1273         case MSR_SYSCALL_MASK:
1274                 svm->vmcb->save.sfmask = data;
1275                 break;
1276 #endif
1277         case MSR_IA32_SYSENTER_CS:
1278                 svm->vmcb->save.sysenter_cs = data;
1279                 break;
1280         case MSR_IA32_SYSENTER_EIP:
1281                 svm->vmcb->save.sysenter_eip = data;
1282                 break;
1283         case MSR_IA32_SYSENTER_ESP:
1284                 svm->vmcb->save.sysenter_esp = data;
1285                 break;
1286         case MSR_IA32_DEBUGCTLMSR:
1287                 if (!svm_has(SVM_FEATURE_LBRV)) {
1288                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1289                                         __func__, data);
1290                         break;
1291                 }
1292                 if (data & DEBUGCTL_RESERVED_BITS)
1293                         return 1;
1294
1295                 svm->vmcb->save.dbgctl = data;
1296                 if (data & (1ULL<<0))
1297                         svm_enable_lbrv(svm);
1298                 else
1299                         svm_disable_lbrv(svm);
1300                 break;
1301         case MSR_K7_EVNTSEL0:
1302         case MSR_K7_EVNTSEL1:
1303         case MSR_K7_EVNTSEL2:
1304         case MSR_K7_EVNTSEL3:
1305                 /*
1306                  * only support writing 0 to the performance counters for now
1307                  * to make Windows happy. Should be replaced by a real
1308                  * performance counter emulation later.
1309                  */
1310                 if (data != 0)
1311                         goto unhandled;
1312                 break;
1313         default:
1314         unhandled:
1315                 return kvm_set_msr_common(vcpu, ecx, data);
1316         }
1317         return 0;
1318 }
1319
1320 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1321 {
1322         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1323         u64 data = (svm->vmcb->save.rax & -1u)
1324                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1325         svm->next_rip = svm->vmcb->save.rip + 2;
1326         if (svm_set_msr(&svm->vcpu, ecx, data))
1327                 kvm_inject_gp(&svm->vcpu, 0);
1328         else
1329                 skip_emulated_instruction(&svm->vcpu);
1330         return 1;
1331 }
1332
1333 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1334 {
1335         if (svm->vmcb->control.exit_info_1)
1336                 return wrmsr_interception(svm, kvm_run);
1337         else
1338                 return rdmsr_interception(svm, kvm_run);
1339 }
1340
1341 static int interrupt_window_interception(struct vcpu_svm *svm,
1342                                    struct kvm_run *kvm_run)
1343 {
1344         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1345         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1346         /*
1347          * If the user space waits to inject interrupts, exit as soon as
1348          * possible
1349          */
1350         if (kvm_run->request_interrupt_window &&
1351             !svm->vcpu.arch.irq_summary) {
1352                 ++svm->vcpu.stat.irq_window_exits;
1353                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1354                 return 0;
1355         }
1356
1357         return 1;
1358 }
1359
1360 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1361                                       struct kvm_run *kvm_run) = {
1362         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1363         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1364         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1365         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1366         /* for now: */
1367         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1368         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1369         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1370         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1371         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1372         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1373         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1374         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1375         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1376         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1377         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1378         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1379         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1380         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1381         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1382         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1383         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1384         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1385         [SVM_EXIT_INTR]                         = nop_on_interception,
1386         [SVM_EXIT_NMI]                          = nop_on_interception,
1387         [SVM_EXIT_SMI]                          = nop_on_interception,
1388         [SVM_EXIT_INIT]                         = nop_on_interception,
1389         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1390         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1391         [SVM_EXIT_CPUID]                        = cpuid_interception,
1392         [SVM_EXIT_INVD]                         = emulate_on_interception,
1393         [SVM_EXIT_HLT]                          = halt_interception,
1394         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1395         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1396         [SVM_EXIT_IOIO]                         = io_interception,
1397         [SVM_EXIT_MSR]                          = msr_interception,
1398         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1399         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1400         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1401         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1402         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1403         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1404         [SVM_EXIT_STGI]                         = invalid_op_interception,
1405         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1406         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1407         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1408         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1409         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1410         [SVM_EXIT_NPF]                          = pf_interception,
1411 };
1412
1413 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1414 {
1415         struct vcpu_svm *svm = to_svm(vcpu);
1416         u32 exit_code = svm->vmcb->control.exit_code;
1417
1418         if (npt_enabled) {
1419                 int mmu_reload = 0;
1420                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1421                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1422                         mmu_reload = 1;
1423                 }
1424                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1425                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1426                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1427                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1428                                 kvm_inject_gp(vcpu, 0);
1429                                 return 1;
1430                         }
1431                 }
1432                 if (mmu_reload) {
1433                         kvm_mmu_reset_context(vcpu);
1434                         kvm_mmu_load(vcpu);
1435                 }
1436         }
1437
1438         kvm_reput_irq(svm);
1439
1440         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1441                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1442                 kvm_run->fail_entry.hardware_entry_failure_reason
1443                         = svm->vmcb->control.exit_code;
1444                 return 0;
1445         }
1446
1447         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1448             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1449             exit_code != SVM_EXIT_NPF)
1450                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1451                        "exit_code 0x%x\n",
1452                        __func__, svm->vmcb->control.exit_int_info,
1453                        exit_code);
1454
1455         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1456             || !svm_exit_handlers[exit_code]) {
1457                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1458                 kvm_run->hw.hardware_exit_reason = exit_code;
1459                 return 0;
1460         }
1461
1462         return svm_exit_handlers[exit_code](svm, kvm_run);
1463 }
1464
1465 static void reload_tss(struct kvm_vcpu *vcpu)
1466 {
1467         int cpu = raw_smp_processor_id();
1468
1469         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1470         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1471         load_TR_desc();
1472 }
1473
1474 static void pre_svm_run(struct vcpu_svm *svm)
1475 {
1476         int cpu = raw_smp_processor_id();
1477
1478         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1479
1480         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1481         if (svm->vcpu.cpu != cpu ||
1482             svm->asid_generation != svm_data->asid_generation)
1483                 new_asid(svm, svm_data);
1484 }
1485
1486
1487 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1488 {
1489         struct vmcb_control_area *control;
1490
1491         control = &svm->vmcb->control;
1492         control->int_vector = irq;
1493         control->int_ctl &= ~V_INTR_PRIO_MASK;
1494         control->int_ctl |= V_IRQ_MASK |
1495                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1496 }
1497
1498 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1499 {
1500         struct vcpu_svm *svm = to_svm(vcpu);
1501
1502         svm_inject_irq(svm, irq);
1503 }
1504
1505 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1506 {
1507         struct vcpu_svm *svm = to_svm(vcpu);
1508         struct vmcb *vmcb = svm->vmcb;
1509         int intr_vector = -1;
1510
1511         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1512             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1513                 intr_vector = vmcb->control.exit_int_info &
1514                               SVM_EVTINJ_VEC_MASK;
1515                 vmcb->control.exit_int_info = 0;
1516                 svm_inject_irq(svm, intr_vector);
1517                 return;
1518         }
1519
1520         if (vmcb->control.int_ctl & V_IRQ_MASK)
1521                 return;
1522
1523         if (!kvm_cpu_has_interrupt(vcpu))
1524                 return;
1525
1526         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1527             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1528             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1529                 /* unable to deliver irq, set pending irq */
1530                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1531                 svm_inject_irq(svm, 0x0);
1532                 return;
1533         }
1534         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1535         intr_vector = kvm_cpu_get_interrupt(vcpu);
1536         svm_inject_irq(svm, intr_vector);
1537         kvm_timer_intr_post(vcpu, intr_vector);
1538 }
1539
1540 static void kvm_reput_irq(struct vcpu_svm *svm)
1541 {
1542         struct vmcb_control_area *control = &svm->vmcb->control;
1543
1544         if ((control->int_ctl & V_IRQ_MASK)
1545             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1546                 control->int_ctl &= ~V_IRQ_MASK;
1547                 push_irq(&svm->vcpu, control->int_vector);
1548         }
1549
1550         svm->vcpu.arch.interrupt_window_open =
1551                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1552 }
1553
1554 static void svm_do_inject_vector(struct vcpu_svm *svm)
1555 {
1556         struct kvm_vcpu *vcpu = &svm->vcpu;
1557         int word_index = __ffs(vcpu->arch.irq_summary);
1558         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1559         int irq = word_index * BITS_PER_LONG + bit_index;
1560
1561         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1562         if (!vcpu->arch.irq_pending[word_index])
1563                 clear_bit(word_index, &vcpu->arch.irq_summary);
1564         svm_inject_irq(svm, irq);
1565 }
1566
1567 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1568                                        struct kvm_run *kvm_run)
1569 {
1570         struct vcpu_svm *svm = to_svm(vcpu);
1571         struct vmcb_control_area *control = &svm->vmcb->control;
1572
1573         svm->vcpu.arch.interrupt_window_open =
1574                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1575                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1576
1577         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1578                 /*
1579                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1580                  */
1581                 svm_do_inject_vector(svm);
1582
1583         /*
1584          * Interrupts blocked.  Wait for unblock.
1585          */
1586         if (!svm->vcpu.arch.interrupt_window_open &&
1587             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1588                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1589          else
1590                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1591 }
1592
1593 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1594 {
1595         return 0;
1596 }
1597
1598 static void save_db_regs(unsigned long *db_regs)
1599 {
1600         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1601         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1602         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1603         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1604 }
1605
1606 static void load_db_regs(unsigned long *db_regs)
1607 {
1608         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1609         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1610         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1611         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1612 }
1613
1614 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1615 {
1616         force_new_asid(vcpu);
1617 }
1618
1619 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1620 {
1621 }
1622
1623 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1624 {
1625         struct vcpu_svm *svm = to_svm(vcpu);
1626         u64 cr8;
1627
1628         if (!irqchip_in_kernel(vcpu->kvm))
1629                 return;
1630
1631         cr8 = kvm_get_cr8(vcpu);
1632         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1633         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1634 }
1635
1636 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1637 {
1638         struct vcpu_svm *svm = to_svm(vcpu);
1639         u16 fs_selector;
1640         u16 gs_selector;
1641         u16 ldt_selector;
1642
1643         pre_svm_run(svm);
1644
1645         sync_lapic_to_cr8(vcpu);
1646
1647         save_host_msrs(vcpu);
1648         fs_selector = read_fs();
1649         gs_selector = read_gs();
1650         ldt_selector = read_ldt();
1651         svm->host_cr2 = kvm_read_cr2();
1652         svm->host_dr6 = read_dr6();
1653         svm->host_dr7 = read_dr7();
1654         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1655         /* required for live migration with NPT */
1656         if (npt_enabled)
1657                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1658
1659         if (svm->vmcb->save.dr7 & 0xff) {
1660                 write_dr7(0);
1661                 save_db_regs(svm->host_db_regs);
1662                 load_db_regs(svm->db_regs);
1663         }
1664
1665         clgi();
1666
1667         local_irq_enable();
1668
1669         asm volatile (
1670 #ifdef CONFIG_X86_64
1671                 "push %%rbp; \n\t"
1672 #else
1673                 "push %%ebp; \n\t"
1674 #endif
1675
1676 #ifdef CONFIG_X86_64
1677                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1678                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1679                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1680                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1681                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1682                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1683                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1684                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1685                 "mov %c[r10](%[svm]), %%r10 \n\t"
1686                 "mov %c[r11](%[svm]), %%r11 \n\t"
1687                 "mov %c[r12](%[svm]), %%r12 \n\t"
1688                 "mov %c[r13](%[svm]), %%r13 \n\t"
1689                 "mov %c[r14](%[svm]), %%r14 \n\t"
1690                 "mov %c[r15](%[svm]), %%r15 \n\t"
1691 #else
1692                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1693                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1694                 "mov %c[rdx](%[svm]), %%edx \n\t"
1695                 "mov %c[rsi](%[svm]), %%esi \n\t"
1696                 "mov %c[rdi](%[svm]), %%edi \n\t"
1697                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1698 #endif
1699
1700 #ifdef CONFIG_X86_64
1701                 /* Enter guest mode */
1702                 "push %%rax \n\t"
1703                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1704                 SVM_VMLOAD "\n\t"
1705                 SVM_VMRUN "\n\t"
1706                 SVM_VMSAVE "\n\t"
1707                 "pop %%rax \n\t"
1708 #else
1709                 /* Enter guest mode */
1710                 "push %%eax \n\t"
1711                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1712                 SVM_VMLOAD "\n\t"
1713                 SVM_VMRUN "\n\t"
1714                 SVM_VMSAVE "\n\t"
1715                 "pop %%eax \n\t"
1716 #endif
1717
1718                 /* Save guest registers, load host registers */
1719 #ifdef CONFIG_X86_64
1720                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1721                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1722                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1723                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1724                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1725                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1726                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1727                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1728                 "mov %%r10, %c[r10](%[svm]) \n\t"
1729                 "mov %%r11, %c[r11](%[svm]) \n\t"
1730                 "mov %%r12, %c[r12](%[svm]) \n\t"
1731                 "mov %%r13, %c[r13](%[svm]) \n\t"
1732                 "mov %%r14, %c[r14](%[svm]) \n\t"
1733                 "mov %%r15, %c[r15](%[svm]) \n\t"
1734
1735                 "pop  %%rbp; \n\t"
1736 #else
1737                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1738                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1739                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1740                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1741                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1742                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1743
1744                 "pop  %%ebp; \n\t"
1745 #endif
1746                 :
1747                 : [svm]"a"(svm),
1748                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1749                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1750                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1751                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1752                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1753                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1754                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1755 #ifdef CONFIG_X86_64
1756                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1757                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1758                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1759                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1760                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1761                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1762                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1763                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1764 #endif
1765                 : "cc", "memory"
1766 #ifdef CONFIG_X86_64
1767                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1768                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1769 #else
1770                 , "ebx", "ecx", "edx" , "esi", "edi"
1771 #endif
1772                 );
1773
1774         if ((svm->vmcb->save.dr7 & 0xff))
1775                 load_db_regs(svm->host_db_regs);
1776
1777         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1778
1779         write_dr6(svm->host_dr6);
1780         write_dr7(svm->host_dr7);
1781         kvm_write_cr2(svm->host_cr2);
1782
1783         load_fs(fs_selector);
1784         load_gs(gs_selector);
1785         load_ldt(ldt_selector);
1786         load_host_msrs(vcpu);
1787
1788         reload_tss(vcpu);
1789
1790         local_irq_disable();
1791
1792         stgi();
1793
1794         svm->next_rip = 0;
1795 }
1796
1797 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1798 {
1799         struct vcpu_svm *svm = to_svm(vcpu);
1800
1801         if (npt_enabled) {
1802                 svm->vmcb->control.nested_cr3 = root;
1803                 force_new_asid(vcpu);
1804                 return;
1805         }
1806
1807         svm->vmcb->save.cr3 = root;
1808         force_new_asid(vcpu);
1809
1810         if (vcpu->fpu_active) {
1811                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1812                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1813                 vcpu->fpu_active = 0;
1814         }
1815 }
1816
1817 static int is_disabled(void)
1818 {
1819         u64 vm_cr;
1820
1821         rdmsrl(MSR_VM_CR, vm_cr);
1822         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1823                 return 1;
1824
1825         return 0;
1826 }
1827
1828 static void
1829 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1830 {
1831         /*
1832          * Patch in the VMMCALL instruction:
1833          */
1834         hypercall[0] = 0x0f;
1835         hypercall[1] = 0x01;
1836         hypercall[2] = 0xd9;
1837 }
1838
1839 static void svm_check_processor_compat(void *rtn)
1840 {
1841         *(int *)rtn = 0;
1842 }
1843
1844 static bool svm_cpu_has_accelerated_tpr(void)
1845 {
1846         return false;
1847 }
1848
1849 static struct kvm_x86_ops svm_x86_ops = {
1850         .cpu_has_kvm_support = has_svm,
1851         .disabled_by_bios = is_disabled,
1852         .hardware_setup = svm_hardware_setup,
1853         .hardware_unsetup = svm_hardware_unsetup,
1854         .check_processor_compatibility = svm_check_processor_compat,
1855         .hardware_enable = svm_hardware_enable,
1856         .hardware_disable = svm_hardware_disable,
1857         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1858
1859         .vcpu_create = svm_create_vcpu,
1860         .vcpu_free = svm_free_vcpu,
1861         .vcpu_reset = svm_vcpu_reset,
1862
1863         .prepare_guest_switch = svm_prepare_guest_switch,
1864         .vcpu_load = svm_vcpu_load,
1865         .vcpu_put = svm_vcpu_put,
1866         .vcpu_decache = svm_vcpu_decache,
1867
1868         .set_guest_debug = svm_guest_debug,
1869         .get_msr = svm_get_msr,
1870         .set_msr = svm_set_msr,
1871         .get_segment_base = svm_get_segment_base,
1872         .get_segment = svm_get_segment,
1873         .set_segment = svm_set_segment,
1874         .get_cpl = svm_get_cpl,
1875         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1876         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1877         .set_cr0 = svm_set_cr0,
1878         .set_cr3 = svm_set_cr3,
1879         .set_cr4 = svm_set_cr4,
1880         .set_efer = svm_set_efer,
1881         .get_idt = svm_get_idt,
1882         .set_idt = svm_set_idt,
1883         .get_gdt = svm_get_gdt,
1884         .set_gdt = svm_set_gdt,
1885         .get_dr = svm_get_dr,
1886         .set_dr = svm_set_dr,
1887         .cache_regs = svm_cache_regs,
1888         .decache_regs = svm_decache_regs,
1889         .get_rflags = svm_get_rflags,
1890         .set_rflags = svm_set_rflags,
1891
1892         .tlb_flush = svm_flush_tlb,
1893
1894         .run = svm_vcpu_run,
1895         .handle_exit = handle_exit,
1896         .skip_emulated_instruction = skip_emulated_instruction,
1897         .patch_hypercall = svm_patch_hypercall,
1898         .get_irq = svm_get_irq,
1899         .set_irq = svm_set_irq,
1900         .queue_exception = svm_queue_exception,
1901         .exception_injected = svm_exception_injected,
1902         .inject_pending_irq = svm_intr_assist,
1903         .inject_pending_vectors = do_interrupt_requests,
1904
1905         .set_tss_addr = svm_set_tss_addr,
1906 };
1907
1908 static int __init svm_init(void)
1909 {
1910         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1911                               THIS_MODULE);
1912 }
1913
1914 static void __exit svm_exit(void)
1915 {
1916         kvm_exit();
1917 }
1918
1919 module_init(svm_init)
1920 module_exit(svm_exit)