err.no Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 static void kvm_reput_irq(struct vcpu_svm *svm);
  51
  52 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  53 {
  54         return container_of(vcpu, struct vcpu_svm, vcpu);
  55 }
  56
  57 unsigned long iopm_base;
  58 unsigned long msrpm_base;
  59
  60 struct kvm_ldttss_desc {
  61         u16 limit0;
  62         u16 base0;
  63         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  64         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  65         u32 base3;
  66         u32 zero1;
  67 } __attribute__((packed));
  68
  69 struct svm_cpu_data {
  70         int cpu;
  71
  72         u64 asid_generation;
  73         u32 max_asid;
  74         u32 next_asid;
  75         struct kvm_ldttss_desc *tss_desc;
  76
  77         struct page *save_area;
  78 };
  79
  80 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  81 static uint32_t svm_features;
  82
  83 struct svm_init_data {
  84         int cpu;
  85         int r;
  86 };
  87
  88 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  89
  90 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  91 #define MSRS_RANGE_SIZE 2048
  92 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  93
  94 #define MAX_INST_SIZE 15
  95
  96 static inline u32 svm_has(u32 feat)
  97 {
  98         return svm_features & feat;
  99 }
 100
 101 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 102 {
 103         int word_index = __ffs(vcpu->arch.irq_summary);
 104         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 105         int irq = word_index * BITS_PER_LONG + bit_index;
 106
 107         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 108         if (!vcpu->arch.irq_pending[word_index])
 109                 clear_bit(word_index, &vcpu->arch.irq_summary);
 110         return irq;
 111 }
 112
 113 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 114 {
 115         set_bit(irq, vcpu->arch.irq_pending);
 116         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 117 }
 118
 119 static inline void clgi(void)
 120 {
 121         asm volatile (SVM_CLGI);
 122 }
 123
 124 static inline void stgi(void)
 125 {
 126         asm volatile (SVM_STGI);
 127 }
 128
 129 static inline void invlpga(unsigned long addr, u32 asid)
 130 {
 131         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 132 }
 133
 134 static inline unsigned long kvm_read_cr2(void)
 135 {
 136         unsigned long cr2;
 137
 138         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 139         return cr2;
 140 }
 141
 142 static inline void kvm_write_cr2(unsigned long val)
 143 {
 144         asm volatile ("mov %0, %%cr2" :: "r" (val));
 145 }
 146
 147 static inline unsigned long read_dr6(void)
 148 {
 149         unsigned long dr6;
 150
 151         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 152         return dr6;
 153 }
 154
 155 static inline void write_dr6(unsigned long val)
 156 {
 157         asm volatile ("mov %0, %%dr6" :: "r" (val));
 158 }
 159
 160 static inline unsigned long read_dr7(void)
 161 {
 162         unsigned long dr7;
 163
 164         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 165         return dr7;
 166 }
 167
 168 static inline void write_dr7(unsigned long val)
 169 {
 170         asm volatile ("mov %0, %%dr7" :: "r" (val));
 171 }
 172
 173 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 174 {
 175         to_svm(vcpu)->asid_generation--;
 176 }
 177
 178 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 179 {
 180         force_new_asid(vcpu);
 181 }
 182
 183 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 184 {
 185         if (!(efer & EFER_LMA))
 186                 efer &= ~EFER_LME;
 187
 188         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 189         vcpu->arch.shadow_efer = efer;
 190 }
 191
 192 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 193                                 bool has_error_code, u32 error_code)
 194 {
 195         struct vcpu_svm *svm = to_svm(vcpu);
 196
 197         svm->vmcb->control.event_inj = nr
 198                 | SVM_EVTINJ_VALID
 199                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 200                 | SVM_EVTINJ_TYPE_EXEPT;
 201         svm->vmcb->control.event_inj_err = error_code;
 202 }
 203
 204 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 209 }
 210
 211 static int is_external_interrupt(u32 info)
 212 {
 213         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 214         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 215 }
 216
 217 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         if (!svm->next_rip) {
 222                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 223                 return;
 224         }
 225         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 226                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 227                        __FUNCTION__,
 228                        svm->vmcb->save.rip,
 229                        svm->next_rip);
 230
 231         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 232         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 233
 234         vcpu->arch.interrupt_window_open = 1;
 235 }
 236
 237 static int has_svm(void)
 238 {
 239         uint32_t eax, ebx, ecx, edx;
 240
 241         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 242                 printk(KERN_INFO "has_svm: not amd\n");
 243                 return 0;
 244         }
 245
 246         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 247         if (eax < SVM_CPUID_FUNC) {
 248                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 249                 return 0;
 250         }
 251
 252         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 253         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 254                 printk(KERN_DEBUG "has_svm: svm not available\n");
 255                 return 0;
 256         }
 257         return 1;
 258 }
 259
 260 static void svm_hardware_disable(void *garbage)
 261 {
 262         struct svm_cpu_data *svm_data
 263                 = per_cpu(svm_data, raw_smp_processor_id());
 264
 265         if (svm_data) {
 266                 uint64_t efer;
 267
 268                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 269                 rdmsrl(MSR_EFER, efer);
 270                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 271                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 272                 __free_page(svm_data->save_area);
 273                 kfree(svm_data);
 274         }
 275 }
 276
 277 static void svm_hardware_enable(void *garbage)
 278 {
 279
 280         struct svm_cpu_data *svm_data;
 281         uint64_t efer;
 282 #ifdef CONFIG_X86_64
 283         struct desc_ptr gdt_descr;
 284 #else
 285         struct desc_ptr gdt_descr;
 286 #endif
 287         struct desc_struct *gdt;
 288         int me = raw_smp_processor_id();
 289
 290         if (!has_svm()) {
 291                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 292                 return;
 293         }
 294         svm_data = per_cpu(svm_data, me);
 295
 296         if (!svm_data) {
 297                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 298                        me);
 299                 return;
 300         }
 301
 302         svm_data->asid_generation = 1;
 303         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 304         svm_data->next_asid = svm_data->max_asid + 1;
 305
 306         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 307         gdt = (struct desc_struct *)gdt_descr.address;
 308         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 309
 310         rdmsrl(MSR_EFER, efer);
 311         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 312
 313         wrmsrl(MSR_VM_HSAVE_PA,
 314                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 315 }
 316
 317 static int svm_cpu_init(int cpu)
 318 {
 319         struct svm_cpu_data *svm_data;
 320         int r;
 321
 322         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 323         if (!svm_data)
 324                 return -ENOMEM;
 325         svm_data->cpu = cpu;
 326         svm_data->save_area = alloc_page(GFP_KERNEL);
 327         r = -ENOMEM;
 328         if (!svm_data->save_area)
 329                 goto err_1;
 330
 331         per_cpu(svm_data, cpu) = svm_data;
 332
 333         return 0;
 334
 335 err_1:
 336         kfree(svm_data);
 337         return r;
 338
 339 }
 340
 341 static void set_msr_interception(u32 *msrpm, unsigned msr,
 342                                  int read, int write)
 343 {
 344         int i;
 345
 346         for (i = 0; i < NUM_MSR_MAPS; i++) {
 347                 if (msr >= msrpm_ranges[i] &&
 348                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 349                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 350                                           msrpm_ranges[i]) * 2;
 351
 352                         u32 *base = msrpm + (msr_offset / 32);
 353                         u32 msr_shift = msr_offset % 32;
 354                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 355                         *base = (*base & ~(0x3 << msr_shift)) |
 356                                 (mask << msr_shift);
 357                         return;
 358                 }
 359         }
 360         BUG();
 361 }
 362
 363 static __init int svm_hardware_setup(void)
 364 {
 365         int cpu;
 366         struct page *iopm_pages;
 367         struct page *msrpm_pages;
 368         void *iopm_va, *msrpm_va;
 369         int r;
 370
 371         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 372
 373         if (!iopm_pages)
 374                 return -ENOMEM;
 375
 376         iopm_va = page_address(iopm_pages);
 377         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 378         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 379         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 380
 381
 382         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 383
 384         r = -ENOMEM;
 385         if (!msrpm_pages)
 386                 goto err_1;
 387
 388         msrpm_va = page_address(msrpm_pages);
 389         memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 390         msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
 391
 392 #ifdef CONFIG_X86_64
 393         set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
 394         set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
 395         set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
 396         set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
 397         set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
 398         set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
 399 #endif
 400         set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
 401         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
 402         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
 403         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
 404
 405         if (boot_cpu_has(X86_FEATURE_NX))
 406                 kvm_enable_efer_bits(EFER_NX);
 407
 408         for_each_online_cpu(cpu) {
 409                 r = svm_cpu_init(cpu);
 410                 if (r)
 411                         goto err_2;
 412         }
 413
 414         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 415
 416         return 0;
 417
 418 err_2:
 419         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 420         msrpm_base = 0;
 421 err_1:
 422         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 423         iopm_base = 0;
 424         return r;
 425 }
 426
 427 static __exit void svm_hardware_unsetup(void)
 428 {
 429         __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 430         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 431         iopm_base = msrpm_base = 0;
 432 }
 433
 434 static void init_seg(struct vmcb_seg *seg)
 435 {
 436         seg->selector = 0;
 437         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 438                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 439         seg->limit = 0xffff;
 440         seg->base = 0;
 441 }
 442
 443 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 444 {
 445         seg->selector = 0;
 446         seg->attrib = SVM_SELECTOR_P_MASK | type;
 447         seg->limit = 0xffff;
 448         seg->base = 0;
 449 }
 450
 451 static void init_vmcb(struct vmcb *vmcb)
 452 {
 453         struct vmcb_control_area *control = &vmcb->control;
 454         struct vmcb_save_area *save = &vmcb->save;
 455
 456         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 457                                         INTERCEPT_CR3_MASK |
 458                                         INTERCEPT_CR4_MASK |
 459                                         INTERCEPT_CR8_MASK;
 460
 461         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 462                                         INTERCEPT_CR3_MASK |
 463                                         INTERCEPT_CR4_MASK |
 464                                         INTERCEPT_CR8_MASK;
 465
 466         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 467                                         INTERCEPT_DR1_MASK |
 468                                         INTERCEPT_DR2_MASK |
 469                                         INTERCEPT_DR3_MASK;
 470
 471         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 472                                         INTERCEPT_DR1_MASK |
 473                                         INTERCEPT_DR2_MASK |
 474                                         INTERCEPT_DR3_MASK |
 475                                         INTERCEPT_DR5_MASK |
 476                                         INTERCEPT_DR7_MASK;
 477
 478         control->intercept_exceptions = (1 << PF_VECTOR) |
 479                                         (1 << UD_VECTOR);
 480
 481
 482         control->intercept =    (1ULL << INTERCEPT_INTR) |
 483                                 (1ULL << INTERCEPT_NMI) |
 484                                 (1ULL << INTERCEPT_SMI) |
 485                 /*
 486                  * selective cr0 intercept bug?
 487                  *      0:   0f 22 d8                mov    %eax,%cr3
 488                  *      3:   0f 20 c0                mov    %cr0,%eax
 489                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 490                  *      b:   0f 22 c0                mov    %eax,%cr0
 491                  * set cr3 ->interception
 492                  * get cr0 ->interception
 493                  * set cr0 -> no interception
 494                  */
 495                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 496                                 (1ULL << INTERCEPT_CPUID) |
 497                                 (1ULL << INTERCEPT_INVD) |
 498                                 (1ULL << INTERCEPT_HLT) |
 499                                 (1ULL << INTERCEPT_INVLPGA) |
 500                                 (1ULL << INTERCEPT_IOIO_PROT) |
 501                                 (1ULL << INTERCEPT_MSR_PROT) |
 502                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 503                                 (1ULL << INTERCEPT_SHUTDOWN) |
 504                                 (1ULL << INTERCEPT_VMRUN) |
 505                                 (1ULL << INTERCEPT_VMMCALL) |
 506                                 (1ULL << INTERCEPT_VMLOAD) |
 507                                 (1ULL << INTERCEPT_VMSAVE) |
 508                                 (1ULL << INTERCEPT_STGI) |
 509                                 (1ULL << INTERCEPT_CLGI) |
 510                                 (1ULL << INTERCEPT_SKINIT) |
 511                                 (1ULL << INTERCEPT_WBINVD) |
 512                                 (1ULL << INTERCEPT_MONITOR) |
 513                                 (1ULL << INTERCEPT_MWAIT);
 514
 515         control->iopm_base_pa = iopm_base;
 516         control->msrpm_base_pa = msrpm_base;
 517         control->tsc_offset = 0;
 518         control->int_ctl = V_INTR_MASKING_MASK;
 519
 520         init_seg(&save->es);
 521         init_seg(&save->ss);
 522         init_seg(&save->ds);
 523         init_seg(&save->fs);
 524         init_seg(&save->gs);
 525
 526         save->cs.selector = 0xf000;
 527         /* Executable/Readable Code Segment */
 528         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 529                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 530         save->cs.limit = 0xffff;
 531         /*
 532          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 533          * be consistent with it.
 534          *
 535          * Replace when we have real mode working for vmx.
 536          */
 537         save->cs.base = 0xf0000;
 538
 539         save->gdtr.limit = 0xffff;
 540         save->idtr.limit = 0xffff;
 541
 542         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 543         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 544
 545         save->efer = MSR_EFER_SVME_MASK;
 546         save->dr6 = 0xffff0ff0;
 547         save->dr7 = 0x400;
 548         save->rflags = 2;
 549         save->rip = 0x0000fff0;
 550
 551         /*
 552          * cr0 val on cpu init should be 0x60000010, we enable cpu
 553          * cache by default. the orderly way is to enable cache in bios.
 554          */
 555         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 556         save->cr4 = X86_CR4_PAE;
 557         /* rdx = ?? */
 558 }
 559
 560 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 561 {
 562         struct vcpu_svm *svm = to_svm(vcpu);
 563
 564         init_vmcb(svm->vmcb);
 565
 566         if (vcpu->vcpu_id != 0) {
 567                 svm->vmcb->save.rip = 0;
 568                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 569                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 570         }
 571
 572         return 0;
 573 }
 574
 575 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 576 {
 577         struct vcpu_svm *svm;
 578         struct page *page;
 579         int err;
 580
 581         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 582         if (!svm) {
 583                 err = -ENOMEM;
 584                 goto out;
 585         }
 586
 587         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 588         if (err)
 589                 goto free_svm;
 590
 591         page = alloc_page(GFP_KERNEL);
 592         if (!page) {
 593                 err = -ENOMEM;
 594                 goto uninit;
 595         }
 596
 597         svm->vmcb = page_address(page);
 598         clear_page(svm->vmcb);
 599         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 600         svm->asid_generation = 0;
 601         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 602         init_vmcb(svm->vmcb);
 603
 604         fx_init(&svm->vcpu);
 605         svm->vcpu.fpu_active = 1;
 606         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 607         if (svm->vcpu.vcpu_id == 0)
 608                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 609
 610         return &svm->vcpu;
 611
 612 uninit:
 613         kvm_vcpu_uninit(&svm->vcpu);
 614 free_svm:
 615         kmem_cache_free(kvm_vcpu_cache, svm);
 616 out:
 617         return ERR_PTR(err);
 618 }
 619
 620 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 621 {
 622         struct vcpu_svm *svm = to_svm(vcpu);
 623
 624         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 625         kvm_vcpu_uninit(vcpu);
 626         kmem_cache_free(kvm_vcpu_cache, svm);
 627 }
 628
 629 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 630 {
 631         struct vcpu_svm *svm = to_svm(vcpu);
 632         int i;
 633
 634         if (unlikely(cpu != vcpu->cpu)) {
 635                 u64 tsc_this, delta;
 636
 637                 /*
 638                  * Make sure that the guest sees a monotonically
 639                  * increasing TSC.
 640                  */
 641                 rdtscll(tsc_this);
 642                 delta = vcpu->arch.host_tsc - tsc_this;
 643                 svm->vmcb->control.tsc_offset += delta;
 644                 vcpu->cpu = cpu;
 645                 kvm_migrate_apic_timer(vcpu);
 646         }
 647
 648         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 649                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 650 }
 651
 652 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 653 {
 654         struct vcpu_svm *svm = to_svm(vcpu);
 655         int i;
 656
 657         ++vcpu->stat.host_state_reload;
 658         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 659                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 660
 661         rdtscll(vcpu->arch.host_tsc);
 662 }
 663
 664 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 665 {
 666 }
 667
 668 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 669 {
 670         struct vcpu_svm *svm = to_svm(vcpu);
 671
 672         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 673         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 674         vcpu->arch.rip = svm->vmcb->save.rip;
 675 }
 676
 677 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 678 {
 679         struct vcpu_svm *svm = to_svm(vcpu);
 680         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 681         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 682         svm->vmcb->save.rip = vcpu->arch.rip;
 683 }
 684
 685 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 686 {
 687         return to_svm(vcpu)->vmcb->save.rflags;
 688 }
 689
 690 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 691 {
 692         to_svm(vcpu)->vmcb->save.rflags = rflags;
 693 }
 694
 695 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 696 {
 697         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 698
 699         switch (seg) {
 700         case VCPU_SREG_CS: return &save->cs;
 701         case VCPU_SREG_DS: return &save->ds;
 702         case VCPU_SREG_ES: return &save->es;
 703         case VCPU_SREG_FS: return &save->fs;
 704         case VCPU_SREG_GS: return &save->gs;
 705         case VCPU_SREG_SS: return &save->ss;
 706         case VCPU_SREG_TR: return &save->tr;
 707         case VCPU_SREG_LDTR: return &save->ldtr;
 708         }
 709         BUG();
 710         return NULL;
 711 }
 712
 713 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 714 {
 715         struct vmcb_seg *s = svm_seg(vcpu, seg);
 716
 717         return s->base;
 718 }
 719
 720 static void svm_get_segment(struct kvm_vcpu *vcpu,
 721                             struct kvm_segment *var, int seg)
 722 {
 723         struct vmcb_seg *s = svm_seg(vcpu, seg);
 724
 725         var->base = s->base;
 726         var->limit = s->limit;
 727         var->selector = s->selector;
 728         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 729         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 730         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 731         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 732         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 733         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 734         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 735         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 736         var->unusable = !var->present;
 737 }
 738
 739 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 740 {
 741         struct vcpu_svm *svm = to_svm(vcpu);
 742
 743         dt->limit = svm->vmcb->save.idtr.limit;
 744         dt->base = svm->vmcb->save.idtr.base;
 745 }
 746
 747 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 748 {
 749         struct vcpu_svm *svm = to_svm(vcpu);
 750
 751         svm->vmcb->save.idtr.limit = dt->limit;
 752         svm->vmcb->save.idtr.base = dt->base ;
 753 }
 754
 755 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 756 {
 757         struct vcpu_svm *svm = to_svm(vcpu);
 758
 759         dt->limit = svm->vmcb->save.gdtr.limit;
 760         dt->base = svm->vmcb->save.gdtr.base;
 761 }
 762
 763 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 764 {
 765         struct vcpu_svm *svm = to_svm(vcpu);
 766
 767         svm->vmcb->save.gdtr.limit = dt->limit;
 768         svm->vmcb->save.gdtr.base = dt->base ;
 769 }
 770
 771 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 772 {
 773 }
 774
 775 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 776 {
 777         struct vcpu_svm *svm = to_svm(vcpu);
 778
 779 #ifdef CONFIG_X86_64
 780         if (vcpu->arch.shadow_efer & EFER_LME) {
 781                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 782                         vcpu->arch.shadow_efer |= EFER_LMA;
 783                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 784                 }
 785
 786                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 787                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 788                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 789                 }
 790         }
 791 #endif
 792         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 793                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 794                 vcpu->fpu_active = 1;
 795         }
 796
 797         vcpu->arch.cr0 = cr0;
 798         cr0 |= X86_CR0_PG | X86_CR0_WP;
 799         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 800         if (!vcpu->fpu_active) {
 801                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 802                 cr0 |= X86_CR0_TS;
 803         }
 804         svm->vmcb->save.cr0 = cr0;
 805 }
 806
 807 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 808 {
 809        vcpu->arch.cr4 = cr4;
 810        to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
 811 }
 812
 813 static void svm_set_segment(struct kvm_vcpu *vcpu,
 814                             struct kvm_segment *var, int seg)
 815 {
 816         struct vcpu_svm *svm = to_svm(vcpu);
 817         struct vmcb_seg *s = svm_seg(vcpu, seg);
 818
 819         s->base = var->base;
 820         s->limit = var->limit;
 821         s->selector = var->selector;
 822         if (var->unusable)
 823                 s->attrib = 0;
 824         else {
 825                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 826                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 827                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 828                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 829                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 830                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 831                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 832                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 833         }
 834         if (seg == VCPU_SREG_CS)
 835                 svm->vmcb->save.cpl
 836                         = (svm->vmcb->save.cs.attrib
 837                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 838
 839 }
 840
 841 /* FIXME:
 842
 843         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 844         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 845
 846 */
 847
 848 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 849 {
 850         return -EOPNOTSUPP;
 851 }
 852
 853 static int svm_get_irq(struct kvm_vcpu *vcpu)
 854 {
 855         struct vcpu_svm *svm = to_svm(vcpu);
 856         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 857
 858         if (is_external_interrupt(exit_int_info))
 859                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 860         return -1;
 861 }
 862
 863 static void load_host_msrs(struct kvm_vcpu *vcpu)
 864 {
 865 #ifdef CONFIG_X86_64
 866         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 867 #endif
 868 }
 869
 870 static void save_host_msrs(struct kvm_vcpu *vcpu)
 871 {
 872 #ifdef CONFIG_X86_64
 873         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 874 #endif
 875 }
 876
 877 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 878 {
 879         if (svm_data->next_asid > svm_data->max_asid) {
 880                 ++svm_data->asid_generation;
 881                 svm_data->next_asid = 1;
 882                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 883         }
 884
 885         svm->vcpu.cpu = svm_data->cpu;
 886         svm->asid_generation = svm_data->asid_generation;
 887         svm->vmcb->control.asid = svm_data->next_asid++;
 888 }
 889
 890 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 891 {
 892         return to_svm(vcpu)->db_regs[dr];
 893 }
 894
 895 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 896                        int *exception)
 897 {
 898         struct vcpu_svm *svm = to_svm(vcpu);
 899
 900         *exception = 0;
 901
 902         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 903                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 904                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 905                 *exception = DB_VECTOR;
 906                 return;
 907         }
 908
 909         switch (dr) {
 910         case 0 ... 3:
 911                 svm->db_regs[dr] = value;
 912                 return;
 913         case 4 ... 5:
 914                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 915                         *exception = UD_VECTOR;
 916                         return;
 917                 }
 918         case 7: {
 919                 if (value & ~((1ULL << 32) - 1)) {
 920                         *exception = GP_VECTOR;
 921                         return;
 922                 }
 923                 svm->vmcb->save.dr7 = value;
 924                 return;
 925         }
 926         default:
 927                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 928                        __FUNCTION__, dr);
 929                 *exception = UD_VECTOR;
 930                 return;
 931         }
 932 }
 933
 934 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 935 {
 936         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 937         struct kvm *kvm = svm->vcpu.kvm;
 938         u64 fault_address;
 939         u32 error_code;
 940
 941         if (!irqchip_in_kernel(kvm) &&
 942                 is_external_interrupt(exit_int_info))
 943                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 944
 945         fault_address  = svm->vmcb->control.exit_info_2;
 946         error_code = svm->vmcb->control.exit_info_1;
 947         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 948 }
 949
 950 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 951 {
 952         int er;
 953
 954         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
 955         if (er != EMULATE_DONE)
 956                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
 957         return 1;
 958 }
 959
 960 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 961 {
 962         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 963         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
 964                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
 965         svm->vcpu.fpu_active = 1;
 966
 967         return 1;
 968 }
 969
 970 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 971 {
 972         /*
 973          * VMCB is undefined after a SHUTDOWN intercept
 974          * so reinitialize it.
 975          */
 976         clear_page(svm->vmcb);
 977         init_vmcb(svm->vmcb);
 978
 979         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
 980         return 0;
 981 }
 982
 983 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 984 {
 985         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
 986         int size, down, in, string, rep;
 987         unsigned port;
 988
 989         ++svm->vcpu.stat.io_exits;
 990
 991         svm->next_rip = svm->vmcb->control.exit_info_2;
 992
 993         string = (io_info & SVM_IOIO_STR_MASK) != 0;
 994
 995         if (string) {
 996                 if (emulate_instruction(&svm->vcpu,
 997                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
 998                         return 0;
 999                 return 1;
1000         }
1001
1002         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1003         port = io_info >> 16;
1004         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1005         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1006         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1007
1008         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1009 }
1010
1011 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1012 {
1013         return 1;
1014 }
1015
1016 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1017 {
1018         svm->next_rip = svm->vmcb->save.rip + 1;
1019         skip_emulated_instruction(&svm->vcpu);
1020         return kvm_emulate_halt(&svm->vcpu);
1021 }
1022
1023 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1024 {
1025         svm->next_rip = svm->vmcb->save.rip + 3;
1026         skip_emulated_instruction(&svm->vcpu);
1027         kvm_emulate_hypercall(&svm->vcpu);
1028         return 1;
1029 }
1030
1031 static int invalid_op_interception(struct vcpu_svm *svm,
1032                                    struct kvm_run *kvm_run)
1033 {
1034         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1035         return 1;
1036 }
1037
1038 static int task_switch_interception(struct vcpu_svm *svm,
1039                                     struct kvm_run *kvm_run)
1040 {
1041         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1042         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1043         return 0;
1044 }
1045
1046 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1047 {
1048         svm->next_rip = svm->vmcb->save.rip + 2;
1049         kvm_emulate_cpuid(&svm->vcpu);
1050         return 1;
1051 }
1052
1053 static int emulate_on_interception(struct vcpu_svm *svm,
1054                                    struct kvm_run *kvm_run)
1055 {
1056         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1057                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1058         return 1;
1059 }
1060
1061 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1062 {
1063         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1064         if (irqchip_in_kernel(svm->vcpu.kvm))
1065                 return 1;
1066         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1067         return 0;
1068 }
1069
1070 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1071 {
1072         struct vcpu_svm *svm = to_svm(vcpu);
1073
1074         switch (ecx) {
1075         case MSR_IA32_TIME_STAMP_COUNTER: {
1076                 u64 tsc;
1077
1078                 rdtscll(tsc);
1079                 *data = svm->vmcb->control.tsc_offset + tsc;
1080                 break;
1081         }
1082         case MSR_K6_STAR:
1083                 *data = svm->vmcb->save.star;
1084                 break;
1085 #ifdef CONFIG_X86_64
1086         case MSR_LSTAR:
1087                 *data = svm->vmcb->save.lstar;
1088                 break;
1089         case MSR_CSTAR:
1090                 *data = svm->vmcb->save.cstar;
1091                 break;
1092         case MSR_KERNEL_GS_BASE:
1093                 *data = svm->vmcb->save.kernel_gs_base;
1094                 break;
1095         case MSR_SYSCALL_MASK:
1096                 *data = svm->vmcb->save.sfmask;
1097                 break;
1098 #endif
1099         case MSR_IA32_SYSENTER_CS:
1100                 *data = svm->vmcb->save.sysenter_cs;
1101                 break;
1102         case MSR_IA32_SYSENTER_EIP:
1103                 *data = svm->vmcb->save.sysenter_eip;
1104                 break;
1105         case MSR_IA32_SYSENTER_ESP:
1106                 *data = svm->vmcb->save.sysenter_esp;
1107                 break;
1108         /* Nobody will change the following 5 values in the VMCB so
1109            we can safely return them on rdmsr. They will always be 0
1110            until LBRV is implemented. */
1111         case MSR_IA32_DEBUGCTLMSR:
1112                 *data = svm->vmcb->save.dbgctl;
1113                 break;
1114         case MSR_IA32_LASTBRANCHFROMIP:
1115                 *data = svm->vmcb->save.br_from;
1116                 break;
1117         case MSR_IA32_LASTBRANCHTOIP:
1118                 *data = svm->vmcb->save.br_to;
1119                 break;
1120         case MSR_IA32_LASTINTFROMIP:
1121                 *data = svm->vmcb->save.last_excp_from;
1122                 break;
1123         case MSR_IA32_LASTINTTOIP:
1124                 *data = svm->vmcb->save.last_excp_to;
1125                 break;
1126         default:
1127                 return kvm_get_msr_common(vcpu, ecx, data);
1128         }
1129         return 0;
1130 }
1131
1132 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1133 {
1134         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1135         u64 data;
1136
1137         if (svm_get_msr(&svm->vcpu, ecx, &data))
1138                 kvm_inject_gp(&svm->vcpu, 0);
1139         else {
1140                 svm->vmcb->save.rax = data & 0xffffffff;
1141                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1142                 svm->next_rip = svm->vmcb->save.rip + 2;
1143                 skip_emulated_instruction(&svm->vcpu);
1144         }
1145         return 1;
1146 }
1147
1148 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1149 {
1150         struct vcpu_svm *svm = to_svm(vcpu);
1151
1152         switch (ecx) {
1153         case MSR_IA32_TIME_STAMP_COUNTER: {
1154                 u64 tsc;
1155
1156                 rdtscll(tsc);
1157                 svm->vmcb->control.tsc_offset = data - tsc;
1158                 break;
1159         }
1160         case MSR_K6_STAR:
1161                 svm->vmcb->save.star = data;
1162                 break;
1163 #ifdef CONFIG_X86_64
1164         case MSR_LSTAR:
1165                 svm->vmcb->save.lstar = data;
1166                 break;
1167         case MSR_CSTAR:
1168                 svm->vmcb->save.cstar = data;
1169                 break;
1170         case MSR_KERNEL_GS_BASE:
1171                 svm->vmcb->save.kernel_gs_base = data;
1172                 break;
1173         case MSR_SYSCALL_MASK:
1174                 svm->vmcb->save.sfmask = data;
1175                 break;
1176 #endif
1177         case MSR_IA32_SYSENTER_CS:
1178                 svm->vmcb->save.sysenter_cs = data;
1179                 break;
1180         case MSR_IA32_SYSENTER_EIP:
1181                 svm->vmcb->save.sysenter_eip = data;
1182                 break;
1183         case MSR_IA32_SYSENTER_ESP:
1184                 svm->vmcb->save.sysenter_esp = data;
1185                 break;
1186         case MSR_IA32_DEBUGCTLMSR:
1187                 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1188                                 __FUNCTION__, data);
1189                 break;
1190         case MSR_K7_EVNTSEL0:
1191         case MSR_K7_EVNTSEL1:
1192         case MSR_K7_EVNTSEL2:
1193         case MSR_K7_EVNTSEL3:
1194                 /*
1195                  * only support writing 0 to the performance counters for now
1196                  * to make Windows happy. Should be replaced by a real
1197                  * performance counter emulation later.
1198                  */
1199                 if (data != 0)
1200                         goto unhandled;
1201                 break;
1202         default:
1203         unhandled:
1204                 return kvm_set_msr_common(vcpu, ecx, data);
1205         }
1206         return 0;
1207 }
1208
1209 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1210 {
1211         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1212         u64 data = (svm->vmcb->save.rax & -1u)
1213                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1214         svm->next_rip = svm->vmcb->save.rip + 2;
1215         if (svm_set_msr(&svm->vcpu, ecx, data))
1216                 kvm_inject_gp(&svm->vcpu, 0);
1217         else
1218                 skip_emulated_instruction(&svm->vcpu);
1219         return 1;
1220 }
1221
1222 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1223 {
1224         if (svm->vmcb->control.exit_info_1)
1225                 return wrmsr_interception(svm, kvm_run);
1226         else
1227                 return rdmsr_interception(svm, kvm_run);
1228 }
1229
1230 static int interrupt_window_interception(struct vcpu_svm *svm,
1231                                    struct kvm_run *kvm_run)
1232 {
1233         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1234         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1235         /*
1236          * If the user space waits to inject interrupts, exit as soon as
1237          * possible
1238          */
1239         if (kvm_run->request_interrupt_window &&
1240             !svm->vcpu.arch.irq_summary) {
1241                 ++svm->vcpu.stat.irq_window_exits;
1242                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1243                 return 0;
1244         }
1245
1246         return 1;
1247 }
1248
1249 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1250                                       struct kvm_run *kvm_run) = {
1251         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1252         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1253         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1254         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1255         /* for now: */
1256         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1257         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1258         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1259         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1260         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1261         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1262         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1263         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1264         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1265         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1266         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1267         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1268         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1269         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1270         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1271         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1272         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1273         [SVM_EXIT_INTR]                         = nop_on_interception,
1274         [SVM_EXIT_NMI]                          = nop_on_interception,
1275         [SVM_EXIT_SMI]                          = nop_on_interception,
1276         [SVM_EXIT_INIT]                         = nop_on_interception,
1277         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1278         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1279         [SVM_EXIT_CPUID]                        = cpuid_interception,
1280         [SVM_EXIT_INVD]                         = emulate_on_interception,
1281         [SVM_EXIT_HLT]                          = halt_interception,
1282         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1283         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1284         [SVM_EXIT_IOIO]                         = io_interception,
1285         [SVM_EXIT_MSR]                          = msr_interception,
1286         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1287         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1288         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1289         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1290         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1291         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1292         [SVM_EXIT_STGI]                         = invalid_op_interception,
1293         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1294         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1295         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1296         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1297         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1298 };
1299
1300
1301 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1302 {
1303         struct vcpu_svm *svm = to_svm(vcpu);
1304         u32 exit_code = svm->vmcb->control.exit_code;
1305
1306         kvm_reput_irq(svm);
1307
1308         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1309                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1310                 kvm_run->fail_entry.hardware_entry_failure_reason
1311                         = svm->vmcb->control.exit_code;
1312                 return 0;
1313         }
1314
1315         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1316             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1317                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1318                        "exit_code 0x%x\n",
1319                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1320                        exit_code);
1321
1322         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1323             || !svm_exit_handlers[exit_code]) {
1324                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1325                 kvm_run->hw.hardware_exit_reason = exit_code;
1326                 return 0;
1327         }
1328
1329         return svm_exit_handlers[exit_code](svm, kvm_run);
1330 }
1331
1332 static void reload_tss(struct kvm_vcpu *vcpu)
1333 {
1334         int cpu = raw_smp_processor_id();
1335
1336         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1337         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1338         load_TR_desc();
1339 }
1340
1341 static void pre_svm_run(struct vcpu_svm *svm)
1342 {
1343         int cpu = raw_smp_processor_id();
1344
1345         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1346
1347         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1348         if (svm->vcpu.cpu != cpu ||
1349             svm->asid_generation != svm_data->asid_generation)
1350                 new_asid(svm, svm_data);
1351 }
1352
1353
1354 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1355 {
1356         struct vmcb_control_area *control;
1357
1358         control = &svm->vmcb->control;
1359         control->int_vector = irq;
1360         control->int_ctl &= ~V_INTR_PRIO_MASK;
1361         control->int_ctl |= V_IRQ_MASK |
1362                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1363 }
1364
1365 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1366 {
1367         struct vcpu_svm *svm = to_svm(vcpu);
1368
1369         svm_inject_irq(svm, irq);
1370 }
1371
1372 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1373 {
1374         struct vcpu_svm *svm = to_svm(vcpu);
1375         struct vmcb *vmcb = svm->vmcb;
1376         int intr_vector = -1;
1377
1378         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1379             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1380                 intr_vector = vmcb->control.exit_int_info &
1381                               SVM_EVTINJ_VEC_MASK;
1382                 vmcb->control.exit_int_info = 0;
1383                 svm_inject_irq(svm, intr_vector);
1384                 return;
1385         }
1386
1387         if (vmcb->control.int_ctl & V_IRQ_MASK)
1388                 return;
1389
1390         if (!kvm_cpu_has_interrupt(vcpu))
1391                 return;
1392
1393         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1394             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1395             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1396                 /* unable to deliver irq, set pending irq */
1397                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1398                 svm_inject_irq(svm, 0x0);
1399                 return;
1400         }
1401         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1402         intr_vector = kvm_cpu_get_interrupt(vcpu);
1403         svm_inject_irq(svm, intr_vector);
1404         kvm_timer_intr_post(vcpu, intr_vector);
1405 }
1406
1407 static void kvm_reput_irq(struct vcpu_svm *svm)
1408 {
1409         struct vmcb_control_area *control = &svm->vmcb->control;
1410
1411         if ((control->int_ctl & V_IRQ_MASK)
1412             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1413                 control->int_ctl &= ~V_IRQ_MASK;
1414                 push_irq(&svm->vcpu, control->int_vector);
1415         }
1416
1417         svm->vcpu.arch.interrupt_window_open =
1418                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1419 }
1420
1421 static void svm_do_inject_vector(struct vcpu_svm *svm)
1422 {
1423         struct kvm_vcpu *vcpu = &svm->vcpu;
1424         int word_index = __ffs(vcpu->arch.irq_summary);
1425         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1426         int irq = word_index * BITS_PER_LONG + bit_index;
1427
1428         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1429         if (!vcpu->arch.irq_pending[word_index])
1430                 clear_bit(word_index, &vcpu->arch.irq_summary);
1431         svm_inject_irq(svm, irq);
1432 }
1433
1434 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1435                                        struct kvm_run *kvm_run)
1436 {
1437         struct vcpu_svm *svm = to_svm(vcpu);
1438         struct vmcb_control_area *control = &svm->vmcb->control;
1439
1440         svm->vcpu.arch.interrupt_window_open =
1441                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1442                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1443
1444         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1445                 /*
1446                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1447                  */
1448                 svm_do_inject_vector(svm);
1449
1450         /*
1451          * Interrupts blocked.  Wait for unblock.
1452          */
1453         if (!svm->vcpu.arch.interrupt_window_open &&
1454             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1455                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1456          else
1457                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1458 }
1459
1460 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1461 {
1462         return 0;
1463 }
1464
1465 static void save_db_regs(unsigned long *db_regs)
1466 {
1467         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1468         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1469         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1470         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1471 }
1472
1473 static void load_db_regs(unsigned long *db_regs)
1474 {
1475         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1476         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1477         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1478         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1479 }
1480
1481 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1482 {
1483         force_new_asid(vcpu);
1484 }
1485
1486 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1487 {
1488 }
1489
1490 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1491 {
1492         struct vcpu_svm *svm = to_svm(vcpu);
1493         u16 fs_selector;
1494         u16 gs_selector;
1495         u16 ldt_selector;
1496
1497         pre_svm_run(svm);
1498
1499         save_host_msrs(vcpu);
1500         fs_selector = read_fs();
1501         gs_selector = read_gs();
1502         ldt_selector = read_ldt();
1503         svm->host_cr2 = kvm_read_cr2();
1504         svm->host_dr6 = read_dr6();
1505         svm->host_dr7 = read_dr7();
1506         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1507
1508         if (svm->vmcb->save.dr7 & 0xff) {
1509                 write_dr7(0);
1510                 save_db_regs(svm->host_db_regs);
1511                 load_db_regs(svm->db_regs);
1512         }
1513
1514         clgi();
1515
1516         local_irq_enable();
1517
1518         asm volatile (
1519 #ifdef CONFIG_X86_64
1520                 "push %%rbp; \n\t"
1521 #else
1522                 "push %%ebp; \n\t"
1523 #endif
1524
1525 #ifdef CONFIG_X86_64
1526                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1527                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1528                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1529                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1530                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1531                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1532                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1533                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1534                 "mov %c[r10](%[svm]), %%r10 \n\t"
1535                 "mov %c[r11](%[svm]), %%r11 \n\t"
1536                 "mov %c[r12](%[svm]), %%r12 \n\t"
1537                 "mov %c[r13](%[svm]), %%r13 \n\t"
1538                 "mov %c[r14](%[svm]), %%r14 \n\t"
1539                 "mov %c[r15](%[svm]), %%r15 \n\t"
1540 #else
1541                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1542                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1543                 "mov %c[rdx](%[svm]), %%edx \n\t"
1544                 "mov %c[rsi](%[svm]), %%esi \n\t"
1545                 "mov %c[rdi](%[svm]), %%edi \n\t"
1546                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1547 #endif
1548
1549 #ifdef CONFIG_X86_64
1550                 /* Enter guest mode */
1551                 "push %%rax \n\t"
1552                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1553                 SVM_VMLOAD "\n\t"
1554                 SVM_VMRUN "\n\t"
1555                 SVM_VMSAVE "\n\t"
1556                 "pop %%rax \n\t"
1557 #else
1558                 /* Enter guest mode */
1559                 "push %%eax \n\t"
1560                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1561                 SVM_VMLOAD "\n\t"
1562                 SVM_VMRUN "\n\t"
1563                 SVM_VMSAVE "\n\t"
1564                 "pop %%eax \n\t"
1565 #endif
1566
1567                 /* Save guest registers, load host registers */
1568 #ifdef CONFIG_X86_64
1569                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1570                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1571                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1572                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1573                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1574                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1575                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1576                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1577                 "mov %%r10, %c[r10](%[svm]) \n\t"
1578                 "mov %%r11, %c[r11](%[svm]) \n\t"
1579                 "mov %%r12, %c[r12](%[svm]) \n\t"
1580                 "mov %%r13, %c[r13](%[svm]) \n\t"
1581                 "mov %%r14, %c[r14](%[svm]) \n\t"
1582                 "mov %%r15, %c[r15](%[svm]) \n\t"
1583
1584                 "pop  %%rbp; \n\t"
1585 #else
1586                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1587                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1588                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1589                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1590                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1591                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1592
1593                 "pop  %%ebp; \n\t"
1594 #endif
1595                 :
1596                 : [svm]"a"(svm),
1597                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1598                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1599                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1600                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1601                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1602                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1603                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1604 #ifdef CONFIG_X86_64
1605                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1606                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1607                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1608                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1609                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1610                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1611                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1612                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1613 #endif
1614                 : "cc", "memory"
1615 #ifdef CONFIG_X86_64
1616                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1617                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1618 #else
1619                 , "ebx", "ecx", "edx" , "esi", "edi"
1620 #endif
1621                 );
1622
1623         if ((svm->vmcb->save.dr7 & 0xff))
1624                 load_db_regs(svm->host_db_regs);
1625
1626         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1627
1628         write_dr6(svm->host_dr6);
1629         write_dr7(svm->host_dr7);
1630         kvm_write_cr2(svm->host_cr2);
1631
1632         load_fs(fs_selector);
1633         load_gs(gs_selector);
1634         load_ldt(ldt_selector);
1635         load_host_msrs(vcpu);
1636
1637         reload_tss(vcpu);
1638
1639         local_irq_disable();
1640
1641         stgi();
1642
1643         svm->next_rip = 0;
1644 }
1645
1646 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1647 {
1648         struct vcpu_svm *svm = to_svm(vcpu);
1649
1650         svm->vmcb->save.cr3 = root;
1651         force_new_asid(vcpu);
1652
1653         if (vcpu->fpu_active) {
1654                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1655                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1656                 vcpu->fpu_active = 0;
1657         }
1658 }
1659
1660 static int is_disabled(void)
1661 {
1662         u64 vm_cr;
1663
1664         rdmsrl(MSR_VM_CR, vm_cr);
1665         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1666                 return 1;
1667
1668         return 0;
1669 }
1670
1671 static void
1672 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1673 {
1674         /*
1675          * Patch in the VMMCALL instruction:
1676          */
1677         hypercall[0] = 0x0f;
1678         hypercall[1] = 0x01;
1679         hypercall[2] = 0xd9;
1680 }
1681
1682 static void svm_check_processor_compat(void *rtn)
1683 {
1684         *(int *)rtn = 0;
1685 }
1686
1687 static bool svm_cpu_has_accelerated_tpr(void)
1688 {
1689         return false;
1690 }
1691
1692 static struct kvm_x86_ops svm_x86_ops = {
1693         .cpu_has_kvm_support = has_svm,
1694         .disabled_by_bios = is_disabled,
1695         .hardware_setup = svm_hardware_setup,
1696         .hardware_unsetup = svm_hardware_unsetup,
1697         .check_processor_compatibility = svm_check_processor_compat,
1698         .hardware_enable = svm_hardware_enable,
1699         .hardware_disable = svm_hardware_disable,
1700         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1701
1702         .vcpu_create = svm_create_vcpu,
1703         .vcpu_free = svm_free_vcpu,
1704         .vcpu_reset = svm_vcpu_reset,
1705
1706         .prepare_guest_switch = svm_prepare_guest_switch,
1707         .vcpu_load = svm_vcpu_load,
1708         .vcpu_put = svm_vcpu_put,
1709         .vcpu_decache = svm_vcpu_decache,
1710
1711         .set_guest_debug = svm_guest_debug,
1712         .get_msr = svm_get_msr,
1713         .set_msr = svm_set_msr,
1714         .get_segment_base = svm_get_segment_base,
1715         .get_segment = svm_get_segment,
1716         .set_segment = svm_set_segment,
1717         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1718         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1719         .set_cr0 = svm_set_cr0,
1720         .set_cr3 = svm_set_cr3,
1721         .set_cr4 = svm_set_cr4,
1722         .set_efer = svm_set_efer,
1723         .get_idt = svm_get_idt,
1724         .set_idt = svm_set_idt,
1725         .get_gdt = svm_get_gdt,
1726         .set_gdt = svm_set_gdt,
1727         .get_dr = svm_get_dr,
1728         .set_dr = svm_set_dr,
1729         .cache_regs = svm_cache_regs,
1730         .decache_regs = svm_decache_regs,
1731         .get_rflags = svm_get_rflags,
1732         .set_rflags = svm_set_rflags,
1733
1734         .tlb_flush = svm_flush_tlb,
1735
1736         .run = svm_vcpu_run,
1737         .handle_exit = handle_exit,
1738         .skip_emulated_instruction = skip_emulated_instruction,
1739         .patch_hypercall = svm_patch_hypercall,
1740         .get_irq = svm_get_irq,
1741         .set_irq = svm_set_irq,
1742         .queue_exception = svm_queue_exception,
1743         .exception_injected = svm_exception_injected,
1744         .inject_pending_irq = svm_intr_assist,
1745         .inject_pending_vectors = do_interrupt_requests,
1746
1747         .set_tss_addr = svm_set_tss_addr,
1748 };
1749
1750 static int __init svm_init(void)
1751 {
1752         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1753                               THIS_MODULE);
1754 }
1755
1756 static void __exit svm_exit(void)
1757 {
1758         kvm_exit();
1759 }
1760
1761 module_init(svm_init)
1762 module_exit(svm_exit)