1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/module.h>
5 #include <linux/timer.h>
6 #include <linux/acpi_pmtmr.h>
7 #include <linux/cpufreq.h>
9 #include <linux/delay.h>
10 #include <linux/clocksource.h>
11 #include <linux/percpu.h>
14 #include <asm/timer.h>
15 #include <asm/vgtod.h>
17 #include <asm/delay.h>
19 unsigned int cpu_khz; /* TSC clocks / usec, not used here */
20 EXPORT_SYMBOL(cpu_khz);
22 EXPORT_SYMBOL(tsc_khz);
25 * TSC can be unstable due to cpufreq or due to unsynced TSCs
27 static int tsc_unstable;
29 /* native_sched_clock() is called before tsc_init(), so
30 we must start with the TSC soft disabled to prevent
31 erroneous rdtsc usage on !cpu_has_tsc processors */
32 static int tsc_disabled = -1;
35 * Scheduler clock - returns current time in nanosec units.
37 u64 native_sched_clock(void)
42 * Fall back to jiffies if there's no TSC available:
43 * ( But note that we still use it if the TSC is marked
44 * unstable. We do this because unlike Time Of Day,
45 * the scheduler clock tolerates small errors and it's
46 * very important for it to be as fast as the platform
49 if (unlikely(tsc_disabled)) {
50 /* No locking but a rare wrong value is not a big deal: */
51 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
54 /* read the Time Stamp Counter: */
57 /* return the value in ns */
58 return cycles_2_ns(this_offset);
61 /* We need to define a real function for sched_clock, to override the
62 weak default version */
63 #ifdef CONFIG_PARAVIRT
64 unsigned long long sched_clock(void)
66 return paravirt_sched_clock();
70 sched_clock(void) __attribute__((alias("native_sched_clock")));
73 int check_tsc_unstable(void)
77 EXPORT_SYMBOL_GPL(check_tsc_unstable);
80 int __init notsc_setup(char *str)
82 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
83 "cannot disable TSC completely.\n");
89 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
92 int __init notsc_setup(char *str)
94 setup_clear_cpu_cap(X86_FEATURE_TSC);
99 __setup("notsc", notsc_setup);
101 #define MAX_RETRIES 5
102 #define SMI_TRESHOLD 50000
105 * Read TSC and the reference counters. Take care of SMI disturbance
107 static u64 tsc_read_refs(u64 *pm, u64 *hpet)
112 for (i = 0; i < MAX_RETRIES; i++) {
115 *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
117 *pm = acpi_pm_read_early();
119 if ((t2 - t1) < SMI_TRESHOLD)
126 * native_calibrate_tsc - calibrate the tsc on boot
128 unsigned long native_calibrate_tsc(void)
130 u64 tsc1, tsc2, tr1, tr2, tsc, delta, pm1, pm2, hpet1, hpet2;
131 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
132 unsigned long flags, tscmin, tscmax;
133 int hpet = is_hpet_enabled(), pitcnt, i;
136 * Run 5 calibration loops to get the lowest frequency value
137 * (the best estimate). We use two different calibration modes
140 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
141 * load a timeout of 50ms. We read the time right after we
142 * started the timer and wait until the PIT count down reaches
143 * zero. In each wait loop iteration we read the TSC and check
144 * the delta to the previous read. We keep track of the min
145 * and max values of that delta. The delta is mostly defined
146 * by the IO time of the PIT access, so we can detect when a
147 * SMI/SMM disturbance happend between the two reads. If the
148 * maximum time is significantly larger than the minimum time,
149 * then we discard the result and have another try.
151 * 2) Reference counter. If available we use the HPET or the
152 * PMTIMER as a reference to check the sanity of that value.
153 * We use separate TSC readouts and check inside of the
154 * reference read for a SMI/SMM disturbance. We dicard
155 * disturbed values here as well. We do that around the PIT
156 * calibration delay loop as we have to wait for a certain
157 * amount of time anyway.
159 for (i = 0; i < 5; i++) {
165 local_irq_save(flags);
168 * Read the start value and the reference count of
169 * hpet/pmtimer when available:
171 tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
173 /* Set the Gate high, disable speaker */
174 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
177 * Setup CTC channel 2* for mode 0, (interrupt on terminal
178 * count mode), binary count. Set the latch register to 50ms
179 * (LSB then MSB) to begin countdown.
181 * Some devices need a delay here.
184 outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
185 outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
187 tsc = tr1 = tr2 = get_cycles();
189 while ((inb(0x61) & 0x20) == 0) {
193 if ((unsigned int) delta < tscmin)
194 tscmin = (unsigned int) delta;
195 if ((unsigned int) delta > tscmax)
196 tscmax = (unsigned int) delta;
201 * We waited at least 50ms above. Now read
202 * pmtimer/hpet reference again
204 tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
206 local_irq_restore(flags);
211 * If we were not able to read the PIT more than 5000
212 * times, then we have been hit by a massive SMI
214 * If the maximum is 10 times larger than the minimum,
215 * then we got hit by an SMI as well.
217 if (pitcnt > 5000 && tscmax < 10 * tscmin) {
219 /* Calculate the PIT value */
223 /* We take the smallest value into account */
224 tsc_pit_min = min(tsc_pit_min, (unsigned long) delta);
227 /* hpet or pmtimer available ? */
228 if (!hpet && !pm1 && !pm2)
231 /* Check, whether the sampling was disturbed by an SMI */
232 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
235 tsc2 = (tsc2 - tsc1) * 1000000LL;
239 hpet2 += 0x100000000ULL;
241 tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
242 do_div(tsc1, 1000000);
245 pm2 += (u64)ACPI_PM_OVRRUN;
247 tsc1 = pm2 * 1000000000LL;
248 do_div(tsc1, PMTMR_TICKS_PER_SEC);
252 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
256 * Now check the results.
258 if (tsc_pit_min == ULONG_MAX) {
259 /* PIT gave no useful value */
260 printk(KERN_WARNING "TSC: PIT calibration failed due to "
261 "SMI disturbance.\n");
263 /* We don't have an alternative source, disable TSC */
264 if (!hpet && !pm1 && !pm2) {
265 printk("TSC: No reference (HPET/PMTIMER) available\n");
269 /* The alternative source failed as well, disable TSC */
270 if (tsc_ref_min == ULONG_MAX) {
271 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
272 "failed due to SMI disturbance.\n");
276 /* Use the alternative source */
277 printk(KERN_INFO "TSC: using %s reference calibration\n",
278 hpet ? "HPET" : "PMTIMER");
283 /* We don't have an alternative source, use the PIT calibration value */
284 if (!hpet && !pm1 && !pm2) {
285 printk(KERN_INFO "TSC: Using PIT calibration value\n");
289 /* The alternative source failed, use the PIT calibration value */
290 if (tsc_ref_min == ULONG_MAX) {
291 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed due "
292 "to SMI disturbance. Using PIT calibration\n");
296 /* Check the reference deviation */
297 delta = ((u64) tsc_pit_min) * 100;
298 do_div(delta, tsc_ref_min);
301 * If both calibration results are inside a 5% window, the we
302 * use the lower frequency of those as it is probably the
305 if (delta >= 95 && delta <= 105) {
306 printk(KERN_INFO "TSC: PIT calibration confirmed by %s.\n",
307 hpet ? "HPET" : "PMTIMER");
308 printk(KERN_INFO "TSC: using %s calibration value\n",
309 tsc_pit_min <= tsc_ref_min ? "PIT" :
310 hpet ? "HPET" : "PMTIMER");
311 return tsc_pit_min <= tsc_ref_min ? tsc_pit_min : tsc_ref_min;
314 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
315 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
318 * The calibration values differ too much. In doubt, we use
319 * the PIT value as we know that there are PMTIMERs around
320 * running at double speed.
322 printk(KERN_INFO "TSC: Using PIT calibration value\n");
327 /* Only called from the Powernow K7 cpu freq driver */
328 int recalibrate_cpu_khz(void)
331 unsigned long cpu_khz_old = cpu_khz;
334 tsc_khz = calibrate_tsc();
336 cpu_data(0).loops_per_jiffy =
337 cpufreq_scale(cpu_data(0).loops_per_jiffy,
338 cpu_khz_old, cpu_khz);
347 EXPORT_SYMBOL(recalibrate_cpu_khz);
349 #endif /* CONFIG_X86_32 */
351 /* Accelerators for sched_clock()
352 * convert from cycles(64bits) => nanoseconds (64bits)
354 * ns = cycles / (freq / ns_per_sec)
355 * ns = cycles * (ns_per_sec / freq)
356 * ns = cycles * (10^9 / (cpu_khz * 10^3))
357 * ns = cycles * (10^6 / cpu_khz)
359 * Then we use scaling math (suggested by george@mvista.com) to get:
360 * ns = cycles * (10^6 * SC / cpu_khz) / SC
361 * ns = cycles * cyc2ns_scale / SC
363 * And since SC is a constant power of two, we can convert the div
366 * We can use khz divisor instead of mhz to keep a better precision, since
367 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
368 * (mathieu.desnoyers@polymtl.ca)
370 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
373 DEFINE_PER_CPU(unsigned long, cyc2ns);
375 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
377 unsigned long long tsc_now, ns_now;
378 unsigned long flags, *scale;
380 local_irq_save(flags);
381 sched_clock_idle_sleep_event();
383 scale = &per_cpu(cyc2ns, cpu);
386 ns_now = __cycles_2_ns(tsc_now);
389 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
391 sched_clock_idle_wakeup_event(0);
392 local_irq_restore(flags);
395 #ifdef CONFIG_CPU_FREQ
397 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
400 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
401 * not that important because current Opteron setups do not support
402 * scaling on SMP anyroads.
404 * Should fix up last_tsc too. Currently gettimeofday in the
405 * first tick after the change will be slightly wrong.
408 static unsigned int ref_freq;
409 static unsigned long loops_per_jiffy_ref;
410 static unsigned long tsc_khz_ref;
412 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
415 struct cpufreq_freqs *freq = data;
416 unsigned long *lpj, dummy;
418 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
422 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
424 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
426 lpj = &boot_cpu_data.loops_per_jiffy;
430 ref_freq = freq->old;
431 loops_per_jiffy_ref = *lpj;
432 tsc_khz_ref = tsc_khz;
434 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
435 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
436 (val == CPUFREQ_RESUMECHANGE)) {
437 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
439 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
440 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
441 mark_tsc_unstable("cpufreq changes");
444 set_cyc2ns_scale(tsc_khz, freq->cpu);
449 static struct notifier_block time_cpufreq_notifier_block = {
450 .notifier_call = time_cpufreq_notifier
453 static int __init cpufreq_tsc(void)
457 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
459 cpufreq_register_notifier(&time_cpufreq_notifier_block,
460 CPUFREQ_TRANSITION_NOTIFIER);
464 core_initcall(cpufreq_tsc);
466 #endif /* CONFIG_CPU_FREQ */
468 /* clocksource code */
470 static struct clocksource clocksource_tsc;
473 * We compare the TSC to the cycle_last value in the clocksource
474 * structure to avoid a nasty time-warp. This can be observed in a
475 * very small window right after one CPU updated cycle_last under
476 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
477 * is smaller than the cycle_last reference value due to a TSC which
478 * is slighty behind. This delta is nowhere else observable, but in
479 * that case it results in a forward time jump in the range of hours
480 * due to the unsigned delta calculation of the time keeping core
481 * code, which is necessary to support wrapping clocksources like pm
484 static cycle_t read_tsc(void)
486 cycle_t ret = (cycle_t)get_cycles();
488 return ret >= clocksource_tsc.cycle_last ?
489 ret : clocksource_tsc.cycle_last;
493 static cycle_t __vsyscall_fn vread_tsc(void)
495 cycle_t ret = (cycle_t)vget_cycles();
497 return ret >= __vsyscall_gtod_data.clock.cycle_last ?
498 ret : __vsyscall_gtod_data.clock.cycle_last;
502 static struct clocksource clocksource_tsc = {
506 .mask = CLOCKSOURCE_MASK(64),
508 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
509 CLOCK_SOURCE_MUST_VERIFY,
515 void mark_tsc_unstable(char *reason)
519 printk("Marking TSC unstable due to %s\n", reason);
520 /* Change only the rating, when not registered */
521 if (clocksource_tsc.mult)
522 clocksource_change_rating(&clocksource_tsc, 0);
524 clocksource_tsc.rating = 0;
528 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
530 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
532 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
538 /* List of systems that have known TSC problems */
539 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
541 .callback = dmi_mark_tsc_unstable,
542 .ident = "IBM Thinkpad 380XD",
544 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
545 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
552 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
554 #ifdef CONFIG_MGEODE_LX
555 /* RTSC counts during suspend */
556 #define RTSC_SUSP 0x100
558 static void __init check_geode_tsc_reliable(void)
560 unsigned long res_low, res_high;
562 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
563 if (res_low & RTSC_SUSP)
564 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
567 static inline void check_geode_tsc_reliable(void) { }
571 * Make an educated guess if the TSC is trustworthy and synchronized
574 __cpuinit int unsynchronized_tsc(void)
576 if (!cpu_has_tsc || tsc_unstable)
580 if (apic_is_clustered_box())
584 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
587 * Intel systems are normally all synchronized.
588 * Exceptions must mark TSC as unstable:
590 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
591 /* assume multi socket systems are not synchronized: */
592 if (num_possible_cpus() > 1)
599 static void __init init_tsc_clocksource(void)
601 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
602 clocksource_tsc.shift);
603 /* lower the rating if we already know its unstable: */
604 if (check_tsc_unstable()) {
605 clocksource_tsc.rating = 0;
606 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
608 clocksource_register(&clocksource_tsc);
611 void __init tsc_init(void)
619 tsc_khz = calibrate_tsc();
623 mark_tsc_unstable("could not calculate TSC khz");
628 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
629 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
630 cpu_khz = calibrate_cpu();
633 lpj = ((u64)tsc_khz * 1000);
637 printk("Detected %lu.%03lu MHz processor.\n",
638 (unsigned long)cpu_khz / 1000,
639 (unsigned long)cpu_khz % 1000);
642 * Secondary CPUs do not run through tsc_init(), so set up
643 * all the scale factors for all CPUs, assuming the same
644 * speed as the bootup CPU. (cpufreq notifiers will fix this
645 * up if their speed diverges)
647 for_each_possible_cpu(cpu)
648 set_cyc2ns_scale(cpu_khz, cpu);
650 if (tsc_disabled > 0)
653 /* now allow native_sched_clock() to use rdtsc */
657 /* Check and install the TSC clocksource */
658 dmi_check_system(bad_tsc_dmi_table);
660 if (unsynchronized_tsc())
661 mark_tsc_unstable("TSCs unsynchronized");
663 check_geode_tsc_reliable();
664 init_tsc_clocksource();