2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/bootmem.h>
44 #include <linux/notifier.h>
45 #include <linux/cpu.h>
46 #include <linux/percpu.h>
47 #include <linux/nmi.h>
49 #include <linux/delay.h>
50 #include <linux/mc146818rtc.h>
51 #include <asm/tlbflush.h>
53 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
62 /* Set if we find a B stepping CPU */
63 static int __cpuinitdata smp_b_stepping;
65 static cpumask_t smp_commenced_mask;
67 /* which logical CPU number maps to which CPU (physical APIC ID) */
68 u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata =
69 { [0 ... NR_CPUS-1] = BAD_APICID };
70 void *x86_cpu_to_apicid_early_ptr;
71 DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID;
72 EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid);
74 u8 apicid_2_node[MAX_APICID];
76 static void map_cpu_to_logical_apicid(void);
78 /* State of each CPU. */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
81 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
84 * Mask B, Pentium, but not Pentium MMX
86 if (c->x86_vendor == X86_VENDOR_INTEL &&
88 c->x86_mask >= 1 && c->x86_mask <= 4 &&
91 * Remember we have B step Pentia with bugs
96 * Certain Athlons might work (for various values of 'work') in SMP
97 * but they are not certified as MP capable.
99 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
101 if (num_possible_cpus() == 1)
104 /* Athlon 660/661 is valid. */
105 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
108 /* Duron 670 is valid */
109 if ((c->x86_model==7) && (c->x86_mask==0))
113 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
114 * It's worth noting that the A5 stepping (662) of some Athlon XP's
115 * have the MP bit set.
116 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
118 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
119 ((c->x86_model==7) && (c->x86_mask>=1)) ||
124 /* If we get here, it's not a certified SMP capable AMD system. */
125 add_taint(TAINT_UNSAFE_SMP);
134 * The bootstrap kernel entry code has set these up. Save them for
138 void __cpuinit smp_store_cpu_info(int id)
140 struct cpuinfo_x86 *c = &cpu_data(id);
145 identify_secondary_cpu(c);
149 static atomic_t init_deasserted;
151 static void __cpuinit smp_callin(void)
154 unsigned long timeout;
157 * If waken up by an INIT in an 82489DX configuration
158 * we may get here before an INIT-deassert IPI reaches
159 * our local APIC. We have to wait for the IPI or we'll
160 * lock up on an APIC access.
162 wait_for_init_deassert(&init_deasserted);
165 * (This works even if the APIC is not enabled.)
167 phys_id = GET_APIC_ID(apic_read(APIC_ID));
168 cpuid = smp_processor_id();
169 if (cpu_isset(cpuid, cpu_callin_map)) {
170 printk("huh, phys CPU#%d, CPU#%d already present??\n",
174 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
177 * STARTUP IPIs are fragile beasts as they might sometimes
178 * trigger some glue motherboard logic. Complete APIC bus
179 * silence for 1 second, this overestimates the time the
180 * boot CPU is spending to send the up to 2 STARTUP IPIs
181 * by a factor of two. This should be enough.
185 * Waiting 2s total for startup (udelay is not yet working)
187 timeout = jiffies + 2*HZ;
188 while (time_before(jiffies, timeout)) {
190 * Has the boot CPU finished it's STARTUP sequence?
192 if (cpu_isset(cpuid, cpu_callout_map))
197 if (!time_before(jiffies, timeout)) {
198 printk("BUG: CPU%d started up but did not get a callout!\n",
204 * the boot CPU has finished the init stage and is spinning
205 * on callin_map until we finish. We are free to set up this
206 * CPU, first the APIC. (this is probably redundant on most
210 Dprintk("CALLIN, before setup_local_APIC().\n");
211 smp_callin_clear_local_apic();
213 map_cpu_to_logical_apicid();
219 Dprintk("Stack at about %p\n",&cpuid);
222 * Save our processor parameters
224 smp_store_cpu_info(cpuid);
227 * Allow the master to continue.
229 cpu_set(cpuid, cpu_callin_map);
235 * Activate a secondary processor.
237 static void __cpuinit start_secondary(void *unused)
240 * Don't put *anything* before cpu_init(), SMP booting is too
241 * fragile that we want to limit the things done here to the
242 * most necessary things.
250 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
253 * Check TSC synchronization with the BP:
255 check_tsc_sync_target();
257 setup_secondary_clock();
258 if (nmi_watchdog == NMI_IO_APIC) {
259 disable_8259A_irq(0);
260 enable_NMI_through_LVT0();
264 * low-memory mappings have been cleared, flush them from
265 * the local TLBs too.
269 /* This must be done before setting cpu_online_map */
270 set_cpu_sibling_map(raw_smp_processor_id());
274 * We need to hold call_lock, so there is no inconsistency
275 * between the time smp_call_function() determines number of
276 * IPI recipients, and the time when the determination is made
277 * for which cpus receive the IPI. Holding this
278 * lock helps us to not include this cpu in a currently in progress
279 * smp_call_function().
281 lock_ipi_call_lock();
282 cpu_set(smp_processor_id(), cpu_online_map);
283 unlock_ipi_call_lock();
284 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
286 /* We can take interrupts now: we're officially "up". */
294 * Everything has been set up for the secondary
295 * CPUs - they just need to reload everything
296 * from the task structure
297 * This function must not return.
299 void __devinit initialize_secondary(void)
302 * We don't actually need to load the full TSS,
303 * basically just the stack pointer and the ip.
310 :"m" (current->thread.sp),"m" (current->thread.ip));
313 /* Static state in head.S used to set up a CPU */
321 /* which logical CPUs are on which nodes */
322 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
323 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
324 EXPORT_SYMBOL(node_to_cpumask_map);
325 /* which node each logical CPU is on */
326 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
327 EXPORT_SYMBOL(cpu_to_node_map);
329 /* set up a mapping between cpu and node. */
330 static inline void map_cpu_to_node(int cpu, int node)
332 printk("Mapping cpu %d to node %d\n", cpu, node);
333 cpu_set(cpu, node_to_cpumask_map[node]);
334 cpu_to_node_map[cpu] = node;
337 /* undo a mapping between cpu and node. */
338 static inline void unmap_cpu_to_node(int cpu)
342 printk("Unmapping cpu %d from all nodes\n", cpu);
343 for (node = 0; node < MAX_NUMNODES; node ++)
344 cpu_clear(cpu, node_to_cpumask_map[node]);
345 cpu_to_node_map[cpu] = 0;
347 #else /* !CONFIG_NUMA */
349 #define map_cpu_to_node(cpu, node) ({})
350 #define unmap_cpu_to_node(cpu) ({})
352 #endif /* CONFIG_NUMA */
354 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
356 static void map_cpu_to_logical_apicid(void)
358 int cpu = smp_processor_id();
359 int apicid = logical_smp_processor_id();
360 int node = apicid_to_node(apicid);
362 if (!node_online(node))
363 node = first_online_node;
365 cpu_2_logical_apicid[cpu] = apicid;
366 map_cpu_to_node(cpu, node);
369 static void unmap_cpu_to_logical_apicid(int cpu)
371 cpu_2_logical_apicid[cpu] = BAD_APICID;
372 unmap_cpu_to_node(cpu);
375 static inline void __inquire_remote_apic(int apicid)
377 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
378 char *names[] = { "ID", "VERSION", "SPIV" };
382 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
384 for (i = 0; i < ARRAY_SIZE(regs); i++) {
385 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
390 status = safe_apic_wait_icr_idle();
393 "a previous APIC delivery may have failed\n");
395 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
396 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
401 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
402 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
405 case APIC_ICR_RR_VALID:
406 status = apic_read(APIC_RRR);
407 printk(KERN_CONT "%08x\n", status);
410 printk(KERN_CONT "failed\n");
415 #ifdef WAKE_SECONDARY_VIA_NMI
417 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
418 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
419 * won't ... remember to clear down the APIC, etc later.
422 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
424 unsigned long send_status, accept_status = 0;
428 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
430 /* Boot on the stack */
431 /* Kick the second */
432 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
434 Dprintk("Waiting for send to finish...\n");
435 send_status = safe_apic_wait_icr_idle();
438 * Give the other CPU some time to accept the IPI.
442 * Due to the Pentium erratum 3AP.
444 maxlvt = lapic_get_maxlvt();
446 apic_read_around(APIC_SPIV);
447 apic_write(APIC_ESR, 0);
449 accept_status = (apic_read(APIC_ESR) & 0xEF);
450 Dprintk("NMI sent.\n");
453 printk("APIC never delivered???\n");
455 printk("APIC delivery error (%lx).\n", accept_status);
457 return (send_status | accept_status);
459 #endif /* WAKE_SECONDARY_VIA_NMI */
461 #ifdef WAKE_SECONDARY_VIA_INIT
463 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
465 unsigned long send_status, accept_status = 0;
466 int maxlvt, num_starts, j;
469 * Be paranoid about clearing APIC errors.
471 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
472 apic_read_around(APIC_SPIV);
473 apic_write(APIC_ESR, 0);
477 Dprintk("Asserting INIT.\n");
480 * Turn INIT on target chip
482 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
487 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
490 Dprintk("Waiting for send to finish...\n");
491 send_status = safe_apic_wait_icr_idle();
495 Dprintk("Deasserting INIT.\n");
498 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
501 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
503 Dprintk("Waiting for send to finish...\n");
504 send_status = safe_apic_wait_icr_idle();
506 atomic_set(&init_deasserted, 1);
509 * Should we send STARTUP IPIs ?
511 * Determine this based on the APIC version.
512 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
514 if (APIC_INTEGRATED(apic_version[phys_apicid]))
520 * Paravirt / VMI wants a startup IPI hook here to set up the
521 * target processor state.
523 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
524 (unsigned long) stack_start.sp);
527 * Run STARTUP IPI loop.
529 Dprintk("#startup loops: %d.\n", num_starts);
531 maxlvt = lapic_get_maxlvt();
533 for (j = 1; j <= num_starts; j++) {
534 Dprintk("Sending STARTUP #%d.\n",j);
535 apic_read_around(APIC_SPIV);
536 apic_write(APIC_ESR, 0);
538 Dprintk("After apic_write.\n");
545 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
547 /* Boot on the stack */
548 /* Kick the second */
549 apic_write_around(APIC_ICR, APIC_DM_STARTUP
550 | (start_eip >> 12));
553 * Give the other CPU some time to accept the IPI.
557 Dprintk("Startup point 1.\n");
559 Dprintk("Waiting for send to finish...\n");
560 send_status = safe_apic_wait_icr_idle();
563 * Give the other CPU some time to accept the IPI.
567 * Due to the Pentium erratum 3AP.
570 apic_read_around(APIC_SPIV);
571 apic_write(APIC_ESR, 0);
573 accept_status = (apic_read(APIC_ESR) & 0xEF);
574 if (send_status || accept_status)
577 Dprintk("After Startup.\n");
580 printk("APIC never delivered???\n");
582 printk("APIC delivery error (%lx).\n", accept_status);
584 return (send_status | accept_status);
586 #endif /* WAKE_SECONDARY_VIA_INIT */
588 extern cpumask_t cpu_initialized;
589 static inline int alloc_cpu_id(void)
593 cpus_complement(tmp_map, cpu_present_map);
594 cpu = first_cpu(tmp_map);
600 #ifdef CONFIG_HOTPLUG_CPU
601 static struct task_struct * __cpuinitdata cpu_idle_tasks[NR_CPUS];
602 static inline struct task_struct * __cpuinit alloc_idle_task(int cpu)
604 struct task_struct *idle;
606 if ((idle = cpu_idle_tasks[cpu]) != NULL) {
607 /* initialize thread_struct. we really want to avoid destroy
610 idle->thread.sp = (unsigned long)task_pt_regs(idle);
611 init_idle(idle, cpu);
614 idle = fork_idle(cpu);
617 cpu_idle_tasks[cpu] = idle;
621 #define alloc_idle_task(cpu) fork_idle(cpu)
624 static int __cpuinit do_boot_cpu(int apicid, int cpu)
626 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
627 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
628 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
631 struct task_struct *idle;
632 unsigned long boot_error;
634 unsigned long start_eip;
635 unsigned short nmi_high = 0, nmi_low = 0;
638 * Save current MTRR state in case it was changed since early boot
639 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
644 * We can't use kernel_thread since we must avoid to
645 * reschedule the child.
647 idle = alloc_idle_task(cpu);
649 panic("failed fork for CPU %d", cpu);
652 per_cpu(current_task, cpu) = idle;
653 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
655 idle->thread.ip = (unsigned long) start_secondary;
656 /* start_eip had better be page-aligned! */
657 start_eip = setup_trampoline();
660 alternatives_smp_switch(1);
662 /* So we see what's up */
663 printk("Booting processor %d/%d ip %lx\n", cpu, apicid, start_eip);
664 /* Stack for startup_32 can be just as for start_secondary onwards */
665 stack_start.sp = (void *) idle->thread.sp;
669 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
671 * This grunge runs the startup process for
672 * the targeted processor.
675 atomic_set(&init_deasserted, 0);
677 Dprintk("Setting warm reset code and vector.\n");
679 store_NMI_vector(&nmi_high, &nmi_low);
681 smpboot_setup_warm_reset_vector(start_eip);
684 * Starting actual IPI sequence...
686 boot_error = wakeup_secondary_cpu(apicid, start_eip);
690 * allow APs to start initializing.
692 Dprintk("Before Callout %d.\n", cpu);
693 cpu_set(cpu, cpu_callout_map);
694 Dprintk("After Callout %d.\n", cpu);
697 * Wait 5s total for a response
699 for (timeout = 0; timeout < 50000; timeout++) {
700 if (cpu_isset(cpu, cpu_callin_map))
701 break; /* It has booted */
705 if (cpu_isset(cpu, cpu_callin_map)) {
706 /* number CPUs logically, starting from 1 (BSP is 0) */
708 printk("CPU%d: ", cpu);
709 print_cpu_info(&cpu_data(cpu));
710 Dprintk("CPU has booted.\n");
713 if (*((volatile unsigned char *)trampoline_base)
715 /* trampoline started but...? */
716 printk("Stuck ??\n");
718 /* trampoline code not run */
719 printk("Not responding.\n");
720 inquire_remote_apic(apicid);
725 /* Try to put things back the way they were before ... */
726 unmap_cpu_to_logical_apicid(cpu);
727 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
728 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
731 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
732 cpu_set(cpu, cpu_present_map);
735 /* mark "stuck" area as not stuck */
736 *((volatile unsigned long *)trampoline_base) = 0;
741 #ifdef CONFIG_HOTPLUG_CPU
742 void cpu_exit_clear(void)
744 int cpu = raw_smp_processor_id();
752 cpu_clear(cpu, cpu_callout_map);
753 cpu_clear(cpu, cpu_callin_map);
755 cpu_clear(cpu, smp_commenced_mask);
756 unmap_cpu_to_logical_apicid(cpu);
759 struct warm_boot_cpu_info {
760 struct completion *complete;
761 struct work_struct task;
766 static void __cpuinit do_warm_boot_cpu(struct work_struct *work)
768 struct warm_boot_cpu_info *info =
769 container_of(work, struct warm_boot_cpu_info, task);
770 do_boot_cpu(info->apicid, info->cpu);
771 complete(info->complete);
774 static int __cpuinit __smp_prepare_cpu(int cpu)
776 DECLARE_COMPLETION_ONSTACK(done);
777 struct warm_boot_cpu_info info;
780 apicid = per_cpu(x86_cpu_to_apicid, cpu);
781 if (apicid == BAD_APICID) {
786 info.complete = &done;
787 info.apicid = apicid;
789 INIT_WORK(&info.task, do_warm_boot_cpu);
791 /* init low mem mapping */
792 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
793 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
795 schedule_work(&info.task);
796 wait_for_completion(&done);
806 * Cycle through the processors sending APIC IPIs to boot each.
809 static int boot_cpu_logical_apicid;
810 /* Where the IO area was mapped on multiquad, always 0 otherwise */
812 #ifdef CONFIG_X86_NUMAQ
813 EXPORT_SYMBOL(xquad_portio);
816 static void __init smp_boot_cpus(unsigned int max_cpus)
818 int apicid, cpu, bit, kicked;
819 unsigned long bogosum = 0;
822 * Setup boot CPU information
824 smp_store_cpu_info(0); /* Final full version of the data */
825 printk("CPU%d: ", 0);
826 print_cpu_info(&cpu_data(0));
828 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
829 boot_cpu_logical_apicid = logical_smp_processor_id();
830 per_cpu(x86_cpu_to_apicid, 0) = boot_cpu_physical_apicid;
832 current_thread_info()->cpu = 0;
834 set_cpu_sibling_map(0);
837 * If we couldn't find an SMP configuration at boot time,
838 * get out of here now!
840 if (!smp_found_config && !acpi_lapic) {
841 printk(KERN_NOTICE "SMP motherboard not detected.\n");
842 smpboot_clear_io_apic_irqs();
843 phys_cpu_present_map = physid_mask_of_physid(0);
844 if (APIC_init_uniprocessor())
845 printk(KERN_NOTICE "Local APIC not detected."
846 " Using dummy APIC emulation.\n");
847 map_cpu_to_logical_apicid();
848 cpu_set(0, per_cpu(cpu_sibling_map, 0));
849 cpu_set(0, per_cpu(cpu_core_map, 0));
854 * Should not be necessary because the MP table should list the boot
855 * CPU too, but we do it for the sake of robustness anyway.
856 * Makes no sense to do this check in clustered apic mode, so skip it
858 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
859 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
860 boot_cpu_physical_apicid);
861 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
865 * If we couldn't find a local APIC, then get out of here now!
867 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
868 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
869 boot_cpu_physical_apicid);
870 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
871 smpboot_clear_io_apic_irqs();
872 phys_cpu_present_map = physid_mask_of_physid(0);
873 map_cpu_to_logical_apicid();
874 cpu_set(0, per_cpu(cpu_sibling_map, 0));
875 cpu_set(0, per_cpu(cpu_core_map, 0));
882 * If SMP should be disabled, then really disable it!
885 smp_found_config = 0;
886 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
888 if (nmi_watchdog == NMI_LOCAL_APIC) {
889 printk(KERN_INFO "activating minimal APIC for NMI watchdog use.\n");
893 smpboot_clear_io_apic_irqs();
894 phys_cpu_present_map = physid_mask_of_physid(0);
895 map_cpu_to_logical_apicid();
896 cpu_set(0, per_cpu(cpu_sibling_map, 0));
897 cpu_set(0, per_cpu(cpu_core_map, 0));
903 map_cpu_to_logical_apicid();
906 setup_portio_remap();
909 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
911 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
912 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
915 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
918 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
919 apicid = cpu_present_to_apicid(bit);
921 * Don't even attempt to start the boot CPU!
923 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
926 if (!check_apicid_present(bit))
928 if (max_cpus <= cpucount+1)
931 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
932 printk("CPU #%d not responding - cannot use it.\n",
939 * Cleanup possible dangling ends...
941 smpboot_restore_warm_reset_vector();
944 * Allow the user to impress friends.
946 Dprintk("Before bogomips.\n");
947 for_each_possible_cpu(cpu)
948 if (cpu_isset(cpu, cpu_callout_map))
949 bogosum += cpu_data(cpu).loops_per_jiffy;
951 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
954 (bogosum/(5000/HZ))%100);
956 Dprintk("Before bogocount - setting activated=1.\n");
959 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
962 * Don't taint if we are running SMP kernel on a single non-MP
965 if (tainted & TAINT_UNSAFE_SMP) {
967 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
969 tainted &= ~TAINT_UNSAFE_SMP;
972 Dprintk("Boot done.\n");
975 * construct cpu_sibling_map, so that we can tell sibling CPUs
978 for_each_possible_cpu(cpu) {
979 cpus_clear(per_cpu(cpu_sibling_map, cpu));
980 cpus_clear(per_cpu(cpu_core_map, cpu));
983 cpu_set(0, per_cpu(cpu_sibling_map, 0));
984 cpu_set(0, per_cpu(cpu_core_map, 0));
986 smpboot_setup_io_apic();
991 /* These are wrappers to interface to the new boot process. Someone
992 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
993 void __init native_smp_prepare_cpus(unsigned int max_cpus)
995 smp_commenced_mask = cpumask_of_cpu(0);
996 cpu_callin_map = cpumask_of_cpu(0);
998 smp_boot_cpus(max_cpus);
1001 void __init native_smp_prepare_boot_cpu(void)
1003 unsigned int cpu = smp_processor_id();
1006 switch_to_new_gdt();
1008 cpu_set(cpu, cpu_online_map);
1009 cpu_set(cpu, cpu_callout_map);
1010 cpu_set(cpu, cpu_present_map);
1011 cpu_set(cpu, cpu_possible_map);
1012 __get_cpu_var(cpu_state) = CPU_ONLINE;
1015 int __cpuinit native_cpu_up(unsigned int cpu)
1017 unsigned long flags;
1018 #ifdef CONFIG_HOTPLUG_CPU
1022 * We do warm boot only on cpus that had booted earlier
1023 * Otherwise cold boot is all handled from smp_boot_cpus().
1024 * cpu_callin_map is set during AP kickstart process. Its reset
1025 * when a cpu is taken offline from cpu_exit_clear().
1027 if (!cpu_isset(cpu, cpu_callin_map))
1028 ret = __smp_prepare_cpu(cpu);
1034 /* In case one didn't come up */
1035 if (!cpu_isset(cpu, cpu_callin_map)) {
1036 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1040 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1041 /* Unleash the CPU! */
1042 cpu_set(cpu, smp_commenced_mask);
1045 * Check TSC synchronization with the AP (keep irqs disabled
1048 local_irq_save(flags);
1049 check_tsc_sync_source(cpu);
1050 local_irq_restore(flags);
1052 while (!cpu_isset(cpu, cpu_online_map)) {
1054 touch_nmi_watchdog();
1060 void __init native_smp_cpus_done(unsigned int max_cpus)
1062 #ifdef CONFIG_X86_IO_APIC
1063 setup_ioapic_dest();
1068 void __init smp_intr_init(void)
1071 * IRQ0 must be given a fixed assignment and initialized,
1072 * because it's used before the IO-APIC is set up.
1074 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1077 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1078 * IPI, driven by wakeup.
1080 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1082 /* IPI for invalidation */
1083 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1085 /* IPI for generic function call */
1086 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);