2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/bootmem.h>
44 #include <linux/notifier.h>
45 #include <linux/cpu.h>
46 #include <linux/percpu.h>
47 #include <linux/nmi.h>
49 #include <linux/delay.h>
50 #include <linux/mc146818rtc.h>
51 #include <asm/tlbflush.h>
53 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
62 /* Set if we find a B stepping CPU */
63 static int __cpuinitdata smp_b_stepping;
65 static cpumask_t smp_commenced_mask;
67 /* which logical CPU number maps to which CPU (physical APIC ID) */
68 u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata =
69 { [0 ... NR_CPUS-1] = BAD_APICID };
70 void *x86_cpu_to_apicid_early_ptr;
71 DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID;
72 EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid);
74 u8 apicid_2_node[MAX_APICID];
76 static void map_cpu_to_logical_apicid(void);
78 /* State of each CPU. */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
82 * The bootstrap kernel entry code has set these up. Save them for
86 void __cpuinit smp_store_cpu_info(int id)
88 struct cpuinfo_x86 *c = &cpu_data(id);
93 identify_secondary_cpu(c);
95 * Mask B, Pentium, but not Pentium MMX
97 if (c->x86_vendor == X86_VENDOR_INTEL &&
99 c->x86_mask >= 1 && c->x86_mask <= 4 &&
102 * Remember we have B step Pentia with bugs
107 * Certain Athlons might work (for various values of 'work') in SMP
108 * but they are not certified as MP capable.
110 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
112 if (num_possible_cpus() == 1)
115 /* Athlon 660/661 is valid. */
116 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
119 /* Duron 670 is valid */
120 if ((c->x86_model==7) && (c->x86_mask==0))
124 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
125 * It's worth noting that the A5 stepping (662) of some Athlon XP's
126 * have the MP bit set.
127 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
129 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
130 ((c->x86_model==7) && (c->x86_mask>=1)) ||
135 /* If we get here, it's not a certified SMP capable AMD system. */
136 add_taint(TAINT_UNSAFE_SMP);
143 static atomic_t init_deasserted;
145 static void __cpuinit smp_callin(void)
148 unsigned long timeout;
151 * If waken up by an INIT in an 82489DX configuration
152 * we may get here before an INIT-deassert IPI reaches
153 * our local APIC. We have to wait for the IPI or we'll
154 * lock up on an APIC access.
156 wait_for_init_deassert(&init_deasserted);
159 * (This works even if the APIC is not enabled.)
161 phys_id = GET_APIC_ID(apic_read(APIC_ID));
162 cpuid = smp_processor_id();
163 if (cpu_isset(cpuid, cpu_callin_map)) {
164 printk("huh, phys CPU#%d, CPU#%d already present??\n",
168 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
171 * STARTUP IPIs are fragile beasts as they might sometimes
172 * trigger some glue motherboard logic. Complete APIC bus
173 * silence for 1 second, this overestimates the time the
174 * boot CPU is spending to send the up to 2 STARTUP IPIs
175 * by a factor of two. This should be enough.
179 * Waiting 2s total for startup (udelay is not yet working)
181 timeout = jiffies + 2*HZ;
182 while (time_before(jiffies, timeout)) {
184 * Has the boot CPU finished it's STARTUP sequence?
186 if (cpu_isset(cpuid, cpu_callout_map))
191 if (!time_before(jiffies, timeout)) {
192 printk("BUG: CPU%d started up but did not get a callout!\n",
198 * the boot CPU has finished the init stage and is spinning
199 * on callin_map until we finish. We are free to set up this
200 * CPU, first the APIC. (this is probably redundant on most
204 Dprintk("CALLIN, before setup_local_APIC().\n");
205 smp_callin_clear_local_apic();
207 map_cpu_to_logical_apicid();
213 Dprintk("Stack at about %p\n",&cpuid);
216 * Save our processor parameters
218 smp_store_cpu_info(cpuid);
221 * Allow the master to continue.
223 cpu_set(cpuid, cpu_callin_map);
229 * Activate a secondary processor.
231 static void __cpuinit start_secondary(void *unused)
234 * Don't put *anything* before cpu_init(), SMP booting is too
235 * fragile that we want to limit the things done here to the
236 * most necessary things.
244 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
247 * Check TSC synchronization with the BP:
249 check_tsc_sync_target();
251 setup_secondary_clock();
252 if (nmi_watchdog == NMI_IO_APIC) {
253 disable_8259A_irq(0);
254 enable_NMI_through_LVT0();
258 * low-memory mappings have been cleared, flush them from
259 * the local TLBs too.
263 /* This must be done before setting cpu_online_map */
264 set_cpu_sibling_map(raw_smp_processor_id());
268 * We need to hold call_lock, so there is no inconsistency
269 * between the time smp_call_function() determines number of
270 * IPI recipients, and the time when the determination is made
271 * for which cpus receive the IPI. Holding this
272 * lock helps us to not include this cpu in a currently in progress
273 * smp_call_function().
275 lock_ipi_call_lock();
276 cpu_set(smp_processor_id(), cpu_online_map);
277 unlock_ipi_call_lock();
278 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
280 /* We can take interrupts now: we're officially "up". */
288 * Everything has been set up for the secondary
289 * CPUs - they just need to reload everything
290 * from the task structure
291 * This function must not return.
293 void __devinit initialize_secondary(void)
296 * We don't actually need to load the full TSS,
297 * basically just the stack pointer and the ip.
304 :"m" (current->thread.sp),"m" (current->thread.ip));
307 /* Static state in head.S used to set up a CPU */
315 /* which logical CPUs are on which nodes */
316 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
317 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
318 EXPORT_SYMBOL(node_to_cpumask_map);
319 /* which node each logical CPU is on */
320 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
321 EXPORT_SYMBOL(cpu_to_node_map);
323 /* set up a mapping between cpu and node. */
324 static inline void map_cpu_to_node(int cpu, int node)
326 printk("Mapping cpu %d to node %d\n", cpu, node);
327 cpu_set(cpu, node_to_cpumask_map[node]);
328 cpu_to_node_map[cpu] = node;
331 /* undo a mapping between cpu and node. */
332 static inline void unmap_cpu_to_node(int cpu)
336 printk("Unmapping cpu %d from all nodes\n", cpu);
337 for (node = 0; node < MAX_NUMNODES; node ++)
338 cpu_clear(cpu, node_to_cpumask_map[node]);
339 cpu_to_node_map[cpu] = 0;
341 #else /* !CONFIG_NUMA */
343 #define map_cpu_to_node(cpu, node) ({})
344 #define unmap_cpu_to_node(cpu) ({})
346 #endif /* CONFIG_NUMA */
348 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
350 static void map_cpu_to_logical_apicid(void)
352 int cpu = smp_processor_id();
353 int apicid = logical_smp_processor_id();
354 int node = apicid_to_node(apicid);
356 if (!node_online(node))
357 node = first_online_node;
359 cpu_2_logical_apicid[cpu] = apicid;
360 map_cpu_to_node(cpu, node);
363 static void unmap_cpu_to_logical_apicid(int cpu)
365 cpu_2_logical_apicid[cpu] = BAD_APICID;
366 unmap_cpu_to_node(cpu);
369 static inline void __inquire_remote_apic(int apicid)
371 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
372 char *names[] = { "ID", "VERSION", "SPIV" };
376 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
378 for (i = 0; i < ARRAY_SIZE(regs); i++) {
379 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
384 status = safe_apic_wait_icr_idle();
387 "a previous APIC delivery may have failed\n");
389 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
390 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
395 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
396 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
399 case APIC_ICR_RR_VALID:
400 status = apic_read(APIC_RRR);
401 printk(KERN_CONT "%08x\n", status);
404 printk(KERN_CONT "failed\n");
409 #ifdef WAKE_SECONDARY_VIA_NMI
411 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
412 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
413 * won't ... remember to clear down the APIC, etc later.
416 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
418 unsigned long send_status, accept_status = 0;
422 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
424 /* Boot on the stack */
425 /* Kick the second */
426 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
428 Dprintk("Waiting for send to finish...\n");
429 send_status = safe_apic_wait_icr_idle();
432 * Give the other CPU some time to accept the IPI.
436 * Due to the Pentium erratum 3AP.
438 maxlvt = lapic_get_maxlvt();
440 apic_read_around(APIC_SPIV);
441 apic_write(APIC_ESR, 0);
443 accept_status = (apic_read(APIC_ESR) & 0xEF);
444 Dprintk("NMI sent.\n");
447 printk("APIC never delivered???\n");
449 printk("APIC delivery error (%lx).\n", accept_status);
451 return (send_status | accept_status);
453 #endif /* WAKE_SECONDARY_VIA_NMI */
455 #ifdef WAKE_SECONDARY_VIA_INIT
457 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
459 unsigned long send_status, accept_status = 0;
460 int maxlvt, num_starts, j;
463 * Be paranoid about clearing APIC errors.
465 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
466 apic_read_around(APIC_SPIV);
467 apic_write(APIC_ESR, 0);
471 Dprintk("Asserting INIT.\n");
474 * Turn INIT on target chip
476 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
481 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
484 Dprintk("Waiting for send to finish...\n");
485 send_status = safe_apic_wait_icr_idle();
489 Dprintk("Deasserting INIT.\n");
492 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
495 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
497 Dprintk("Waiting for send to finish...\n");
498 send_status = safe_apic_wait_icr_idle();
500 atomic_set(&init_deasserted, 1);
503 * Should we send STARTUP IPIs ?
505 * Determine this based on the APIC version.
506 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
508 if (APIC_INTEGRATED(apic_version[phys_apicid]))
514 * Paravirt / VMI wants a startup IPI hook here to set up the
515 * target processor state.
517 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
518 (unsigned long) stack_start.sp);
521 * Run STARTUP IPI loop.
523 Dprintk("#startup loops: %d.\n", num_starts);
525 maxlvt = lapic_get_maxlvt();
527 for (j = 1; j <= num_starts; j++) {
528 Dprintk("Sending STARTUP #%d.\n",j);
529 apic_read_around(APIC_SPIV);
530 apic_write(APIC_ESR, 0);
532 Dprintk("After apic_write.\n");
539 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
541 /* Boot on the stack */
542 /* Kick the second */
543 apic_write_around(APIC_ICR, APIC_DM_STARTUP
544 | (start_eip >> 12));
547 * Give the other CPU some time to accept the IPI.
551 Dprintk("Startup point 1.\n");
553 Dprintk("Waiting for send to finish...\n");
554 send_status = safe_apic_wait_icr_idle();
557 * Give the other CPU some time to accept the IPI.
561 * Due to the Pentium erratum 3AP.
564 apic_read_around(APIC_SPIV);
565 apic_write(APIC_ESR, 0);
567 accept_status = (apic_read(APIC_ESR) & 0xEF);
568 if (send_status || accept_status)
571 Dprintk("After Startup.\n");
574 printk("APIC never delivered???\n");
576 printk("APIC delivery error (%lx).\n", accept_status);
578 return (send_status | accept_status);
580 #endif /* WAKE_SECONDARY_VIA_INIT */
582 extern cpumask_t cpu_initialized;
583 static inline int alloc_cpu_id(void)
587 cpus_complement(tmp_map, cpu_present_map);
588 cpu = first_cpu(tmp_map);
594 #ifdef CONFIG_HOTPLUG_CPU
595 static struct task_struct * __cpuinitdata cpu_idle_tasks[NR_CPUS];
596 static inline struct task_struct * __cpuinit alloc_idle_task(int cpu)
598 struct task_struct *idle;
600 if ((idle = cpu_idle_tasks[cpu]) != NULL) {
601 /* initialize thread_struct. we really want to avoid destroy
604 idle->thread.sp = (unsigned long)task_pt_regs(idle);
605 init_idle(idle, cpu);
608 idle = fork_idle(cpu);
611 cpu_idle_tasks[cpu] = idle;
615 #define alloc_idle_task(cpu) fork_idle(cpu)
618 static int __cpuinit do_boot_cpu(int apicid, int cpu)
620 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
621 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
622 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
625 struct task_struct *idle;
626 unsigned long boot_error;
628 unsigned long start_eip;
629 unsigned short nmi_high = 0, nmi_low = 0;
632 * Save current MTRR state in case it was changed since early boot
633 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
638 * We can't use kernel_thread since we must avoid to
639 * reschedule the child.
641 idle = alloc_idle_task(cpu);
643 panic("failed fork for CPU %d", cpu);
646 per_cpu(current_task, cpu) = idle;
647 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
649 idle->thread.ip = (unsigned long) start_secondary;
650 /* start_eip had better be page-aligned! */
651 start_eip = setup_trampoline();
654 alternatives_smp_switch(1);
656 /* So we see what's up */
657 printk("Booting processor %d/%d ip %lx\n", cpu, apicid, start_eip);
658 /* Stack for startup_32 can be just as for start_secondary onwards */
659 stack_start.sp = (void *) idle->thread.sp;
663 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
665 * This grunge runs the startup process for
666 * the targeted processor.
669 atomic_set(&init_deasserted, 0);
671 Dprintk("Setting warm reset code and vector.\n");
673 store_NMI_vector(&nmi_high, &nmi_low);
675 smpboot_setup_warm_reset_vector(start_eip);
678 * Starting actual IPI sequence...
680 boot_error = wakeup_secondary_cpu(apicid, start_eip);
684 * allow APs to start initializing.
686 Dprintk("Before Callout %d.\n", cpu);
687 cpu_set(cpu, cpu_callout_map);
688 Dprintk("After Callout %d.\n", cpu);
691 * Wait 5s total for a response
693 for (timeout = 0; timeout < 50000; timeout++) {
694 if (cpu_isset(cpu, cpu_callin_map))
695 break; /* It has booted */
699 if (cpu_isset(cpu, cpu_callin_map)) {
700 /* number CPUs logically, starting from 1 (BSP is 0) */
702 printk("CPU%d: ", cpu);
703 print_cpu_info(&cpu_data(cpu));
704 Dprintk("CPU has booted.\n");
707 if (*((volatile unsigned char *)trampoline_base)
709 /* trampoline started but...? */
710 printk("Stuck ??\n");
712 /* trampoline code not run */
713 printk("Not responding.\n");
714 inquire_remote_apic(apicid);
719 /* Try to put things back the way they were before ... */
720 unmap_cpu_to_logical_apicid(cpu);
721 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
722 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
725 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
726 cpu_set(cpu, cpu_present_map);
729 /* mark "stuck" area as not stuck */
730 *((volatile unsigned long *)trampoline_base) = 0;
735 #ifdef CONFIG_HOTPLUG_CPU
736 void cpu_exit_clear(void)
738 int cpu = raw_smp_processor_id();
746 cpu_clear(cpu, cpu_callout_map);
747 cpu_clear(cpu, cpu_callin_map);
749 cpu_clear(cpu, smp_commenced_mask);
750 unmap_cpu_to_logical_apicid(cpu);
753 struct warm_boot_cpu_info {
754 struct completion *complete;
755 struct work_struct task;
760 static void __cpuinit do_warm_boot_cpu(struct work_struct *work)
762 struct warm_boot_cpu_info *info =
763 container_of(work, struct warm_boot_cpu_info, task);
764 do_boot_cpu(info->apicid, info->cpu);
765 complete(info->complete);
768 static int __cpuinit __smp_prepare_cpu(int cpu)
770 DECLARE_COMPLETION_ONSTACK(done);
771 struct warm_boot_cpu_info info;
774 apicid = per_cpu(x86_cpu_to_apicid, cpu);
775 if (apicid == BAD_APICID) {
780 info.complete = &done;
781 info.apicid = apicid;
783 INIT_WORK(&info.task, do_warm_boot_cpu);
785 /* init low mem mapping */
786 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
787 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
789 schedule_work(&info.task);
790 wait_for_completion(&done);
800 * Cycle through the processors sending APIC IPIs to boot each.
803 static int boot_cpu_logical_apicid;
804 /* Where the IO area was mapped on multiquad, always 0 otherwise */
806 #ifdef CONFIG_X86_NUMAQ
807 EXPORT_SYMBOL(xquad_portio);
810 static void __init smp_boot_cpus(unsigned int max_cpus)
812 int apicid, cpu, bit, kicked;
813 unsigned long bogosum = 0;
816 * Setup boot CPU information
818 smp_store_cpu_info(0); /* Final full version of the data */
819 printk("CPU%d: ", 0);
820 print_cpu_info(&cpu_data(0));
822 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
823 boot_cpu_logical_apicid = logical_smp_processor_id();
824 per_cpu(x86_cpu_to_apicid, 0) = boot_cpu_physical_apicid;
826 current_thread_info()->cpu = 0;
828 set_cpu_sibling_map(0);
831 * If we couldn't find an SMP configuration at boot time,
832 * get out of here now!
834 if (!smp_found_config && !acpi_lapic) {
835 printk(KERN_NOTICE "SMP motherboard not detected.\n");
836 smpboot_clear_io_apic_irqs();
837 phys_cpu_present_map = physid_mask_of_physid(0);
838 if (APIC_init_uniprocessor())
839 printk(KERN_NOTICE "Local APIC not detected."
840 " Using dummy APIC emulation.\n");
841 map_cpu_to_logical_apicid();
842 cpu_set(0, per_cpu(cpu_sibling_map, 0));
843 cpu_set(0, per_cpu(cpu_core_map, 0));
848 * Should not be necessary because the MP table should list the boot
849 * CPU too, but we do it for the sake of robustness anyway.
850 * Makes no sense to do this check in clustered apic mode, so skip it
852 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
853 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
854 boot_cpu_physical_apicid);
855 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
859 * If we couldn't find a local APIC, then get out of here now!
861 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
862 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
863 boot_cpu_physical_apicid);
864 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
865 smpboot_clear_io_apic_irqs();
866 phys_cpu_present_map = physid_mask_of_physid(0);
867 map_cpu_to_logical_apicid();
868 cpu_set(0, per_cpu(cpu_sibling_map, 0));
869 cpu_set(0, per_cpu(cpu_core_map, 0));
876 * If SMP should be disabled, then really disable it!
879 smp_found_config = 0;
880 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
882 if (nmi_watchdog == NMI_LOCAL_APIC) {
883 printk(KERN_INFO "activating minimal APIC for NMI watchdog use.\n");
887 smpboot_clear_io_apic_irqs();
888 phys_cpu_present_map = physid_mask_of_physid(0);
889 map_cpu_to_logical_apicid();
890 cpu_set(0, per_cpu(cpu_sibling_map, 0));
891 cpu_set(0, per_cpu(cpu_core_map, 0));
897 map_cpu_to_logical_apicid();
900 setup_portio_remap();
903 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
905 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
906 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
909 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
912 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
913 apicid = cpu_present_to_apicid(bit);
915 * Don't even attempt to start the boot CPU!
917 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
920 if (!check_apicid_present(bit))
922 if (max_cpus <= cpucount+1)
925 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
926 printk("CPU #%d not responding - cannot use it.\n",
933 * Cleanup possible dangling ends...
935 smpboot_restore_warm_reset_vector();
938 * Allow the user to impress friends.
940 Dprintk("Before bogomips.\n");
941 for_each_possible_cpu(cpu)
942 if (cpu_isset(cpu, cpu_callout_map))
943 bogosum += cpu_data(cpu).loops_per_jiffy;
945 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
948 (bogosum/(5000/HZ))%100);
950 Dprintk("Before bogocount - setting activated=1.\n");
953 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
956 * Don't taint if we are running SMP kernel on a single non-MP
959 if (tainted & TAINT_UNSAFE_SMP) {
961 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
963 tainted &= ~TAINT_UNSAFE_SMP;
966 Dprintk("Boot done.\n");
969 * construct cpu_sibling_map, so that we can tell sibling CPUs
972 for_each_possible_cpu(cpu) {
973 cpus_clear(per_cpu(cpu_sibling_map, cpu));
974 cpus_clear(per_cpu(cpu_core_map, cpu));
977 cpu_set(0, per_cpu(cpu_sibling_map, 0));
978 cpu_set(0, per_cpu(cpu_core_map, 0));
980 smpboot_setup_io_apic();
985 /* These are wrappers to interface to the new boot process. Someone
986 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
987 void __init native_smp_prepare_cpus(unsigned int max_cpus)
989 smp_commenced_mask = cpumask_of_cpu(0);
990 cpu_callin_map = cpumask_of_cpu(0);
992 smp_boot_cpus(max_cpus);
995 void __init native_smp_prepare_boot_cpu(void)
997 unsigned int cpu = smp_processor_id();
1000 switch_to_new_gdt();
1002 cpu_set(cpu, cpu_online_map);
1003 cpu_set(cpu, cpu_callout_map);
1004 cpu_set(cpu, cpu_present_map);
1005 cpu_set(cpu, cpu_possible_map);
1006 __get_cpu_var(cpu_state) = CPU_ONLINE;
1009 int __cpuinit native_cpu_up(unsigned int cpu)
1011 unsigned long flags;
1012 #ifdef CONFIG_HOTPLUG_CPU
1016 * We do warm boot only on cpus that had booted earlier
1017 * Otherwise cold boot is all handled from smp_boot_cpus().
1018 * cpu_callin_map is set during AP kickstart process. Its reset
1019 * when a cpu is taken offline from cpu_exit_clear().
1021 if (!cpu_isset(cpu, cpu_callin_map))
1022 ret = __smp_prepare_cpu(cpu);
1028 /* In case one didn't come up */
1029 if (!cpu_isset(cpu, cpu_callin_map)) {
1030 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1034 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1035 /* Unleash the CPU! */
1036 cpu_set(cpu, smp_commenced_mask);
1039 * Check TSC synchronization with the AP (keep irqs disabled
1042 local_irq_save(flags);
1043 check_tsc_sync_source(cpu);
1044 local_irq_restore(flags);
1046 while (!cpu_isset(cpu, cpu_online_map)) {
1048 touch_nmi_watchdog();
1054 void __init native_smp_cpus_done(unsigned int max_cpus)
1056 #ifdef CONFIG_X86_IO_APIC
1057 setup_ioapic_dest();
1062 void __init smp_intr_init(void)
1065 * IRQ0 must be given a fixed assignment and initialized,
1066 * because it's used before the IO-APIC is set up.
1068 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1071 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1072 * IPI, driven by wakeup.
1074 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1076 /* IPI for invalidation */
1077 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1079 /* IPI for generic function call */
1080 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);