2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
58 #include <asm/pgtable.h>
59 #include <asm/tlbflush.h>
63 #include <linux/mc146818rtc.h>
65 #include <mach_apic.h>
66 #include <mach_wakecpu.h>
67 #include <smpboot_hooks.h>
70 * FIXME: For x86_64, those are defined in other files. But moving them here,
71 * would make the setup areas dependent on smp, which is a loss. When we
72 * integrate apic between arches, we can probably do a better job, but
73 * right now, they'll stay here -- glommer
76 /* which logical CPU number maps to which CPU (physical APIC ID) */
77 u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata =
78 { [0 ... NR_CPUS-1] = BAD_APICID };
79 void *x86_cpu_to_apicid_early_ptr;
80 DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID;
81 EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid);
83 u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
84 = { [0 ... NR_CPUS-1] = BAD_APICID };
85 void *x86_bios_cpu_apicid_early_ptr;
86 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
87 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
89 /* Internal processor count */
90 unsigned int num_processors;
91 unsigned disabled_cpus __cpuinitdata;
93 /* Bitmask of physically existing CPUs */
94 physid_mask_t phys_cpu_present_map;
96 u8 apicid_2_node[MAX_APICID];
99 /* State of each CPU */
100 DEFINE_PER_CPU(int, cpu_state) = { 0 };
102 /* Store all idle threads, this can be reused instead of creating
103 * a new thread. Also avoids complicated thread destroy functionality
106 #ifdef CONFIG_HOTPLUG_CPU
108 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
109 * removed after init for !CONFIG_HOTPLUG_CPU.
111 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
112 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
113 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
115 struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
116 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
117 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
120 /* Number of siblings per CPU package */
121 int smp_num_siblings = 1;
122 EXPORT_SYMBOL(smp_num_siblings);
124 /* Last level cache ID of each logical CPU */
125 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
127 /* bitmap of online cpus */
128 cpumask_t cpu_online_map __read_mostly;
129 EXPORT_SYMBOL(cpu_online_map);
131 cpumask_t cpu_callin_map;
132 cpumask_t cpu_callout_map;
133 cpumask_t cpu_possible_map;
134 EXPORT_SYMBOL(cpu_possible_map);
136 /* representing HT siblings of each logical CPU */
137 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
138 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
140 /* representing HT and core siblings of each logical CPU */
141 DEFINE_PER_CPU(cpumask_t, cpu_core_map);
142 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
144 /* Per CPU bogomips and other parameters */
145 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
146 EXPORT_PER_CPU_SYMBOL(cpu_info);
148 static atomic_t init_deasserted;
150 static int boot_cpu_logical_apicid;
152 /* ready for x86_64, no harm for x86, since it will overwrite after alloc */
153 unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
155 /* representing cpus for which sibling maps can be computed */
156 static cpumask_t cpu_sibling_setup_map;
158 /* Set if we find a B stepping CPU */
159 int __cpuinitdata smp_b_stepping;
161 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
163 /* which logical CPUs are on which nodes */
164 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
165 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
166 EXPORT_SYMBOL(node_to_cpumask_map);
167 /* which node each logical CPU is on */
168 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
169 EXPORT_SYMBOL(cpu_to_node_map);
171 /* set up a mapping between cpu and node. */
172 static void map_cpu_to_node(int cpu, int node)
174 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
175 cpu_set(cpu, node_to_cpumask_map[node]);
176 cpu_to_node_map[cpu] = node;
179 /* undo a mapping between cpu and node. */
180 static void unmap_cpu_to_node(int cpu)
184 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
185 for (node = 0; node < MAX_NUMNODES; node++)
186 cpu_clear(cpu, node_to_cpumask_map[node]);
187 cpu_to_node_map[cpu] = 0;
189 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
190 #define map_cpu_to_node(cpu, node) ({})
191 #define unmap_cpu_to_node(cpu) ({})
195 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
196 { [0 ... NR_CPUS-1] = BAD_APICID };
198 void map_cpu_to_logical_apicid(void)
200 int cpu = smp_processor_id();
201 int apicid = logical_smp_processor_id();
202 int node = apicid_to_node(apicid);
204 if (!node_online(node))
205 node = first_online_node;
207 cpu_2_logical_apicid[cpu] = apicid;
208 map_cpu_to_node(cpu, node);
211 void unmap_cpu_to_logical_apicid(int cpu)
213 cpu_2_logical_apicid[cpu] = BAD_APICID;
214 unmap_cpu_to_node(cpu);
217 #define unmap_cpu_to_logical_apicid(cpu) do {} while (0)
218 #define map_cpu_to_logical_apicid() do {} while (0)
222 * Report back to the Boot Processor.
225 void __cpuinit smp_callin(void)
228 unsigned long timeout;
231 * If waken up by an INIT in an 82489DX configuration
232 * we may get here before an INIT-deassert IPI reaches
233 * our local APIC. We have to wait for the IPI or we'll
234 * lock up on an APIC access.
236 wait_for_init_deassert(&init_deasserted);
239 * (This works even if the APIC is not enabled.)
241 phys_id = GET_APIC_ID(apic_read(APIC_ID));
242 cpuid = smp_processor_id();
243 if (cpu_isset(cpuid, cpu_callin_map)) {
244 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
247 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
250 * STARTUP IPIs are fragile beasts as they might sometimes
251 * trigger some glue motherboard logic. Complete APIC bus
252 * silence for 1 second, this overestimates the time the
253 * boot CPU is spending to send the up to 2 STARTUP IPIs
254 * by a factor of two. This should be enough.
258 * Waiting 2s total for startup (udelay is not yet working)
260 timeout = jiffies + 2*HZ;
261 while (time_before(jiffies, timeout)) {
263 * Has the boot CPU finished it's STARTUP sequence?
265 if (cpu_isset(cpuid, cpu_callout_map))
270 if (!time_before(jiffies, timeout)) {
271 panic("%s: CPU%d started up but did not get a callout!\n",
276 * the boot CPU has finished the init stage and is spinning
277 * on callin_map until we finish. We are free to set up this
278 * CPU, first the APIC. (this is probably redundant on most
282 Dprintk("CALLIN, before setup_local_APIC().\n");
283 smp_callin_clear_local_apic();
285 end_local_APIC_setup();
286 map_cpu_to_logical_apicid();
291 * Need to enable IRQs because it can take longer and then
292 * the NMI watchdog might kill us.
297 Dprintk("Stack at about %p\n", &cpuid);
300 * Save our processor parameters
302 smp_store_cpu_info(cpuid);
305 * Allow the master to continue.
307 cpu_set(cpuid, cpu_callin_map);
311 * Activate a secondary processor.
313 void __cpuinit start_secondary(void *unused)
316 * Don't put *anything* before cpu_init(), SMP booting is too
317 * fragile that we want to limit the things done here to the
318 * most necessary things.
327 /* otherwise gcc will move up smp_processor_id before the cpu_init */
330 * Check TSC synchronization with the BP:
332 check_tsc_sync_target();
334 if (nmi_watchdog == NMI_IO_APIC) {
335 disable_8259A_irq(0);
336 enable_NMI_through_LVT0();
340 /* This must be done before setting cpu_online_map */
341 set_cpu_sibling_map(raw_smp_processor_id());
345 * We need to hold call_lock, so there is no inconsistency
346 * between the time smp_call_function() determines number of
347 * IPI recipients, and the time when the determination is made
348 * for which cpus receive the IPI. Holding this
349 * lock helps us to not include this cpu in a currently in progress
350 * smp_call_function().
352 lock_ipi_call_lock();
354 spin_lock(&vector_lock);
356 /* Setup the per cpu irq handling data structures */
357 __setup_vector_irq(smp_processor_id());
359 * Allow the master to continue.
361 spin_unlock(&vector_lock);
363 cpu_set(smp_processor_id(), cpu_online_map);
364 unlock_ipi_call_lock();
365 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
367 setup_secondary_clock();
375 * Everything has been set up for the secondary
376 * CPUs - they just need to reload everything
377 * from the task structure
378 * This function must not return.
380 void __devinit initialize_secondary(void)
383 * We don't actually need to load the full TSS,
384 * basically just the stack pointer and the ip.
391 :"m" (current->thread.sp), "m" (current->thread.ip));
395 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
399 * Mask B, Pentium, but not Pentium MMX
401 if (c->x86_vendor == X86_VENDOR_INTEL &&
403 c->x86_mask >= 1 && c->x86_mask <= 4 &&
406 * Remember we have B step Pentia with bugs
411 * Certain Athlons might work (for various values of 'work') in SMP
412 * but they are not certified as MP capable.
414 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
416 if (num_possible_cpus() == 1)
419 /* Athlon 660/661 is valid. */
420 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
424 /* Duron 670 is valid */
425 if ((c->x86_model == 7) && (c->x86_mask == 0))
429 * Athlon 662, Duron 671, and Athlon >model 7 have capability
430 * bit. It's worth noting that the A5 stepping (662) of some
431 * Athlon XP's have the MP bit set.
432 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
435 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
436 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
441 /* If we get here, not a certified SMP capable AMD system. */
442 add_taint(TAINT_UNSAFE_SMP);
450 void smp_checks(void)
453 printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
454 "with B stepping processors.\n");
457 * Don't taint if we are running SMP kernel on a single non-MP
460 if (tainted & TAINT_UNSAFE_SMP) {
461 if (num_online_cpus())
462 printk(KERN_INFO "WARNING: This combination of AMD"
463 "processors is not suitable for SMP.\n");
465 tainted &= ~TAINT_UNSAFE_SMP;
470 * The bootstrap kernel entry code has set these up. Save them for
474 void __cpuinit smp_store_cpu_info(int id)
476 struct cpuinfo_x86 *c = &cpu_data(id);
481 identify_secondary_cpu(c);
486 void __cpuinit set_cpu_sibling_map(int cpu)
489 struct cpuinfo_x86 *c = &cpu_data(cpu);
491 cpu_set(cpu, cpu_sibling_setup_map);
493 if (smp_num_siblings > 1) {
494 for_each_cpu_mask(i, cpu_sibling_setup_map) {
495 if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
496 c->cpu_core_id == cpu_data(i).cpu_core_id) {
497 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
498 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
499 cpu_set(i, per_cpu(cpu_core_map, cpu));
500 cpu_set(cpu, per_cpu(cpu_core_map, i));
501 cpu_set(i, c->llc_shared_map);
502 cpu_set(cpu, cpu_data(i).llc_shared_map);
506 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
509 cpu_set(cpu, c->llc_shared_map);
511 if (current_cpu_data.x86_max_cores == 1) {
512 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
517 for_each_cpu_mask(i, cpu_sibling_setup_map) {
518 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
519 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
520 cpu_set(i, c->llc_shared_map);
521 cpu_set(cpu, cpu_data(i).llc_shared_map);
523 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
524 cpu_set(i, per_cpu(cpu_core_map, cpu));
525 cpu_set(cpu, per_cpu(cpu_core_map, i));
527 * Does this new cpu bringup a new core?
529 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
531 * for each core in package, increment
532 * the booted_cores for this new cpu
534 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
537 * increment the core count for all
538 * the other cpus in this package
541 cpu_data(i).booted_cores++;
542 } else if (i != cpu && !c->booted_cores)
543 c->booted_cores = cpu_data(i).booted_cores;
548 /* maps the cpu to the sched domain representing multi-core */
549 cpumask_t cpu_coregroup_map(int cpu)
551 struct cpuinfo_x86 *c = &cpu_data(cpu);
553 * For perf, we return last level cache shared map.
554 * And for power savings, we return cpu_core_map
556 if (sched_mc_power_savings || sched_smt_power_savings)
557 return per_cpu(cpu_core_map, cpu);
559 return c->llc_shared_map;
563 * Currently trivial. Write the real->protected mode
564 * bootstrap into the page concerned. The caller
565 * has made sure it's suitably aligned.
568 unsigned long __cpuinit setup_trampoline(void)
570 memcpy(trampoline_base, trampoline_data,
571 trampoline_end - trampoline_data);
572 return virt_to_phys(trampoline_base);
577 * We are called very early to get the low memory for the
578 * SMP bootup trampoline page.
580 void __init smp_alloc_memory(void)
582 trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
584 * Has to be in very low memory so we can execute
587 if (__pa(trampoline_base) >= 0x9F000)
592 void impress_friends(void)
595 unsigned long bogosum = 0;
597 * Allow the user to impress friends.
599 Dprintk("Before bogomips.\n");
600 for_each_possible_cpu(cpu)
601 if (cpu_isset(cpu, cpu_callout_map))
602 bogosum += cpu_data(cpu).loops_per_jiffy;
604 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
607 (bogosum/(5000/HZ))%100);
609 Dprintk("Before bogocount - setting activated=1.\n");
612 static inline void __inquire_remote_apic(int apicid)
614 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
615 char *names[] = { "ID", "VERSION", "SPIV" };
619 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
621 for (i = 0; i < ARRAY_SIZE(regs); i++) {
622 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
627 status = safe_apic_wait_icr_idle();
630 "a previous APIC delivery may have failed\n");
632 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
633 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
638 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
639 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
642 case APIC_ICR_RR_VALID:
643 status = apic_read(APIC_RRR);
644 printk(KERN_CONT "%08x\n", status);
647 printk(KERN_CONT "failed\n");
652 #ifdef WAKE_SECONDARY_VIA_NMI
654 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
655 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
656 * won't ... remember to clear down the APIC, etc later.
659 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
661 unsigned long send_status, accept_status = 0;
665 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
667 /* Boot on the stack */
668 /* Kick the second */
669 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
671 Dprintk("Waiting for send to finish...\n");
672 send_status = safe_apic_wait_icr_idle();
675 * Give the other CPU some time to accept the IPI.
679 * Due to the Pentium erratum 3AP.
681 maxlvt = lapic_get_maxlvt();
683 apic_read_around(APIC_SPIV);
684 apic_write(APIC_ESR, 0);
686 accept_status = (apic_read(APIC_ESR) & 0xEF);
687 Dprintk("NMI sent.\n");
690 printk(KERN_ERR "APIC never delivered???\n");
692 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
694 return (send_status | accept_status);
696 #endif /* WAKE_SECONDARY_VIA_NMI */
698 #ifdef WAKE_SECONDARY_VIA_INIT
700 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
702 unsigned long send_status, accept_status = 0;
703 int maxlvt, num_starts, j;
706 * Be paranoid about clearing APIC errors.
708 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
709 apic_read_around(APIC_SPIV);
710 apic_write(APIC_ESR, 0);
714 Dprintk("Asserting INIT.\n");
717 * Turn INIT on target chip
719 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
724 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
727 Dprintk("Waiting for send to finish...\n");
728 send_status = safe_apic_wait_icr_idle();
732 Dprintk("Deasserting INIT.\n");
735 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
738 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
740 Dprintk("Waiting for send to finish...\n");
741 send_status = safe_apic_wait_icr_idle();
744 atomic_set(&init_deasserted, 1);
747 * Should we send STARTUP IPIs ?
749 * Determine this based on the APIC version.
750 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
752 if (APIC_INTEGRATED(apic_version[phys_apicid]))
758 * Paravirt / VMI wants a startup IPI hook here to set up the
759 * target processor state.
761 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
763 (unsigned long)init_rsp);
765 (unsigned long)stack_start.sp);
769 * Run STARTUP IPI loop.
771 Dprintk("#startup loops: %d.\n", num_starts);
773 maxlvt = lapic_get_maxlvt();
775 for (j = 1; j <= num_starts; j++) {
776 Dprintk("Sending STARTUP #%d.\n", j);
777 apic_read_around(APIC_SPIV);
778 apic_write(APIC_ESR, 0);
780 Dprintk("After apic_write.\n");
787 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
789 /* Boot on the stack */
790 /* Kick the second */
791 apic_write_around(APIC_ICR, APIC_DM_STARTUP
792 | (start_eip >> 12));
795 * Give the other CPU some time to accept the IPI.
799 Dprintk("Startup point 1.\n");
801 Dprintk("Waiting for send to finish...\n");
802 send_status = safe_apic_wait_icr_idle();
805 * Give the other CPU some time to accept the IPI.
809 * Due to the Pentium erratum 3AP.
812 apic_read_around(APIC_SPIV);
813 apic_write(APIC_ESR, 0);
815 accept_status = (apic_read(APIC_ESR) & 0xEF);
816 if (send_status || accept_status)
819 Dprintk("After Startup.\n");
822 printk(KERN_ERR "APIC never delivered???\n");
824 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
826 return (send_status | accept_status);
828 #endif /* WAKE_SECONDARY_VIA_INIT */
831 struct work_struct work;
832 struct task_struct *idle;
833 struct completion done;
837 static void __cpuinit do_fork_idle(struct work_struct *work)
839 struct create_idle *c_idle =
840 container_of(work, struct create_idle, work);
842 c_idle->idle = fork_idle(c_idle->cpu);
843 complete(&c_idle->done);
846 static int __cpuinit do_boot_cpu(int apicid, int cpu)
848 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
849 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
850 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
853 unsigned long boot_error = 0;
855 unsigned long start_ip;
856 unsigned short nmi_high = 0, nmi_low = 0;
857 struct create_idle c_idle = {
859 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
861 INIT_WORK(&c_idle.work, do_fork_idle);
863 /* allocate memory for gdts of secondary cpus. Hotplug is considered */
864 if (!cpu_gdt_descr[cpu].address &&
865 !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
866 printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
870 /* Allocate node local memory for AP pdas */
871 if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
872 struct x8664_pda *newpda, *pda;
873 int node = cpu_to_node(cpu);
875 newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC,
878 memcpy(newpda, pda, sizeof(struct x8664_pda));
879 cpu_pda(cpu) = newpda;
882 "Could not allocate node local PDA for CPU %d on node %d\n",
887 alternatives_smp_switch(1);
889 c_idle.idle = get_idle_for_cpu(cpu);
892 * We can't use kernel_thread since we must avoid to
893 * reschedule the child.
896 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
897 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
898 init_idle(c_idle.idle, cpu);
902 if (!keventd_up() || current_is_keventd())
903 c_idle.work.func(&c_idle.work);
905 schedule_work(&c_idle.work);
906 wait_for_completion(&c_idle.done);
909 if (IS_ERR(c_idle.idle)) {
910 printk("failed fork for CPU %d\n", cpu);
911 return PTR_ERR(c_idle.idle);
914 set_idle_for_cpu(cpu, c_idle.idle);
917 per_cpu(current_task, cpu) = c_idle.idle;
919 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
920 c_idle.idle->thread.ip = (unsigned long) start_secondary;
921 /* Stack for startup_32 can be just as for start_secondary onwards */
922 stack_start.sp = (void *) c_idle.idle->thread.sp;
925 cpu_pda(cpu)->pcurrent = c_idle.idle;
926 init_rsp = c_idle.idle->thread.sp;
927 load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
928 initial_code = (unsigned long)start_secondary;
929 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
932 /* start_ip had better be page-aligned! */
933 start_ip = setup_trampoline();
935 /* So we see what's up */
936 printk(KERN_INFO "Booting processor %d/%d ip %lx\n",
937 cpu, apicid, start_ip);
940 * This grunge runs the startup process for
941 * the targeted processor.
944 atomic_set(&init_deasserted, 0);
946 Dprintk("Setting warm reset code and vector.\n");
948 store_NMI_vector(&nmi_high, &nmi_low);
950 smpboot_setup_warm_reset_vector(start_ip);
952 * Be paranoid about clearing APIC errors.
954 apic_write(APIC_ESR, 0);
958 * Starting actual IPI sequence...
960 boot_error = wakeup_secondary_cpu(apicid, start_ip);
964 * allow APs to start initializing.
966 Dprintk("Before Callout %d.\n", cpu);
967 cpu_set(cpu, cpu_callout_map);
968 Dprintk("After Callout %d.\n", cpu);
971 * Wait 5s total for a response
973 for (timeout = 0; timeout < 50000; timeout++) {
974 if (cpu_isset(cpu, cpu_callin_map))
975 break; /* It has booted */
979 if (cpu_isset(cpu, cpu_callin_map)) {
980 /* number CPUs logically, starting from 1 (BSP is 0) */
982 printk(KERN_INFO "CPU%d: ", cpu);
983 print_cpu_info(&cpu_data(cpu));
984 Dprintk("CPU has booted.\n");
987 if (*((volatile unsigned char *)trampoline_base)
989 /* trampoline started but...? */
990 printk(KERN_ERR "Stuck ??\n");
992 /* trampoline code not run */
993 printk(KERN_ERR "Not responding.\n");
994 inquire_remote_apic(apicid);
999 /* Try to put things back the way they were before ... */
1000 unmap_cpu_to_logical_apicid(cpu);
1001 #ifdef CONFIG_X86_64
1002 clear_node_cpumask(cpu); /* was set by numa_add_cpu */
1004 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */
1005 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
1006 cpu_clear(cpu, cpu_possible_map);
1007 cpu_clear(cpu, cpu_present_map);
1008 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
1011 /* mark "stuck" area as not stuck */
1012 *((volatile unsigned long *)trampoline_base) = 0;
1017 int __cpuinit native_cpu_up(unsigned int cpu)
1019 int apicid = cpu_present_to_apicid(cpu);
1020 unsigned long flags;
1023 WARN_ON(irqs_disabled());
1025 Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1027 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
1028 !physid_isset(apicid, phys_cpu_present_map)) {
1029 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
1034 * Already booted CPU?
1036 if (cpu_isset(cpu, cpu_callin_map)) {
1037 Dprintk("do_boot_cpu %d Already started\n", cpu);
1042 * Save current MTRR state in case it was changed since early boot
1043 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1047 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1049 #ifdef CONFIG_X86_32
1050 /* init low mem mapping */
1051 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1052 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
1056 err = do_boot_cpu(apicid, cpu);
1058 Dprintk("do_boot_cpu failed %d\n", err);
1063 * Check TSC synchronization with the AP (keep irqs disabled
1066 local_irq_save(flags);
1067 check_tsc_sync_source(cpu);
1068 local_irq_restore(flags);
1070 while (!cpu_isset(cpu, cpu_online_map)) {
1072 touch_nmi_watchdog();
1079 * Fall back to non SMP mode after errors.
1081 * RED-PEN audit/test this more. I bet there is more state messed up here.
1083 static __init void disable_smp(void)
1085 cpu_present_map = cpumask_of_cpu(0);
1086 cpu_possible_map = cpumask_of_cpu(0);
1087 #ifdef CONFIG_X86_32
1088 smpboot_clear_io_apic_irqs();
1090 if (smp_found_config)
1091 phys_cpu_present_map =
1092 physid_mask_of_physid(boot_cpu_physical_apicid);
1094 phys_cpu_present_map = physid_mask_of_physid(0);
1095 map_cpu_to_logical_apicid();
1096 cpu_set(0, per_cpu(cpu_sibling_map, 0));
1097 cpu_set(0, per_cpu(cpu_core_map, 0));
1101 * Various sanity checks.
1103 static int __init smp_sanity_check(unsigned max_cpus)
1105 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1106 printk(KERN_WARNING "weird, boot CPU (#%d) not listed"
1107 "by the BIOS.\n", hard_smp_processor_id());
1108 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1112 * If we couldn't find an SMP configuration at boot time,
1113 * get out of here now!
1115 if (!smp_found_config && !acpi_lapic) {
1116 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1118 if (APIC_init_uniprocessor())
1119 printk(KERN_NOTICE "Local APIC not detected."
1120 " Using dummy APIC emulation.\n");
1125 * Should not be necessary because the MP table should list the boot
1126 * CPU too, but we do it for the sake of robustness anyway.
1128 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1130 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1131 boot_cpu_physical_apicid);
1132 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1136 * If we couldn't find a local APIC, then get out of here now!
1138 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1140 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1141 boot_cpu_physical_apicid);
1142 printk(KERN_ERR "... forcing use of dummy APIC emulation."
1143 "(tell your hw vendor)\n");
1144 smpboot_clear_io_apic();
1148 verify_local_APIC();
1151 * If SMP should be disabled, then really disable it!
1154 printk(KERN_INFO "SMP mode deactivated,"
1155 "forcing use of dummy APIC emulation.\n");
1156 smpboot_clear_io_apic();
1157 #ifdef CONFIG_X86_32
1158 if (nmi_watchdog == NMI_LOCAL_APIC) {
1159 printk(KERN_INFO "activating minimal APIC for"
1160 "NMI watchdog use.\n");
1163 end_local_APIC_setup();
1172 static void __init smp_cpu_index_default(void)
1175 struct cpuinfo_x86 *c;
1177 for_each_cpu_mask(i, cpu_possible_map) {
1179 /* mark all to hotplug */
1180 c->cpu_index = NR_CPUS;
1185 * Prepare for SMP bootup. The MP table or ACPI has been read
1186 * earlier. Just do some sanity checking here and enable APIC mode.
1188 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1190 nmi_watchdog_default();
1191 smp_cpu_index_default();
1192 current_cpu_data = boot_cpu_data;
1193 cpu_callin_map = cpumask_of_cpu(0);
1196 * Setup boot CPU information
1198 smp_store_cpu_info(0); /* Final full version of the data */
1199 boot_cpu_logical_apicid = logical_smp_processor_id();
1200 current_thread_info()->cpu = 0; /* needed? */
1201 set_cpu_sibling_map(0);
1203 if (smp_sanity_check(max_cpus) < 0) {
1204 printk(KERN_INFO "SMP disabled\n");
1209 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid) {
1210 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1211 GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_physical_apicid);
1212 /* Or can we switch back to PIC here? */
1215 #ifdef CONFIG_X86_32
1219 * Switch from PIC to APIC mode.
1223 #ifdef CONFIG_X86_64
1225 * Enable IO APIC before setting up error vector
1227 if (!skip_ioapic_setup && nr_ioapics)
1230 end_local_APIC_setup();
1232 map_cpu_to_logical_apicid();
1234 setup_portio_remap();
1236 smpboot_setup_io_apic();
1238 * Set up local APIC timer on boot CPU.
1241 printk(KERN_INFO "CPU%d: ", 0);
1242 print_cpu_info(&cpu_data(0));
1246 * Early setup to make printk work.
1248 void __init native_smp_prepare_boot_cpu(void)
1250 int me = smp_processor_id();
1251 #ifdef CONFIG_X86_32
1253 switch_to_new_gdt();
1255 /* already set me in cpu_online_map in boot_cpu_init() */
1256 cpu_set(me, cpu_callout_map);
1257 per_cpu(cpu_state, me) = CPU_ONLINE;
1260 void __init native_smp_cpus_done(unsigned int max_cpus)
1263 * Cleanup possible dangling ends...
1265 smpboot_restore_warm_reset_vector();
1267 Dprintk("Boot done.\n");
1271 #ifdef CONFIG_X86_IO_APIC
1272 setup_ioapic_dest();
1274 check_nmi_watchdog();
1275 #ifdef CONFIG_X86_32
1280 #ifdef CONFIG_HOTPLUG_CPU
1282 # ifdef CONFIG_X86_32
1283 void cpu_exit_clear(void)
1285 int cpu = raw_smp_processor_id();
1292 cpu_clear(cpu, cpu_callout_map);
1293 cpu_clear(cpu, cpu_callin_map);
1295 unmap_cpu_to_logical_apicid(cpu);
1297 # endif /* CONFIG_X86_32 */
1299 void remove_siblinginfo(int cpu)
1302 struct cpuinfo_x86 *c = &cpu_data(cpu);
1304 for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
1305 cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
1307 * last thread sibling in this cpu core going down
1309 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
1310 cpu_data(sibling).booted_cores--;
1313 for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
1314 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
1315 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1316 cpus_clear(per_cpu(cpu_core_map, cpu));
1317 c->phys_proc_id = 0;
1319 cpu_clear(cpu, cpu_sibling_setup_map);
1322 int additional_cpus __initdata = -1;
1324 static __init int setup_additional_cpus(char *s)
1326 return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
1328 early_param("additional_cpus", setup_additional_cpus);
1331 * cpu_possible_map should be static, it cannot change as cpu's
1332 * are onlined, or offlined. The reason is per-cpu data-structures
1333 * are allocated by some modules at init time, and dont expect to
1334 * do this dynamically on cpu arrival/departure.
1335 * cpu_present_map on the other hand can change dynamically.
1336 * In case when cpu_hotplug is not compiled, then we resort to current
1337 * behaviour, which is cpu_possible == cpu_present.
1340 * Three ways to find out the number of additional hotplug CPUs:
1341 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1342 * - The user can overwrite it with additional_cpus=NUM
1343 * - Otherwise don't reserve additional CPUs.
1344 * We do this because additional CPUs waste a lot of memory.
1347 __init void prefill_possible_map(void)
1352 if (additional_cpus == -1) {
1353 if (disabled_cpus > 0)
1354 additional_cpus = disabled_cpus;
1356 additional_cpus = 0;
1358 possible = num_processors + additional_cpus;
1359 if (possible > NR_CPUS)
1362 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1363 possible, max_t(int, possible - num_processors, 0));
1365 for (i = 0; i < possible; i++)
1366 cpu_set(i, cpu_possible_map);
1369 static void __ref remove_cpu_from_maps(int cpu)
1371 cpu_clear(cpu, cpu_online_map);
1372 #ifdef CONFIG_X86_64
1373 cpu_clear(cpu, cpu_callout_map);
1374 cpu_clear(cpu, cpu_callin_map);
1375 /* was set by cpu_init() */
1376 clear_bit(cpu, (unsigned long *)&cpu_initialized);
1377 clear_node_cpumask(cpu);
1381 int __cpu_disable(void)
1383 int cpu = smp_processor_id();
1386 * Perhaps use cpufreq to drop frequency, but that could go
1387 * into generic code.
1389 * We won't take down the boot processor on i386 due to some
1390 * interrupts only being able to be serviced by the BSP.
1391 * Especially so if we're not using an IOAPIC -zwane
1396 if (nmi_watchdog == NMI_LOCAL_APIC)
1397 stop_apic_nmi_watchdog(NULL);
1402 * Allow any queued timer interrupts to get serviced
1403 * This is only a temporary solution until we cleanup
1404 * fixup_irqs as we do for IA64.
1409 local_irq_disable();
1410 remove_siblinginfo(cpu);
1412 /* It's now safe to remove this processor from the online map */
1413 remove_cpu_from_maps(cpu);
1414 fixup_irqs(cpu_online_map);
1418 void __cpu_die(unsigned int cpu)
1420 /* We don't do anything here: idle task is faking death itself. */
1423 for (i = 0; i < 10; i++) {
1424 /* They ack this in play_dead by setting CPU_DEAD */
1425 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1426 printk(KERN_INFO "CPU %d is now offline\n", cpu);
1427 if (1 == num_online_cpus())
1428 alternatives_smp_switch(0);
1433 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1435 #else /* ... !CONFIG_HOTPLUG_CPU */
1436 int __cpu_disable(void)
1441 void __cpu_die(unsigned int cpu)
1443 /* We said "no" in __cpu_disable */
1449 * If the BIOS enumerates physical processors before logical,
1450 * maxcpus=N at enumeration-time can be used to disable HT.
1452 static int __init parse_maxcpus(char *arg)
1454 extern unsigned int maxcpus;
1456 maxcpus = simple_strtoul(arg, NULL, 0);
1459 early_param("maxcpus", parse_maxcpus);