2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
52 #include <video/edid.h>
55 #include <asm/mpspec.h>
56 #include <asm/mmu_context.h>
57 #include <asm/proto.h>
58 #include <asm/setup.h>
59 #include <asm/mach_apic.h>
61 #include <asm/sections.h>
63 #include <asm/cacheflush.h>
67 #ifdef CONFIG_PARAVIRT
68 #include <asm/paravirt.h>
77 struct cpuinfo_x86 boot_cpu_data __read_mostly;
78 EXPORT_SYMBOL(boot_cpu_data);
80 unsigned long mmu_cr4_features;
82 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
85 unsigned long saved_video_mode;
87 int force_mwait __cpuinitdata;
93 char dmi_alloc_data[DMI_MAX_DATA];
98 struct screen_info screen_info;
99 EXPORT_SYMBOL(screen_info);
100 struct sys_desc_table_struct {
101 unsigned short length;
102 unsigned char table[0];
105 struct edid_info edid_info;
106 EXPORT_SYMBOL_GPL(edid_info);
108 extern int root_mountflags;
110 char __initdata command_line[COMMAND_LINE_SIZE];
112 struct resource standard_io_resources[] = {
113 { .name = "dma1", .start = 0x00, .end = 0x1f,
114 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
115 { .name = "pic1", .start = 0x20, .end = 0x21,
116 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
117 { .name = "timer0", .start = 0x40, .end = 0x43,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "timer1", .start = 0x50, .end = 0x53,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "keyboard", .start = 0x60, .end = 0x6f,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "pic2", .start = 0xa0, .end = 0xa1,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "dma2", .start = 0xc0, .end = 0xdf,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "fpu", .start = 0xf0, .end = 0xff,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
133 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
135 static struct resource data_resource = {
136 .name = "Kernel data",
139 .flags = IORESOURCE_RAM,
141 static struct resource code_resource = {
142 .name = "Kernel code",
145 .flags = IORESOURCE_RAM,
147 static struct resource bss_resource = {
148 .name = "Kernel bss",
151 .flags = IORESOURCE_RAM,
154 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
156 #ifdef CONFIG_PROC_VMCORE
157 /* elfcorehdr= specifies the location of elf core header
158 * stored by the crashed kernel. This option will be passed
159 * by kexec loader to the capture kernel.
161 static int __init setup_elfcorehdr(char *arg)
166 elfcorehdr_addr = memparse(arg, &end);
167 return end > arg ? 0 : -EINVAL;
169 early_param("elfcorehdr", setup_elfcorehdr);
174 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
176 unsigned long bootmap_size, bootmap;
178 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
179 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
181 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
182 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
183 e820_register_active_regions(0, start_pfn, end_pfn);
184 free_bootmem_with_active_regions(0, end_pfn);
185 reserve_bootmem(bootmap, bootmap_size);
189 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
191 #ifdef CONFIG_EDD_MODULE
195 * copy_edd() - Copy the BIOS EDD information
196 * from boot_params into a safe place.
199 static inline void copy_edd(void)
201 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
202 sizeof(edd.mbr_signature));
203 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
204 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
205 edd.edd_info_nr = boot_params.eddbuf_entries;
208 static inline void copy_edd(void)
214 static void __init reserve_crashkernel(void)
216 unsigned long long free_mem;
217 unsigned long long crash_size, crash_base;
221 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
223 ret = parse_crashkernel(boot_command_line, free_mem,
224 &crash_size, &crash_base);
225 if (ret == 0 && crash_size) {
226 if (crash_base > 0) {
227 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
228 "for crashkernel (System RAM: %ldMB)\n",
229 (unsigned long)(crash_size >> 20),
230 (unsigned long)(crash_base >> 20),
231 (unsigned long)(free_mem >> 20));
232 crashk_res.start = crash_base;
233 crashk_res.end = crash_base + crash_size - 1;
234 reserve_bootmem(crash_base, crash_size);
236 printk(KERN_INFO "crashkernel reservation failed - "
237 "you have to specify a base address\n");
241 static inline void __init reserve_crashkernel(void)
245 #define EBDA_ADDR_POINTER 0x40E
247 unsigned __initdata ebda_addr;
248 unsigned __initdata ebda_size;
250 static void discover_ebda(void)
253 * there is a real-mode segmented pointer pointing to the
254 * 4K EBDA area at 0x40E
256 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
258 * There can be some situations, like paravirtualized guests,
259 * in which there is no available ebda information. In such
269 ebda_size = *(unsigned short *)__va(ebda_addr);
271 /* Round EBDA up to pages */
275 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
276 if (ebda_size > 64*1024)
280 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
281 void __attribute__((weak)) memory_setup(void)
283 machine_specific_memory_setup();
286 void __init setup_arch(char **cmdline_p)
290 printk(KERN_INFO "Command line: %s\n", boot_command_line);
292 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
293 screen_info = boot_params.screen_info;
294 edid_info = boot_params.edid_info;
295 saved_video_mode = boot_params.hdr.vid_mode;
296 bootloader_type = boot_params.hdr.type_of_loader;
298 #ifdef CONFIG_BLK_DEV_RAM
299 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
300 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
301 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
304 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
314 if (!boot_params.hdr.root_flags)
315 root_mountflags &= ~MS_RDONLY;
316 init_mm.start_code = (unsigned long) &_text;
317 init_mm.end_code = (unsigned long) &_etext;
318 init_mm.end_data = (unsigned long) &_edata;
319 init_mm.brk = (unsigned long) &_end;
321 code_resource.start = virt_to_phys(&_text);
322 code_resource.end = virt_to_phys(&_etext)-1;
323 data_resource.start = virt_to_phys(&_etext);
324 data_resource.end = virt_to_phys(&_edata)-1;
325 bss_resource.start = virt_to_phys(&__bss_start);
326 bss_resource.end = virt_to_phys(&__bss_stop)-1;
328 early_identify_cpu(&boot_cpu_data);
330 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
331 *cmdline_p = command_line;
335 finish_e820_parsing();
337 e820_register_active_regions(0, 0, -1UL);
339 * partially used pages are not usable - thus
340 * we are rounding upwards:
342 end_pfn = e820_end_of_ram();
343 num_physpages = end_pfn;
349 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
358 /* setup to use the static apicid table during kernel startup */
359 x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
364 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
365 * Call this early for SRAT node setup.
367 acpi_boot_table_init();
370 /* How many end-of-memory variables you have, grandma! */
371 max_low_pfn = end_pfn;
373 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
375 /* Remove active ranges so rediscovery with NUMA-awareness happens */
376 remove_all_active_ranges();
378 #ifdef CONFIG_ACPI_NUMA
380 * Parse SRAT to discover nodes.
386 numa_initmem_init(0, end_pfn);
388 contig_initmem_init(0, end_pfn);
391 /* Reserve direct mapping */
392 reserve_bootmem_generic(table_start << PAGE_SHIFT,
393 (table_end - table_start) << PAGE_SHIFT);
396 reserve_bootmem_generic(__pa_symbol(&_text),
397 __pa_symbol(&_end) - __pa_symbol(&_text));
400 * reserve physical page 0 - it's a special BIOS page on many boxes,
401 * enabling clean reboots, SMP operation, laptop functions.
403 reserve_bootmem_generic(0, PAGE_SIZE);
405 /* reserve ebda region */
407 reserve_bootmem_generic(ebda_addr, ebda_size);
409 /* reserve nodemap region */
411 reserve_bootmem_generic(nodemap_addr, nodemap_size);
415 /* Reserve SMP trampoline */
416 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
419 #ifdef CONFIG_ACPI_SLEEP
421 * Reserve low memory region for sleep support.
423 acpi_reserve_bootmem();
428 efi_reserve_bootmem();
432 * Find and reserve possible boot-time SMP configuration:
435 #ifdef CONFIG_BLK_DEV_INITRD
436 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
437 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
438 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
439 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
440 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
442 if (ramdisk_end <= end_of_mem) {
443 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
444 initrd_start = ramdisk_image + PAGE_OFFSET;
445 initrd_end = initrd_start+ramdisk_size;
447 printk(KERN_ERR "initrd extends beyond end of memory "
448 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
449 ramdisk_end, end_of_mem);
454 reserve_crashkernel();
460 * set this early, so we dont allocate cpu0
461 * if MADT list doesnt list BSP first
462 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
464 cpu_set(0, cpu_present_map);
467 * Read APIC and some other early information from ACPI tables.
475 * get boot-time SMP configuration:
477 if (smp_found_config)
479 init_apic_mappings();
480 ioapic_init_mappings();
483 * We trust e820 completely. No explicit ROM probing in memory.
485 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
486 e820_mark_nosave_regions();
488 /* request I/O space for devices used on all i[345]86 PCs */
489 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
490 request_resource(&ioport_resource, &standard_io_resources[i]);
495 #if defined(CONFIG_VGA_CONSOLE)
496 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
497 conswitchp = &vga_con;
498 #elif defined(CONFIG_DUMMY_CONSOLE)
499 conswitchp = &dummy_con;
504 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
508 if (c->extended_cpuid_level < 0x80000004)
511 v = (unsigned int *) c->x86_model_id;
512 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
513 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
514 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
515 c->x86_model_id[48] = 0;
520 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
522 unsigned int n, dummy, eax, ebx, ecx, edx;
524 n = c->extended_cpuid_level;
526 if (n >= 0x80000005) {
527 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
528 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
529 "D cache %dK (%d bytes/line)\n",
530 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
531 c->x86_cache_size = (ecx>>24) + (edx>>24);
532 /* On K8 L1 TLB is inclusive, so don't count it */
536 if (n >= 0x80000006) {
537 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
538 ecx = cpuid_ecx(0x80000006);
539 c->x86_cache_size = ecx >> 16;
540 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
542 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
543 c->x86_cache_size, ecx & 0xFF);
547 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
548 if (n >= 0x80000008) {
549 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
550 c->x86_virt_bits = (eax >> 8) & 0xff;
551 c->x86_phys_bits = eax & 0xff;
556 static int nearby_node(int apicid)
560 for (i = apicid - 1; i >= 0; i--) {
561 node = apicid_to_node[i];
562 if (node != NUMA_NO_NODE && node_online(node))
565 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
566 node = apicid_to_node[i];
567 if (node != NUMA_NO_NODE && node_online(node))
570 return first_node(node_online_map); /* Shouldn't happen */
575 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
576 * Assumes number of cores is a power of two.
578 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
583 int cpu = smp_processor_id();
585 unsigned apicid = hard_smp_processor_id();
587 bits = c->x86_coreid_bits;
589 /* Low order bits define the core id (index of core in socket) */
590 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
591 /* Convert the APIC ID into the socket ID */
592 c->phys_proc_id = phys_pkg_id(bits);
595 node = c->phys_proc_id;
596 if (apicid_to_node[apicid] != NUMA_NO_NODE)
597 node = apicid_to_node[apicid];
598 if (!node_online(node)) {
599 /* Two possibilities here:
600 - The CPU is missing memory and no node was created.
601 In that case try picking one from a nearby CPU
602 - The APIC IDs differ from the HyperTransport node IDs
603 which the K8 northbridge parsing fills in.
604 Assume they are all increased by a constant offset,
605 but in the same order as the HT nodeids.
606 If that doesn't result in a usable node fall back to the
607 path for the previous case. */
609 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
611 if (ht_nodeid >= 0 &&
612 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
613 node = apicid_to_node[ht_nodeid];
614 /* Pick a nearby node */
615 if (!node_online(node))
616 node = nearby_node(apicid);
618 numa_set_node(cpu, node);
620 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
625 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
630 /* Multi core CPU? */
631 if (c->extended_cpuid_level < 0x80000008)
634 ecx = cpuid_ecx(0x80000008);
636 c->x86_max_cores = (ecx & 0xff) + 1;
638 /* CPU telling us the core id bits shift? */
639 bits = (ecx >> 12) & 0xF;
641 /* Otherwise recompute */
643 while ((1 << bits) < c->x86_max_cores)
647 c->x86_coreid_bits = bits;
652 #define ENABLE_C1E_MASK 0x18000000
653 #define CPUID_PROCESSOR_SIGNATURE 1
654 #define CPUID_XFAM 0x0ff00000
655 #define CPUID_XFAM_K8 0x00000000
656 #define CPUID_XFAM_10H 0x00100000
657 #define CPUID_XFAM_11H 0x00200000
658 #define CPUID_XMOD 0x000f0000
659 #define CPUID_XMOD_REV_F 0x00040000
661 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
662 static __cpuinit int amd_apic_timer_broken(void)
664 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
666 switch (eax & CPUID_XFAM) {
668 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
672 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
673 if (lo & ENABLE_C1E_MASK)
677 /* err on the side of caution */
683 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
691 * Disable TLB flush filter by setting HWCR.FFDIS on K8
692 * bit 6 of msr C001_0015
694 * Errata 63 for SH-B3 steppings
695 * Errata 122 for all steppings (F+ have it disabled by default)
698 rdmsrl(MSR_K8_HWCR, value);
700 wrmsrl(MSR_K8_HWCR, value);
704 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
705 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
706 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
708 /* On C+ stepping K8 rep microcode works well for copy/memset */
709 level = cpuid_eax(1);
710 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
712 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
713 if (c->x86 == 0x10 || c->x86 == 0x11)
714 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
716 /* Enable workaround for FXSAVE leak */
718 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
720 level = get_model_name(c);
724 /* Should distinguish Models here, but this is only
725 a fallback anyways. */
726 strcpy(c->x86_model_id, "Hammer");
730 display_cacheinfo(c);
732 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
733 if (c->x86_power & (1<<8))
734 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
736 /* Multi core CPU? */
737 if (c->extended_cpuid_level >= 0x80000008)
740 if (c->extended_cpuid_level >= 0x80000006 &&
741 (cpuid_edx(0x80000006) & 0xf000))
742 num_cache_leaves = 4;
744 num_cache_leaves = 3;
746 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
747 set_cpu_cap(c, X86_FEATURE_K8);
749 /* MFENCE stops RDTSC speculation */
750 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
752 /* Family 10 doesn't support C states in MWAIT so don't use it */
753 if (c->x86 == 0x10 && !force_mwait)
754 clear_cpu_cap(c, X86_FEATURE_MWAIT);
756 if (amd_apic_timer_broken())
757 disable_apic_timer = 1;
760 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
763 u32 eax, ebx, ecx, edx;
764 int index_msb, core_bits;
766 cpuid(1, &eax, &ebx, &ecx, &edx);
769 if (!cpu_has(c, X86_FEATURE_HT))
771 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
774 smp_num_siblings = (ebx & 0xff0000) >> 16;
776 if (smp_num_siblings == 1) {
777 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
778 } else if (smp_num_siblings > 1) {
780 if (smp_num_siblings > NR_CPUS) {
781 printk(KERN_WARNING "CPU: Unsupported number of "
782 "siblings %d", smp_num_siblings);
783 smp_num_siblings = 1;
787 index_msb = get_count_order(smp_num_siblings);
788 c->phys_proc_id = phys_pkg_id(index_msb);
790 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
792 index_msb = get_count_order(smp_num_siblings);
794 core_bits = get_count_order(c->x86_max_cores);
796 c->cpu_core_id = phys_pkg_id(index_msb) &
797 ((1 << core_bits) - 1);
800 if ((c->x86_max_cores * smp_num_siblings) > 1) {
801 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
803 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
811 * find out the number of processor cores on the die
813 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
817 if (c->cpuid_level < 4)
820 cpuid_count(4, 0, &eax, &t, &t, &t);
823 return ((eax >> 26) + 1);
828 static void srat_detect_node(void)
832 int cpu = smp_processor_id();
833 int apicid = hard_smp_processor_id();
835 /* Don't do the funky fallback heuristics the AMD version employs
837 node = apicid_to_node[apicid];
838 if (node == NUMA_NO_NODE)
839 node = first_node(node_online_map);
840 numa_set_node(cpu, node);
842 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
846 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
851 init_intel_cacheinfo(c);
852 if (c->cpuid_level > 9) {
853 unsigned eax = cpuid_eax(10);
854 /* Check for version and the number of counters */
855 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
856 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
861 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
863 set_cpu_cap(c, X86_FEATURE_BTS);
865 set_cpu_cap(c, X86_FEATURE_PEBS);
872 n = c->extended_cpuid_level;
873 if (n >= 0x80000008) {
874 unsigned eax = cpuid_eax(0x80000008);
875 c->x86_virt_bits = (eax >> 8) & 0xff;
876 c->x86_phys_bits = eax & 0xff;
877 /* CPUID workaround for Intel 0F34 CPU */
878 if (c->x86_vendor == X86_VENDOR_INTEL &&
879 c->x86 == 0xF && c->x86_model == 0x3 &&
881 c->x86_phys_bits = 36;
885 c->x86_cache_alignment = c->x86_clflush_size * 2;
886 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
887 (c->x86 == 0x6 && c->x86_model >= 0x0e))
888 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
890 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
892 set_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
894 clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
895 c->x86_max_cores = intel_num_cpu_cores(c);
900 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
902 char *v = c->x86_vendor_id;
904 if (!strcmp(v, "AuthenticAMD"))
905 c->x86_vendor = X86_VENDOR_AMD;
906 else if (!strcmp(v, "GenuineIntel"))
907 c->x86_vendor = X86_VENDOR_INTEL;
909 c->x86_vendor = X86_VENDOR_UNKNOWN;
912 struct cpu_model_info {
915 char *model_names[16];
918 /* Do some early cpuid on the boot CPU to get some parameter that are
919 needed before check_bugs. Everything advanced is in identify_cpu
921 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
925 c->loops_per_jiffy = loops_per_jiffy;
926 c->x86_cache_size = -1;
927 c->x86_vendor = X86_VENDOR_UNKNOWN;
928 c->x86_model = c->x86_mask = 0; /* So far unknown... */
929 c->x86_vendor_id[0] = '\0'; /* Unset */
930 c->x86_model_id[0] = '\0'; /* Unset */
931 c->x86_clflush_size = 64;
932 c->x86_cache_alignment = c->x86_clflush_size;
933 c->x86_max_cores = 1;
934 c->x86_coreid_bits = 0;
935 c->extended_cpuid_level = 0;
936 memset(&c->x86_capability, 0, sizeof c->x86_capability);
938 /* Get vendor name */
939 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
940 (unsigned int *)&c->x86_vendor_id[0],
941 (unsigned int *)&c->x86_vendor_id[8],
942 (unsigned int *)&c->x86_vendor_id[4]);
946 /* Initialize the standard set of capabilities */
947 /* Note that the vendor-specific code below might override */
949 /* Intel-defined flags: level 0x00000001 */
950 if (c->cpuid_level >= 0x00000001) {
952 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
953 &c->x86_capability[0]);
954 c->x86 = (tfms >> 8) & 0xf;
955 c->x86_model = (tfms >> 4) & 0xf;
956 c->x86_mask = tfms & 0xf;
958 c->x86 += (tfms >> 20) & 0xff;
960 c->x86_model += ((tfms >> 16) & 0xF) << 4;
961 if (c->x86_capability[0] & (1<<19))
962 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
964 /* Have CPUID level 0 only - unheard of */
969 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
971 /* AMD-defined flags: level 0x80000001 */
972 xlvl = cpuid_eax(0x80000000);
973 c->extended_cpuid_level = xlvl;
974 if ((xlvl & 0xffff0000) == 0x80000000) {
975 if (xlvl >= 0x80000001) {
976 c->x86_capability[1] = cpuid_edx(0x80000001);
977 c->x86_capability[6] = cpuid_ecx(0x80000001);
979 if (xlvl >= 0x80000004)
980 get_model_name(c); /* Default name */
983 /* Transmeta-defined flags: level 0x80860001 */
984 xlvl = cpuid_eax(0x80860000);
985 if ((xlvl & 0xffff0000) == 0x80860000) {
986 /* Don't set x86_cpuid_level here for now to not confuse. */
987 if (xlvl >= 0x80860001)
988 c->x86_capability[2] = cpuid_edx(0x80860001);
991 switch (c->x86_vendor) {
1000 * This does the hard work of actually picking apart the CPU stuff...
1002 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1006 early_identify_cpu(c);
1008 init_scattered_cpuid_features(c);
1010 c->apicid = phys_pkg_id(0);
1013 * Vendor-specific initialization. In this section we
1014 * canonicalize the feature flags, meaning if there are
1015 * features a certain CPU supports which CPUID doesn't
1016 * tell us, CPUID claiming incorrect flags, or other bugs,
1017 * we handle them here.
1019 * At the end of this section, c->x86_capability better
1020 * indicate the features this CPU genuinely supports!
1022 switch (c->x86_vendor) {
1023 case X86_VENDOR_AMD:
1027 case X86_VENDOR_INTEL:
1031 case X86_VENDOR_UNKNOWN:
1033 display_cacheinfo(c);
1037 select_idle_routine(c);
1041 * On SMP, boot_cpu_data holds the common feature set between
1042 * all CPUs; so make sure that we indicate which features are
1043 * common between the CPUs. The first time this routine gets
1044 * executed, c == &boot_cpu_data.
1046 if (c != &boot_cpu_data) {
1047 /* AND the already accumulated flags with these */
1048 for (i = 0; i < NCAPINTS; i++)
1049 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1052 #ifdef CONFIG_X86_MCE
1055 if (c != &boot_cpu_data)
1058 numa_add_cpu(smp_processor_id());
1062 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1064 if (c->x86_model_id[0])
1065 printk(KERN_INFO "%s", c->x86_model_id);
1067 if (c->x86_mask || c->cpuid_level >= 0)
1068 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1070 printk(KERN_CONT "\n");
1074 * Get CPU information for use by the procfs.
1077 static int show_cpuinfo(struct seq_file *m, void *v)
1079 struct cpuinfo_x86 *c = v;
1083 * These flag bits must match the definitions in <asm/cpufeature.h>.
1084 * NULL means this bit is undefined or reserved; either way it doesn't
1085 * have meaning as far as Linux is concerned. Note that it's important
1086 * to realize there is a difference between this table and CPUID -- if
1087 * applications want to get the raw CPUID data, they should access
1088 * /dev/cpu/<cpu_nr>/cpuid instead.
1090 static const char *const x86_cap_flags[] = {
1092 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1093 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1094 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1095 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1098 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1099 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1100 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1101 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1102 "3dnowext", "3dnow",
1104 /* Transmeta-defined */
1105 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1108 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1110 /* Other (Linux-defined) */
1111 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1112 NULL, NULL, NULL, NULL,
1113 "constant_tsc", "up", NULL, "arch_perfmon",
1114 "pebs", "bts", NULL, "sync_rdtsc",
1115 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1116 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1118 /* Intel-defined (#2) */
1119 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1120 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1121 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1122 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1124 /* VIA/Cyrix/Centaur-defined */
1125 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1126 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1127 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1128 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1130 /* AMD-defined (#2) */
1131 "lahf_lm", "cmp_legacy", "svm", "extapic",
1132 "cr8_legacy", "abm", "sse4a", "misalignsse",
1133 "3dnowprefetch", "osvw", "ibs", "sse5",
1134 "skinit", "wdt", NULL, NULL,
1135 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1138 /* Auxiliary (Linux-defined) */
1139 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1141 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1142 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1144 static const char *const x86_power_flags[] = {
1145 "ts", /* temperature sensor */
1146 "fid", /* frequency id control */
1147 "vid", /* voltage id control */
1148 "ttp", /* thermal trip */
1153 "", /* tsc invariant mapped to constant_tsc */
1162 seq_printf(m, "processor\t: %u\n"
1164 "cpu family\t: %d\n"
1166 "model name\t: %s\n",
1168 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1171 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1173 if (c->x86_mask || c->cpuid_level >= 0)
1174 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1176 seq_printf(m, "stepping\t: unknown\n");
1178 if (cpu_has(c, X86_FEATURE_TSC)) {
1179 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1183 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1184 freq / 1000, (freq % 1000));
1188 if (c->x86_cache_size >= 0)
1189 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1192 if (smp_num_siblings * c->x86_max_cores > 1) {
1193 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1194 seq_printf(m, "siblings\t: %d\n",
1195 cpus_weight(per_cpu(cpu_core_map, cpu)));
1196 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1197 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1203 "fpu_exception\t: yes\n"
1204 "cpuid level\t: %d\n"
1209 for (i = 0; i < 32*NCAPINTS; i++)
1210 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1211 seq_printf(m, " %s", x86_cap_flags[i]);
1213 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1214 c->loops_per_jiffy/(500000/HZ),
1215 (c->loops_per_jiffy/(5000/HZ)) % 100);
1217 if (c->x86_tlbsize > 0)
1218 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1219 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1220 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1222 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1223 c->x86_phys_bits, c->x86_virt_bits);
1225 seq_printf(m, "power management:");
1226 for (i = 0; i < 32; i++) {
1227 if (c->x86_power & (1 << i)) {
1228 if (i < ARRAY_SIZE(x86_power_flags) &&
1230 seq_printf(m, "%s%s",
1231 x86_power_flags[i][0]?" ":"",
1232 x86_power_flags[i]);
1234 seq_printf(m, " [%d]", i);
1238 seq_printf(m, "\n\n");
1243 static void *c_start(struct seq_file *m, loff_t *pos)
1245 if (*pos == 0) /* just in case, cpu 0 is not the first */
1246 *pos = first_cpu(cpu_online_map);
1247 if ((*pos) < NR_CPUS && cpu_online(*pos))
1248 return &cpu_data(*pos);
1252 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1254 *pos = next_cpu(*pos, cpu_online_map);
1255 return c_start(m, pos);
1258 static void c_stop(struct seq_file *m, void *v)
1262 struct seq_operations cpuinfo_op = {
1266 .show = show_cpuinfo,