2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
53 #include <video/edid.h>
56 #include <asm/mpspec.h>
57 #include <asm/mmu_context.h>
58 #include <asm/proto.h>
59 #include <asm/setup.h>
60 #include <asm/mach_apic.h>
62 #include <asm/sections.h>
64 #include <asm/cacheflush.h>
68 #ifdef CONFIG_PARAVIRT
69 #include <asm/paravirt.h>
78 struct cpuinfo_x86 boot_cpu_data __read_mostly;
79 EXPORT_SYMBOL(boot_cpu_data);
81 unsigned long mmu_cr4_features;
83 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
86 unsigned long saved_video_mode;
88 int force_mwait __cpuinitdata;
94 char dmi_alloc_data[DMI_MAX_DATA];
99 struct screen_info screen_info;
100 EXPORT_SYMBOL(screen_info);
101 struct sys_desc_table_struct {
102 unsigned short length;
103 unsigned char table[0];
106 struct edid_info edid_info;
107 EXPORT_SYMBOL_GPL(edid_info);
109 extern int root_mountflags;
111 char __initdata command_line[COMMAND_LINE_SIZE];
113 struct resource standard_io_resources[] = {
114 { .name = "dma1", .start = 0x00, .end = 0x1f,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "pic1", .start = 0x20, .end = 0x21,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "timer0", .start = 0x40, .end = 0x43,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "timer1", .start = 0x50, .end = 0x53,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "keyboard", .start = 0x60, .end = 0x6f,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "pic2", .start = 0xa0, .end = 0xa1,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "dma2", .start = 0xc0, .end = 0xdf,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "fpu", .start = 0xf0, .end = 0xff,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
134 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
136 static struct resource data_resource = {
137 .name = "Kernel data",
140 .flags = IORESOURCE_RAM,
142 static struct resource code_resource = {
143 .name = "Kernel code",
146 .flags = IORESOURCE_RAM,
148 static struct resource bss_resource = {
149 .name = "Kernel bss",
152 .flags = IORESOURCE_RAM,
155 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
157 #ifdef CONFIG_PROC_VMCORE
158 /* elfcorehdr= specifies the location of elf core header
159 * stored by the crashed kernel. This option will be passed
160 * by kexec loader to the capture kernel.
162 static int __init setup_elfcorehdr(char *arg)
167 elfcorehdr_addr = memparse(arg, &end);
168 return end > arg ? 0 : -EINVAL;
170 early_param("elfcorehdr", setup_elfcorehdr);
175 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
177 unsigned long bootmap_size, bootmap;
179 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
180 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
182 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
183 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
184 e820_register_active_regions(0, start_pfn, end_pfn);
185 free_bootmem_with_active_regions(0, end_pfn);
186 reserve_bootmem(bootmap, bootmap_size);
190 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
192 #ifdef CONFIG_EDD_MODULE
196 * copy_edd() - Copy the BIOS EDD information
197 * from boot_params into a safe place.
200 static inline void copy_edd(void)
202 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
203 sizeof(edd.mbr_signature));
204 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
205 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
206 edd.edd_info_nr = boot_params.eddbuf_entries;
209 static inline void copy_edd(void)
215 static void __init reserve_crashkernel(void)
217 unsigned long long free_mem;
218 unsigned long long crash_size, crash_base;
222 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
224 ret = parse_crashkernel(boot_command_line, free_mem,
225 &crash_size, &crash_base);
226 if (ret == 0 && crash_size) {
227 if (crash_base > 0) {
228 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
229 "for crashkernel (System RAM: %ldMB)\n",
230 (unsigned long)(crash_size >> 20),
231 (unsigned long)(crash_base >> 20),
232 (unsigned long)(free_mem >> 20));
233 crashk_res.start = crash_base;
234 crashk_res.end = crash_base + crash_size - 1;
235 reserve_bootmem(crash_base, crash_size);
237 printk(KERN_INFO "crashkernel reservation failed - "
238 "you have to specify a base address\n");
242 static inline void __init reserve_crashkernel(void)
246 #define EBDA_ADDR_POINTER 0x40E
248 unsigned __initdata ebda_addr;
249 unsigned __initdata ebda_size;
251 static void discover_ebda(void)
254 * there is a real-mode segmented pointer pointing to the
255 * 4K EBDA area at 0x40E
257 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
259 * There can be some situations, like paravirtualized guests,
260 * in which there is no available ebda information. In such
270 ebda_size = *(unsigned short *)__va(ebda_addr);
272 /* Round EBDA up to pages */
276 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
277 if (ebda_size > 64*1024)
281 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
282 void __attribute__((weak)) __init memory_setup(void)
284 machine_specific_memory_setup();
287 void __init setup_arch(char **cmdline_p)
291 printk(KERN_INFO "Command line: %s\n", boot_command_line);
293 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
294 screen_info = boot_params.screen_info;
295 edid_info = boot_params.edid_info;
296 saved_video_mode = boot_params.hdr.vid_mode;
297 bootloader_type = boot_params.hdr.type_of_loader;
299 #ifdef CONFIG_BLK_DEV_RAM
300 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
301 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
302 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
305 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
315 if (!boot_params.hdr.root_flags)
316 root_mountflags &= ~MS_RDONLY;
317 init_mm.start_code = (unsigned long) &_text;
318 init_mm.end_code = (unsigned long) &_etext;
319 init_mm.end_data = (unsigned long) &_edata;
320 init_mm.brk = (unsigned long) &_end;
322 code_resource.start = virt_to_phys(&_text);
323 code_resource.end = virt_to_phys(&_etext)-1;
324 data_resource.start = virt_to_phys(&_etext);
325 data_resource.end = virt_to_phys(&_edata)-1;
326 bss_resource.start = virt_to_phys(&__bss_start);
327 bss_resource.end = virt_to_phys(&__bss_stop)-1;
329 early_identify_cpu(&boot_cpu_data);
331 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
332 *cmdline_p = command_line;
336 finish_e820_parsing();
338 e820_register_active_regions(0, 0, -1UL);
340 * partially used pages are not usable - thus
341 * we are rounding upwards:
343 end_pfn = e820_end_of_ram();
344 num_physpages = end_pfn;
350 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
359 /* setup to use the static apicid table during kernel startup */
360 x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
365 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
366 * Call this early for SRAT node setup.
368 acpi_boot_table_init();
371 /* How many end-of-memory variables you have, grandma! */
372 max_low_pfn = end_pfn;
374 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
376 /* Remove active ranges so rediscovery with NUMA-awareness happens */
377 remove_all_active_ranges();
379 #ifdef CONFIG_ACPI_NUMA
381 * Parse SRAT to discover nodes.
387 numa_initmem_init(0, end_pfn);
389 contig_initmem_init(0, end_pfn);
392 /* Reserve direct mapping */
393 reserve_bootmem_generic(table_start << PAGE_SHIFT,
394 (table_end - table_start) << PAGE_SHIFT);
397 reserve_bootmem_generic(__pa_symbol(&_text),
398 __pa_symbol(&_end) - __pa_symbol(&_text));
401 * reserve physical page 0 - it's a special BIOS page on many boxes,
402 * enabling clean reboots, SMP operation, laptop functions.
404 reserve_bootmem_generic(0, PAGE_SIZE);
406 /* reserve ebda region */
408 reserve_bootmem_generic(ebda_addr, ebda_size);
410 /* reserve nodemap region */
412 reserve_bootmem_generic(nodemap_addr, nodemap_size);
416 /* Reserve SMP trampoline */
417 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
420 #ifdef CONFIG_ACPI_SLEEP
422 * Reserve low memory region for sleep support.
424 acpi_reserve_bootmem();
429 efi_reserve_bootmem();
433 * Find and reserve possible boot-time SMP configuration:
436 #ifdef CONFIG_BLK_DEV_INITRD
437 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
438 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
439 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
440 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
441 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
443 if (ramdisk_end <= end_of_mem) {
444 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
445 initrd_start = ramdisk_image + PAGE_OFFSET;
446 initrd_end = initrd_start+ramdisk_size;
448 printk(KERN_ERR "initrd extends beyond end of memory "
449 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
450 ramdisk_end, end_of_mem);
455 reserve_crashkernel();
462 * set this early, so we dont allocate cpu0
463 * if MADT list doesnt list BSP first
464 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
466 cpu_set(0, cpu_present_map);
469 * Read APIC and some other early information from ACPI tables.
477 * get boot-time SMP configuration:
479 if (smp_found_config)
481 init_apic_mappings();
482 ioapic_init_mappings();
485 * We trust e820 completely. No explicit ROM probing in memory.
487 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
488 e820_mark_nosave_regions();
490 /* request I/O space for devices used on all i[345]86 PCs */
491 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
492 request_resource(&ioport_resource, &standard_io_resources[i]);
497 #if defined(CONFIG_VGA_CONSOLE)
498 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
499 conswitchp = &vga_con;
500 #elif defined(CONFIG_DUMMY_CONSOLE)
501 conswitchp = &dummy_con;
506 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
510 if (c->extended_cpuid_level < 0x80000004)
513 v = (unsigned int *) c->x86_model_id;
514 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
515 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
516 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
517 c->x86_model_id[48] = 0;
522 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
524 unsigned int n, dummy, eax, ebx, ecx, edx;
526 n = c->extended_cpuid_level;
528 if (n >= 0x80000005) {
529 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
530 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
531 "D cache %dK (%d bytes/line)\n",
532 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
533 c->x86_cache_size = (ecx>>24) + (edx>>24);
534 /* On K8 L1 TLB is inclusive, so don't count it */
538 if (n >= 0x80000006) {
539 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
540 ecx = cpuid_ecx(0x80000006);
541 c->x86_cache_size = ecx >> 16;
542 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
544 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
545 c->x86_cache_size, ecx & 0xFF);
547 if (n >= 0x80000008) {
548 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
549 c->x86_virt_bits = (eax >> 8) & 0xff;
550 c->x86_phys_bits = eax & 0xff;
555 static int nearby_node(int apicid)
559 for (i = apicid - 1; i >= 0; i--) {
560 node = apicid_to_node[i];
561 if (node != NUMA_NO_NODE && node_online(node))
564 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
565 node = apicid_to_node[i];
566 if (node != NUMA_NO_NODE && node_online(node))
569 return first_node(node_online_map); /* Shouldn't happen */
574 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
575 * Assumes number of cores is a power of two.
577 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
582 int cpu = smp_processor_id();
584 unsigned apicid = hard_smp_processor_id();
586 bits = c->x86_coreid_bits;
588 /* Low order bits define the core id (index of core in socket) */
589 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
590 /* Convert the APIC ID into the socket ID */
591 c->phys_proc_id = phys_pkg_id(bits);
594 node = c->phys_proc_id;
595 if (apicid_to_node[apicid] != NUMA_NO_NODE)
596 node = apicid_to_node[apicid];
597 if (!node_online(node)) {
598 /* Two possibilities here:
599 - The CPU is missing memory and no node was created.
600 In that case try picking one from a nearby CPU
601 - The APIC IDs differ from the HyperTransport node IDs
602 which the K8 northbridge parsing fills in.
603 Assume they are all increased by a constant offset,
604 but in the same order as the HT nodeids.
605 If that doesn't result in a usable node fall back to the
606 path for the previous case. */
608 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
610 if (ht_nodeid >= 0 &&
611 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
612 node = apicid_to_node[ht_nodeid];
613 /* Pick a nearby node */
614 if (!node_online(node))
615 node = nearby_node(apicid);
617 numa_set_node(cpu, node);
619 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
624 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
629 /* Multi core CPU? */
630 if (c->extended_cpuid_level < 0x80000008)
633 ecx = cpuid_ecx(0x80000008);
635 c->x86_max_cores = (ecx & 0xff) + 1;
637 /* CPU telling us the core id bits shift? */
638 bits = (ecx >> 12) & 0xF;
640 /* Otherwise recompute */
642 while ((1 << bits) < c->x86_max_cores)
646 c->x86_coreid_bits = bits;
651 #define ENABLE_C1E_MASK 0x18000000
652 #define CPUID_PROCESSOR_SIGNATURE 1
653 #define CPUID_XFAM 0x0ff00000
654 #define CPUID_XFAM_K8 0x00000000
655 #define CPUID_XFAM_10H 0x00100000
656 #define CPUID_XFAM_11H 0x00200000
657 #define CPUID_XMOD 0x000f0000
658 #define CPUID_XMOD_REV_F 0x00040000
660 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
661 static __cpuinit int amd_apic_timer_broken(void)
663 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
665 switch (eax & CPUID_XFAM) {
667 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
671 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
672 if (lo & ENABLE_C1E_MASK)
676 /* err on the side of caution */
682 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
684 early_init_amd_mc(c);
686 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
687 if (c->x86_power & (1<<8))
688 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
691 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
699 * Disable TLB flush filter by setting HWCR.FFDIS on K8
700 * bit 6 of msr C001_0015
702 * Errata 63 for SH-B3 steppings
703 * Errata 122 for all steppings (F+ have it disabled by default)
706 rdmsrl(MSR_K8_HWCR, value);
708 wrmsrl(MSR_K8_HWCR, value);
712 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
713 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
714 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
716 /* On C+ stepping K8 rep microcode works well for copy/memset */
717 level = cpuid_eax(1);
718 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
720 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
721 if (c->x86 == 0x10 || c->x86 == 0x11)
722 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
724 /* Enable workaround for FXSAVE leak */
726 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
728 level = get_model_name(c);
732 /* Should distinguish Models here, but this is only
733 a fallback anyways. */
734 strcpy(c->x86_model_id, "Hammer");
738 display_cacheinfo(c);
740 /* Multi core CPU? */
741 if (c->extended_cpuid_level >= 0x80000008)
744 if (c->extended_cpuid_level >= 0x80000006 &&
745 (cpuid_edx(0x80000006) & 0xf000))
746 num_cache_leaves = 4;
748 num_cache_leaves = 3;
750 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
751 set_cpu_cap(c, X86_FEATURE_K8);
753 /* MFENCE stops RDTSC speculation */
754 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
756 /* Family 10 doesn't support C states in MWAIT so don't use it */
757 if (c->x86 == 0x10 && !force_mwait)
758 clear_cpu_cap(c, X86_FEATURE_MWAIT);
760 if (amd_apic_timer_broken())
761 disable_apic_timer = 1;
764 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
767 u32 eax, ebx, ecx, edx;
768 int index_msb, core_bits;
770 cpuid(1, &eax, &ebx, &ecx, &edx);
773 if (!cpu_has(c, X86_FEATURE_HT))
775 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
778 smp_num_siblings = (ebx & 0xff0000) >> 16;
780 if (smp_num_siblings == 1) {
781 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
782 } else if (smp_num_siblings > 1) {
784 if (smp_num_siblings > NR_CPUS) {
785 printk(KERN_WARNING "CPU: Unsupported number of "
786 "siblings %d", smp_num_siblings);
787 smp_num_siblings = 1;
791 index_msb = get_count_order(smp_num_siblings);
792 c->phys_proc_id = phys_pkg_id(index_msb);
794 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
796 index_msb = get_count_order(smp_num_siblings);
798 core_bits = get_count_order(c->x86_max_cores);
800 c->cpu_core_id = phys_pkg_id(index_msb) &
801 ((1 << core_bits) - 1);
804 if ((c->x86_max_cores * smp_num_siblings) > 1) {
805 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
807 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
815 * find out the number of processor cores on the die
817 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
821 if (c->cpuid_level < 4)
824 cpuid_count(4, 0, &eax, &t, &t, &t);
827 return ((eax >> 26) + 1);
832 static void srat_detect_node(void)
836 int cpu = smp_processor_id();
837 int apicid = hard_smp_processor_id();
839 /* Don't do the funky fallback heuristics the AMD version employs
841 node = apicid_to_node[apicid];
842 if (node == NUMA_NO_NODE)
843 node = first_node(node_online_map);
844 numa_set_node(cpu, node);
846 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
850 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
852 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
853 (c->x86 == 0x6 && c->x86_model >= 0x0e))
854 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
857 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
862 init_intel_cacheinfo(c);
863 if (c->cpuid_level > 9) {
864 unsigned eax = cpuid_eax(10);
865 /* Check for version and the number of counters */
866 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
867 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
872 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
874 set_cpu_cap(c, X86_FEATURE_BTS);
876 set_cpu_cap(c, X86_FEATURE_PEBS);
883 n = c->extended_cpuid_level;
884 if (n >= 0x80000008) {
885 unsigned eax = cpuid_eax(0x80000008);
886 c->x86_virt_bits = (eax >> 8) & 0xff;
887 c->x86_phys_bits = eax & 0xff;
888 /* CPUID workaround for Intel 0F34 CPU */
889 if (c->x86_vendor == X86_VENDOR_INTEL &&
890 c->x86 == 0xF && c->x86_model == 0x3 &&
892 c->x86_phys_bits = 36;
896 c->x86_cache_alignment = c->x86_clflush_size * 2;
897 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
898 (c->x86 == 0x6 && c->x86_model >= 0x0e))
899 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
901 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
902 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
903 c->x86_max_cores = intel_num_cpu_cores(c);
908 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
910 char *v = c->x86_vendor_id;
912 if (!strcmp(v, "AuthenticAMD"))
913 c->x86_vendor = X86_VENDOR_AMD;
914 else if (!strcmp(v, "GenuineIntel"))
915 c->x86_vendor = X86_VENDOR_INTEL;
917 c->x86_vendor = X86_VENDOR_UNKNOWN;
920 struct cpu_model_info {
923 char *model_names[16];
926 /* Do some early cpuid on the boot CPU to get some parameter that are
927 needed before check_bugs. Everything advanced is in identify_cpu
929 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
933 c->loops_per_jiffy = loops_per_jiffy;
934 c->x86_cache_size = -1;
935 c->x86_vendor = X86_VENDOR_UNKNOWN;
936 c->x86_model = c->x86_mask = 0; /* So far unknown... */
937 c->x86_vendor_id[0] = '\0'; /* Unset */
938 c->x86_model_id[0] = '\0'; /* Unset */
939 c->x86_clflush_size = 64;
940 c->x86_cache_alignment = c->x86_clflush_size;
941 c->x86_max_cores = 1;
942 c->x86_coreid_bits = 0;
943 c->extended_cpuid_level = 0;
944 memset(&c->x86_capability, 0, sizeof c->x86_capability);
946 /* Get vendor name */
947 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
948 (unsigned int *)&c->x86_vendor_id[0],
949 (unsigned int *)&c->x86_vendor_id[8],
950 (unsigned int *)&c->x86_vendor_id[4]);
954 /* Initialize the standard set of capabilities */
955 /* Note that the vendor-specific code below might override */
957 /* Intel-defined flags: level 0x00000001 */
958 if (c->cpuid_level >= 0x00000001) {
960 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
961 &c->x86_capability[0]);
962 c->x86 = (tfms >> 8) & 0xf;
963 c->x86_model = (tfms >> 4) & 0xf;
964 c->x86_mask = tfms & 0xf;
966 c->x86 += (tfms >> 20) & 0xff;
968 c->x86_model += ((tfms >> 16) & 0xF) << 4;
969 if (c->x86_capability[0] & (1<<19))
970 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
972 /* Have CPUID level 0 only - unheard of */
977 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
979 /* AMD-defined flags: level 0x80000001 */
980 xlvl = cpuid_eax(0x80000000);
981 c->extended_cpuid_level = xlvl;
982 if ((xlvl & 0xffff0000) == 0x80000000) {
983 if (xlvl >= 0x80000001) {
984 c->x86_capability[1] = cpuid_edx(0x80000001);
985 c->x86_capability[6] = cpuid_ecx(0x80000001);
987 if (xlvl >= 0x80000004)
988 get_model_name(c); /* Default name */
991 /* Transmeta-defined flags: level 0x80860001 */
992 xlvl = cpuid_eax(0x80860000);
993 if ((xlvl & 0xffff0000) == 0x80860000) {
994 /* Don't set x86_cpuid_level here for now to not confuse. */
995 if (xlvl >= 0x80860001)
996 c->x86_capability[2] = cpuid_edx(0x80860001);
999 c->extended_cpuid_level = cpuid_eax(0x80000000);
1000 if (c->extended_cpuid_level >= 0x80000007)
1001 c->x86_power = cpuid_edx(0x80000007);
1003 switch (c->x86_vendor) {
1004 case X86_VENDOR_AMD:
1012 * This does the hard work of actually picking apart the CPU stuff...
1014 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1018 early_identify_cpu(c);
1020 init_scattered_cpuid_features(c);
1022 c->apicid = phys_pkg_id(0);
1025 * Vendor-specific initialization. In this section we
1026 * canonicalize the feature flags, meaning if there are
1027 * features a certain CPU supports which CPUID doesn't
1028 * tell us, CPUID claiming incorrect flags, or other bugs,
1029 * we handle them here.
1031 * At the end of this section, c->x86_capability better
1032 * indicate the features this CPU genuinely supports!
1034 switch (c->x86_vendor) {
1035 case X86_VENDOR_AMD:
1039 case X86_VENDOR_INTEL:
1043 case X86_VENDOR_UNKNOWN:
1045 display_cacheinfo(c);
1049 select_idle_routine(c);
1053 * On SMP, boot_cpu_data holds the common feature set between
1054 * all CPUs; so make sure that we indicate which features are
1055 * common between the CPUs. The first time this routine gets
1056 * executed, c == &boot_cpu_data.
1058 if (c != &boot_cpu_data) {
1059 /* AND the already accumulated flags with these */
1060 for (i = 0; i < NCAPINTS; i++)
1061 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1064 #ifdef CONFIG_X86_MCE
1067 if (c != &boot_cpu_data)
1070 numa_add_cpu(smp_processor_id());
1073 switch (c->x86_vendor) {
1074 case X86_VENDOR_AMD:
1077 case X86_VENDOR_INTEL:
1078 early_init_intel(c);
1083 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1085 if (c->x86_model_id[0])
1086 printk(KERN_INFO "%s", c->x86_model_id);
1088 if (c->x86_mask || c->cpuid_level >= 0)
1089 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1091 printk(KERN_CONT "\n");
1095 * Get CPU information for use by the procfs.
1098 static int show_cpuinfo(struct seq_file *m, void *v)
1100 struct cpuinfo_x86 *c = v;
1104 * These flag bits must match the definitions in <asm/cpufeature.h>.
1105 * NULL means this bit is undefined or reserved; either way it doesn't
1106 * have meaning as far as Linux is concerned. Note that it's important
1107 * to realize there is a difference between this table and CPUID -- if
1108 * applications want to get the raw CPUID data, they should access
1109 * /dev/cpu/<cpu_nr>/cpuid instead.
1111 static const char *const x86_cap_flags[] = {
1113 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1114 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1115 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1116 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1119 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1120 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1122 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1123 "3dnowext", "3dnow",
1125 /* Transmeta-defined */
1126 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1128 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1129 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1131 /* Other (Linux-defined) */
1132 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1133 NULL, NULL, NULL, NULL,
1134 "constant_tsc", "up", NULL, "arch_perfmon",
1135 "pebs", "bts", NULL, "sync_rdtsc",
1136 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1139 /* Intel-defined (#2) */
1140 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1141 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1142 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1143 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1145 /* VIA/Cyrix/Centaur-defined */
1146 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1147 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1148 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1149 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1151 /* AMD-defined (#2) */
1152 "lahf_lm", "cmp_legacy", "svm", "extapic",
1153 "cr8_legacy", "abm", "sse4a", "misalignsse",
1154 "3dnowprefetch", "osvw", "ibs", "sse5",
1155 "skinit", "wdt", NULL, NULL,
1156 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1157 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1159 /* Auxiliary (Linux-defined) */
1160 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1161 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1162 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1163 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1165 static const char *const x86_power_flags[] = {
1166 "ts", /* temperature sensor */
1167 "fid", /* frequency id control */
1168 "vid", /* voltage id control */
1169 "ttp", /* thermal trip */
1174 "", /* tsc invariant mapped to constant_tsc */
1183 seq_printf(m, "processor\t: %u\n"
1185 "cpu family\t: %d\n"
1187 "model name\t: %s\n",
1189 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1192 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1194 if (c->x86_mask || c->cpuid_level >= 0)
1195 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1197 seq_printf(m, "stepping\t: unknown\n");
1199 if (cpu_has(c, X86_FEATURE_TSC)) {
1200 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1204 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1205 freq / 1000, (freq % 1000));
1209 if (c->x86_cache_size >= 0)
1210 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1213 if (smp_num_siblings * c->x86_max_cores > 1) {
1214 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1215 seq_printf(m, "siblings\t: %d\n",
1216 cpus_weight(per_cpu(cpu_core_map, cpu)));
1217 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1218 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1224 "fpu_exception\t: yes\n"
1225 "cpuid level\t: %d\n"
1230 for (i = 0; i < 32*NCAPINTS; i++)
1231 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1232 seq_printf(m, " %s", x86_cap_flags[i]);
1234 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1235 c->loops_per_jiffy/(500000/HZ),
1236 (c->loops_per_jiffy/(5000/HZ)) % 100);
1238 if (c->x86_tlbsize > 0)
1239 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1240 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1241 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1243 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1244 c->x86_phys_bits, c->x86_virt_bits);
1246 seq_printf(m, "power management:");
1247 for (i = 0; i < 32; i++) {
1248 if (c->x86_power & (1 << i)) {
1249 if (i < ARRAY_SIZE(x86_power_flags) &&
1251 seq_printf(m, "%s%s",
1252 x86_power_flags[i][0]?" ":"",
1253 x86_power_flags[i]);
1255 seq_printf(m, " [%d]", i);
1259 seq_printf(m, "\n\n");
1264 static void *c_start(struct seq_file *m, loff_t *pos)
1266 if (*pos == 0) /* just in case, cpu 0 is not the first */
1267 *pos = first_cpu(cpu_online_map);
1268 if ((*pos) < NR_CPUS && cpu_online(*pos))
1269 return &cpu_data(*pos);
1273 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1275 *pos = next_cpu(*pos, cpu_online_map);
1276 return c_start(m, pos);
1279 static void c_stop(struct seq_file *m, void *v)
1283 struct seq_operations cpuinfo_op = {
1287 .show = show_cpuinfo,