2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/mmzone.h>
37 #include <linux/kexec.h>
38 #include <linux/cpufreq.h>
39 #include <linux/dmi.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ctype.h>
44 #include <asm/uaccess.h>
45 #include <asm/system.h>
50 #include <video/edid.h>
53 #include <asm/mpspec.h>
54 #include <asm/mmu_context.h>
55 #include <asm/proto.h>
56 #include <asm/setup.h>
57 #include <asm/mach_apic.h>
59 #include <asm/sections.h>
66 struct cpuinfo_x86 boot_cpu_data __read_mostly;
67 EXPORT_SYMBOL(boot_cpu_data);
69 unsigned long mmu_cr4_features;
71 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
74 unsigned long saved_video_mode;
76 int force_mwait __cpuinitdata;
82 char dmi_alloc_data[DMI_MAX_DATA];
87 struct screen_info screen_info;
88 EXPORT_SYMBOL(screen_info);
89 struct sys_desc_table_struct {
90 unsigned short length;
91 unsigned char table[0];
94 struct edid_info edid_info;
95 EXPORT_SYMBOL_GPL(edid_info);
97 extern int root_mountflags;
99 char __initdata command_line[COMMAND_LINE_SIZE];
101 struct resource standard_io_resources[] = {
102 { .name = "dma1", .start = 0x00, .end = 0x1f,
103 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
104 { .name = "pic1", .start = 0x20, .end = 0x21,
105 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
106 { .name = "timer0", .start = 0x40, .end = 0x43,
107 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
108 { .name = "timer1", .start = 0x50, .end = 0x53,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "keyboard", .start = 0x60, .end = 0x6f,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "pic2", .start = 0xa0, .end = 0xa1,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "dma2", .start = 0xc0, .end = 0xdf,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "fpu", .start = 0xf0, .end = 0xff,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
122 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
124 struct resource data_resource = {
125 .name = "Kernel data",
128 .flags = IORESOURCE_RAM,
130 struct resource code_resource = {
131 .name = "Kernel code",
134 .flags = IORESOURCE_RAM,
137 #ifdef CONFIG_PROC_VMCORE
138 /* elfcorehdr= specifies the location of elf core header
139 * stored by the crashed kernel. This option will be passed
140 * by kexec loader to the capture kernel.
142 static int __init setup_elfcorehdr(char *arg)
147 elfcorehdr_addr = memparse(arg, &end);
148 return end > arg ? 0 : -EINVAL;
150 early_param("elfcorehdr", setup_elfcorehdr);
155 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
157 unsigned long bootmap_size, bootmap;
159 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
160 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
162 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
163 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
164 e820_register_active_regions(0, start_pfn, end_pfn);
165 free_bootmem_with_active_regions(0, end_pfn);
166 reserve_bootmem(bootmap, bootmap_size);
170 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
172 #ifdef CONFIG_EDD_MODULE
176 * copy_edd() - Copy the BIOS EDD information
177 * from boot_params into a safe place.
180 static inline void copy_edd(void)
182 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
183 sizeof(edd.mbr_signature));
184 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
185 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
186 edd.edd_info_nr = boot_params.eddbuf_entries;
189 static inline void copy_edd(void)
194 #define EBDA_ADDR_POINTER 0x40E
196 unsigned __initdata ebda_addr;
197 unsigned __initdata ebda_size;
199 static void discover_ebda(void)
202 * there is a real-mode segmented pointer pointing to the
203 * 4K EBDA area at 0x40E
205 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
208 ebda_size = *(unsigned short *)__va(ebda_addr);
210 /* Round EBDA up to pages */
214 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
215 if (ebda_size > 64*1024)
219 void __init setup_arch(char **cmdline_p)
221 printk(KERN_INFO "Command line: %s\n", boot_command_line);
223 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
224 screen_info = boot_params.screen_info;
225 edid_info = boot_params.edid_info;
226 saved_video_mode = boot_params.hdr.vid_mode;
227 bootloader_type = boot_params.hdr.type_of_loader;
229 #ifdef CONFIG_BLK_DEV_RAM
230 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
231 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
232 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
234 setup_memory_region();
237 if (!boot_params.hdr.root_flags)
238 root_mountflags &= ~MS_RDONLY;
239 init_mm.start_code = (unsigned long) &_text;
240 init_mm.end_code = (unsigned long) &_etext;
241 init_mm.end_data = (unsigned long) &_edata;
242 init_mm.brk = (unsigned long) &_end;
244 code_resource.start = virt_to_phys(&_text);
245 code_resource.end = virt_to_phys(&_etext)-1;
246 data_resource.start = virt_to_phys(&_etext);
247 data_resource.end = virt_to_phys(&_edata)-1;
249 early_identify_cpu(&boot_cpu_data);
251 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
252 *cmdline_p = command_line;
256 finish_e820_parsing();
258 e820_register_active_regions(0, 0, -1UL);
260 * partially used pages are not usable - thus
261 * we are rounding upwards:
263 end_pfn = e820_end_of_ram();
264 num_physpages = end_pfn;
270 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
276 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
277 * Call this early for SRAT node setup.
279 acpi_boot_table_init();
282 /* How many end-of-memory variables you have, grandma! */
283 max_low_pfn = end_pfn;
285 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
287 /* Remove active ranges so rediscovery with NUMA-awareness happens */
288 remove_all_active_ranges();
290 #ifdef CONFIG_ACPI_NUMA
292 * Parse SRAT to discover nodes.
298 numa_initmem_init(0, end_pfn);
300 contig_initmem_init(0, end_pfn);
303 /* Reserve direct mapping */
304 reserve_bootmem_generic(table_start << PAGE_SHIFT,
305 (table_end - table_start) << PAGE_SHIFT);
308 reserve_bootmem_generic(__pa_symbol(&_text),
309 __pa_symbol(&_end) - __pa_symbol(&_text));
312 * reserve physical page 0 - it's a special BIOS page on many boxes,
313 * enabling clean reboots, SMP operation, laptop functions.
315 reserve_bootmem_generic(0, PAGE_SIZE);
317 /* reserve ebda region */
319 reserve_bootmem_generic(ebda_addr, ebda_size);
321 /* reserve nodemap region */
323 reserve_bootmem_generic(nodemap_addr, nodemap_size);
327 /* Reserve SMP trampoline */
328 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
331 #ifdef CONFIG_ACPI_SLEEP
333 * Reserve low memory region for sleep support.
335 acpi_reserve_bootmem();
338 * Find and reserve possible boot-time SMP configuration:
341 #ifdef CONFIG_BLK_DEV_INITRD
342 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
343 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
344 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
345 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
346 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
348 if (ramdisk_end <= end_of_mem) {
349 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
350 initrd_start = ramdisk_image + PAGE_OFFSET;
351 initrd_end = initrd_start+ramdisk_size;
353 printk(KERN_ERR "initrd extends beyond end of memory "
354 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
355 ramdisk_end, end_of_mem);
361 if (crashk_res.start != crashk_res.end) {
362 reserve_bootmem_generic(crashk_res.start,
363 crashk_res.end - crashk_res.start + 1);
374 * set this early, so we dont allocate cpu0
375 * if MADT list doesnt list BSP first
376 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
378 cpu_set(0, cpu_present_map);
381 * Read APIC and some other early information from ACPI tables.
389 * get boot-time SMP configuration:
391 if (smp_found_config)
393 init_apic_mappings();
396 * We trust e820 completely. No explicit ROM probing in memory.
398 e820_reserve_resources();
399 e820_mark_nosave_regions();
403 /* request I/O space for devices used on all i[345]86 PCs */
404 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
405 request_resource(&ioport_resource, &standard_io_resources[i]);
411 #if defined(CONFIG_VGA_CONSOLE)
412 conswitchp = &vga_con;
413 #elif defined(CONFIG_DUMMY_CONSOLE)
414 conswitchp = &dummy_con;
419 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
423 if (c->extended_cpuid_level < 0x80000004)
426 v = (unsigned int *) c->x86_model_id;
427 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
428 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
429 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
430 c->x86_model_id[48] = 0;
435 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
437 unsigned int n, dummy, eax, ebx, ecx, edx;
439 n = c->extended_cpuid_level;
441 if (n >= 0x80000005) {
442 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
443 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
444 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
445 c->x86_cache_size=(ecx>>24)+(edx>>24);
446 /* On K8 L1 TLB is inclusive, so don't count it */
450 if (n >= 0x80000006) {
451 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
452 ecx = cpuid_ecx(0x80000006);
453 c->x86_cache_size = ecx >> 16;
454 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
456 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
457 c->x86_cache_size, ecx & 0xFF);
461 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
462 if (n >= 0x80000008) {
463 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
464 c->x86_virt_bits = (eax >> 8) & 0xff;
465 c->x86_phys_bits = eax & 0xff;
470 static int nearby_node(int apicid)
473 for (i = apicid - 1; i >= 0; i--) {
474 int node = apicid_to_node[i];
475 if (node != NUMA_NO_NODE && node_online(node))
478 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
479 int node = apicid_to_node[i];
480 if (node != NUMA_NO_NODE && node_online(node))
483 return first_node(node_online_map); /* Shouldn't happen */
488 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
489 * Assumes number of cores is a power of two.
491 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
496 int cpu = smp_processor_id();
498 unsigned apicid = hard_smp_processor_id();
500 unsigned ecx = cpuid_ecx(0x80000008);
502 c->x86_max_cores = (ecx & 0xff) + 1;
504 /* CPU telling us the core id bits shift? */
505 bits = (ecx >> 12) & 0xF;
507 /* Otherwise recompute */
509 while ((1 << bits) < c->x86_max_cores)
513 /* Low order bits define the core id (index of core in socket) */
514 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
515 /* Convert the APIC ID into the socket ID */
516 c->phys_proc_id = phys_pkg_id(bits);
519 node = c->phys_proc_id;
520 if (apicid_to_node[apicid] != NUMA_NO_NODE)
521 node = apicid_to_node[apicid];
522 if (!node_online(node)) {
523 /* Two possibilities here:
524 - The CPU is missing memory and no node was created.
525 In that case try picking one from a nearby CPU
526 - The APIC IDs differ from the HyperTransport node IDs
527 which the K8 northbridge parsing fills in.
528 Assume they are all increased by a constant offset,
529 but in the same order as the HT nodeids.
530 If that doesn't result in a usable node fall back to the
531 path for the previous case. */
532 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
533 if (ht_nodeid >= 0 &&
534 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
535 node = apicid_to_node[ht_nodeid];
536 /* Pick a nearby node */
537 if (!node_online(node))
538 node = nearby_node(apicid);
540 numa_set_node(cpu, node);
542 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
547 #define ENABLE_C1E_MASK 0x18000000
548 #define CPUID_PROCESSOR_SIGNATURE 1
549 #define CPUID_XFAM 0x0ff00000
550 #define CPUID_XFAM_K8 0x00000000
551 #define CPUID_XFAM_10H 0x00100000
552 #define CPUID_XFAM_11H 0x00200000
553 #define CPUID_XMOD 0x000f0000
554 #define CPUID_XMOD_REV_F 0x00040000
556 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
557 static __cpuinit int amd_apic_timer_broken(void)
560 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
561 switch (eax & CPUID_XFAM) {
563 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
567 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
568 if (lo & ENABLE_C1E_MASK)
572 /* err on the side of caution */
578 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
586 * Disable TLB flush filter by setting HWCR.FFDIS on K8
587 * bit 6 of msr C001_0015
589 * Errata 63 for SH-B3 steppings
590 * Errata 122 for all steppings (F+ have it disabled by default)
593 rdmsrl(MSR_K8_HWCR, value);
595 wrmsrl(MSR_K8_HWCR, value);
599 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
600 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
601 clear_bit(0*32+31, &c->x86_capability);
603 /* On C+ stepping K8 rep microcode works well for copy/memset */
604 level = cpuid_eax(1);
605 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
606 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
607 if (c->x86 == 0x10 || c->x86 == 0x11)
608 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
610 /* Enable workaround for FXSAVE leak */
612 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
614 level = get_model_name(c);
618 /* Should distinguish Models here, but this is only
619 a fallback anyways. */
620 strcpy(c->x86_model_id, "Hammer");
624 display_cacheinfo(c);
626 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
627 if (c->x86_power & (1<<8))
628 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
630 /* Multi core CPU? */
631 if (c->extended_cpuid_level >= 0x80000008)
634 if (c->extended_cpuid_level >= 0x80000006 &&
635 (cpuid_edx(0x80000006) & 0xf000))
636 num_cache_leaves = 4;
638 num_cache_leaves = 3;
640 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
641 set_bit(X86_FEATURE_K8, &c->x86_capability);
643 /* RDTSC can be speculated around */
644 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
646 /* Family 10 doesn't support C states in MWAIT so don't use it */
647 if (c->x86 == 0x10 && !force_mwait)
648 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
650 if (amd_apic_timer_broken())
651 disable_apic_timer = 1;
654 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
657 u32 eax, ebx, ecx, edx;
658 int index_msb, core_bits;
660 cpuid(1, &eax, &ebx, &ecx, &edx);
663 if (!cpu_has(c, X86_FEATURE_HT))
665 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
668 smp_num_siblings = (ebx & 0xff0000) >> 16;
670 if (smp_num_siblings == 1) {
671 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
672 } else if (smp_num_siblings > 1 ) {
674 if (smp_num_siblings > NR_CPUS) {
675 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
676 smp_num_siblings = 1;
680 index_msb = get_count_order(smp_num_siblings);
681 c->phys_proc_id = phys_pkg_id(index_msb);
683 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
685 index_msb = get_count_order(smp_num_siblings) ;
687 core_bits = get_count_order(c->x86_max_cores);
689 c->cpu_core_id = phys_pkg_id(index_msb) &
690 ((1 << core_bits) - 1);
693 if ((c->x86_max_cores * smp_num_siblings) > 1) {
694 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
695 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
702 * find out the number of processor cores on the die
704 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
708 if (c->cpuid_level < 4)
711 cpuid_count(4, 0, &eax, &t, &t, &t);
714 return ((eax >> 26) + 1);
719 static void srat_detect_node(void)
723 int cpu = smp_processor_id();
724 int apicid = hard_smp_processor_id();
726 /* Don't do the funky fallback heuristics the AMD version employs
728 node = apicid_to_node[apicid];
729 if (node == NUMA_NO_NODE)
730 node = first_node(node_online_map);
731 numa_set_node(cpu, node);
733 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
737 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
742 init_intel_cacheinfo(c);
743 if (c->cpuid_level > 9 ) {
744 unsigned eax = cpuid_eax(10);
745 /* Check for version and the number of counters */
746 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
747 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
752 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
754 set_bit(X86_FEATURE_BTS, c->x86_capability);
756 set_bit(X86_FEATURE_PEBS, c->x86_capability);
759 n = c->extended_cpuid_level;
760 if (n >= 0x80000008) {
761 unsigned eax = cpuid_eax(0x80000008);
762 c->x86_virt_bits = (eax >> 8) & 0xff;
763 c->x86_phys_bits = eax & 0xff;
764 /* CPUID workaround for Intel 0F34 CPU */
765 if (c->x86_vendor == X86_VENDOR_INTEL &&
766 c->x86 == 0xF && c->x86_model == 0x3 &&
768 c->x86_phys_bits = 36;
772 c->x86_cache_alignment = c->x86_clflush_size * 2;
773 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
774 (c->x86 == 0x6 && c->x86_model >= 0x0e))
775 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
777 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
779 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
781 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
782 c->x86_max_cores = intel_num_cpu_cores(c);
787 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
789 char *v = c->x86_vendor_id;
791 if (!strcmp(v, "AuthenticAMD"))
792 c->x86_vendor = X86_VENDOR_AMD;
793 else if (!strcmp(v, "GenuineIntel"))
794 c->x86_vendor = X86_VENDOR_INTEL;
796 c->x86_vendor = X86_VENDOR_UNKNOWN;
799 struct cpu_model_info {
802 char *model_names[16];
805 /* Do some early cpuid on the boot CPU to get some parameter that are
806 needed before check_bugs. Everything advanced is in identify_cpu
808 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
812 c->loops_per_jiffy = loops_per_jiffy;
813 c->x86_cache_size = -1;
814 c->x86_vendor = X86_VENDOR_UNKNOWN;
815 c->x86_model = c->x86_mask = 0; /* So far unknown... */
816 c->x86_vendor_id[0] = '\0'; /* Unset */
817 c->x86_model_id[0] = '\0'; /* Unset */
818 c->x86_clflush_size = 64;
819 c->x86_cache_alignment = c->x86_clflush_size;
820 c->x86_max_cores = 1;
821 c->extended_cpuid_level = 0;
822 memset(&c->x86_capability, 0, sizeof c->x86_capability);
824 /* Get vendor name */
825 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
826 (unsigned int *)&c->x86_vendor_id[0],
827 (unsigned int *)&c->x86_vendor_id[8],
828 (unsigned int *)&c->x86_vendor_id[4]);
832 /* Initialize the standard set of capabilities */
833 /* Note that the vendor-specific code below might override */
835 /* Intel-defined flags: level 0x00000001 */
836 if (c->cpuid_level >= 0x00000001) {
838 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
839 &c->x86_capability[0]);
840 c->x86 = (tfms >> 8) & 0xf;
841 c->x86_model = (tfms >> 4) & 0xf;
842 c->x86_mask = tfms & 0xf;
844 c->x86 += (tfms >> 20) & 0xff;
846 c->x86_model += ((tfms >> 16) & 0xF) << 4;
847 if (c->x86_capability[0] & (1<<19))
848 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
850 /* Have CPUID level 0 only - unheard of */
855 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
860 * This does the hard work of actually picking apart the CPU stuff...
862 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
867 early_identify_cpu(c);
869 /* AMD-defined flags: level 0x80000001 */
870 xlvl = cpuid_eax(0x80000000);
871 c->extended_cpuid_level = xlvl;
872 if ((xlvl & 0xffff0000) == 0x80000000) {
873 if (xlvl >= 0x80000001) {
874 c->x86_capability[1] = cpuid_edx(0x80000001);
875 c->x86_capability[6] = cpuid_ecx(0x80000001);
877 if (xlvl >= 0x80000004)
878 get_model_name(c); /* Default name */
881 /* Transmeta-defined flags: level 0x80860001 */
882 xlvl = cpuid_eax(0x80860000);
883 if ((xlvl & 0xffff0000) == 0x80860000) {
884 /* Don't set x86_cpuid_level here for now to not confuse. */
885 if (xlvl >= 0x80860001)
886 c->x86_capability[2] = cpuid_edx(0x80860001);
889 init_scattered_cpuid_features(c);
891 c->apicid = phys_pkg_id(0);
894 * Vendor-specific initialization. In this section we
895 * canonicalize the feature flags, meaning if there are
896 * features a certain CPU supports which CPUID doesn't
897 * tell us, CPUID claiming incorrect flags, or other bugs,
898 * we handle them here.
900 * At the end of this section, c->x86_capability better
901 * indicate the features this CPU genuinely supports!
903 switch (c->x86_vendor) {
908 case X86_VENDOR_INTEL:
912 case X86_VENDOR_UNKNOWN:
914 display_cacheinfo(c);
918 select_idle_routine(c);
922 * On SMP, boot_cpu_data holds the common feature set between
923 * all CPUs; so make sure that we indicate which features are
924 * common between the CPUs. The first time this routine gets
925 * executed, c == &boot_cpu_data.
927 if (c != &boot_cpu_data) {
928 /* AND the already accumulated flags with these */
929 for (i = 0 ; i < NCAPINTS ; i++)
930 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
933 #ifdef CONFIG_X86_MCE
936 if (c != &boot_cpu_data)
939 numa_add_cpu(smp_processor_id());
944 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
946 if (c->x86_model_id[0])
947 printk("%s", c->x86_model_id);
949 if (c->x86_mask || c->cpuid_level >= 0)
950 printk(" stepping %02x\n", c->x86_mask);
956 * Get CPU information for use by the procfs.
959 static int show_cpuinfo(struct seq_file *m, void *v)
961 struct cpuinfo_x86 *c = v;
964 * These flag bits must match the definitions in <asm/cpufeature.h>.
965 * NULL means this bit is undefined or reserved; either way it doesn't
966 * have meaning as far as Linux is concerned. Note that it's important
967 * to realize there is a difference between this table and CPUID -- if
968 * applications want to get the raw CPUID data, they should access
969 * /dev/cpu/<cpu_nr>/cpuid instead.
971 static const char *const x86_cap_flags[] = {
973 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
974 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
975 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
976 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
979 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
980 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
981 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
982 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
985 /* Transmeta-defined */
986 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
991 /* Other (Linux-defined) */
992 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
993 NULL, NULL, NULL, NULL,
994 "constant_tsc", "up", NULL, "arch_perfmon",
995 "pebs", "bts", NULL, "sync_rdtsc",
996 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
997 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
999 /* Intel-defined (#2) */
1000 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1001 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1002 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
1003 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1005 /* VIA/Cyrix/Centaur-defined */
1006 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1007 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1008 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1011 /* AMD-defined (#2) */
1012 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
1013 "altmovcr8", "abm", "sse4a",
1014 "misalignsse", "3dnowprefetch",
1015 "osvw", "ibs", NULL, NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1019 /* Auxiliary (Linux-defined) */
1020 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1021 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1022 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1025 static const char *const x86_power_flags[] = {
1026 "ts", /* temperature sensor */
1027 "fid", /* frequency id control */
1028 "vid", /* voltage id control */
1029 "ttp", /* thermal trip */
1034 "", /* tsc invariant mapped to constant_tsc */
1040 if (!cpu_online(c-cpu_data))
1044 seq_printf(m,"processor\t: %u\n"
1046 "cpu family\t: %d\n"
1048 "model name\t: %s\n",
1049 (unsigned)(c-cpu_data),
1050 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1053 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1055 if (c->x86_mask || c->cpuid_level >= 0)
1056 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1058 seq_printf(m, "stepping\t: unknown\n");
1060 if (cpu_has(c,X86_FEATURE_TSC)) {
1061 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1064 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1065 freq / 1000, (freq % 1000));
1069 if (c->x86_cache_size >= 0)
1070 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1073 if (smp_num_siblings * c->x86_max_cores > 1) {
1074 int cpu = c - cpu_data;
1075 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1076 seq_printf(m, "siblings\t: %d\n",
1077 cpus_weight(per_cpu(cpu_core_map, cpu)));
1078 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1079 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1085 "fpu_exception\t: yes\n"
1086 "cpuid level\t: %d\n"
1093 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1094 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1095 seq_printf(m, " %s", x86_cap_flags[i]);
1098 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1099 c->loops_per_jiffy/(500000/HZ),
1100 (c->loops_per_jiffy/(5000/HZ)) % 100);
1102 if (c->x86_tlbsize > 0)
1103 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1104 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1105 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1107 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1108 c->x86_phys_bits, c->x86_virt_bits);
1110 seq_printf(m, "power management:");
1113 for (i = 0; i < 32; i++)
1114 if (c->x86_power & (1 << i)) {
1115 if (i < ARRAY_SIZE(x86_power_flags) &&
1117 seq_printf(m, "%s%s",
1118 x86_power_flags[i][0]?" ":"",
1119 x86_power_flags[i]);
1121 seq_printf(m, " [%d]", i);
1125 seq_printf(m, "\n\n");
1130 static void *c_start(struct seq_file *m, loff_t *pos)
1132 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1135 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1138 return c_start(m, pos);
1141 static void c_stop(struct seq_file *m, void *v)
1145 struct seq_operations cpuinfo_op = {
1149 .show = show_cpuinfo,