2 * linux/arch/x86-64/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
11 * This file handles the architecture-dependent parts of initialization
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
18 #include <linux/stddef.h>
19 #include <linux/unistd.h>
20 #include <linux/ptrace.h>
21 #include <linux/slab.h>
22 #include <linux/user.h>
23 #include <linux/a.out.h>
24 #include <linux/screen_info.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/initrd.h>
29 #include <linux/highmem.h>
30 #include <linux/bootmem.h>
31 #include <linux/module.h>
32 #include <asm/processor.h>
33 #include <linux/console.h>
34 #include <linux/seq_file.h>
35 #include <linux/crash_dump.h>
36 #include <linux/root_dev.h>
37 #include <linux/pci.h>
38 #include <linux/acpi.h>
39 #include <linux/kallsyms.h>
40 #include <linux/edd.h>
41 #include <linux/mmzone.h>
42 #include <linux/kexec.h>
43 #include <linux/cpufreq.h>
44 #include <linux/dmi.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/ctype.h>
49 #include <asm/uaccess.h>
50 #include <asm/system.h>
55 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/bootsetup.h>
61 #include <asm/proto.h>
62 #include <asm/setup.h>
63 #include <asm/mach_apic.h>
65 #include <asm/sections.h>
72 struct cpuinfo_x86 boot_cpu_data __read_mostly;
73 EXPORT_SYMBOL(boot_cpu_data);
75 unsigned long mmu_cr4_features;
77 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
80 unsigned long saved_video_mode;
82 int force_mwait __cpuinitdata;
88 char dmi_alloc_data[DMI_MAX_DATA];
93 struct screen_info screen_info;
94 EXPORT_SYMBOL(screen_info);
95 struct sys_desc_table_struct {
96 unsigned short length;
97 unsigned char table[0];
100 struct edid_info edid_info;
101 EXPORT_SYMBOL_GPL(edid_info);
103 extern int root_mountflags;
105 char __initdata command_line[COMMAND_LINE_SIZE];
107 struct resource standard_io_resources[] = {
108 { .name = "dma1", .start = 0x00, .end = 0x1f,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "pic1", .start = 0x20, .end = 0x21,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "timer0", .start = 0x40, .end = 0x43,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "timer1", .start = 0x50, .end = 0x53,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "keyboard", .start = 0x60, .end = 0x6f,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "pic2", .start = 0xa0, .end = 0xa1,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "dma2", .start = 0xc0, .end = 0xdf,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "fpu", .start = 0xf0, .end = 0xff,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
128 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
130 struct resource data_resource = {
131 .name = "Kernel data",
134 .flags = IORESOURCE_RAM,
136 struct resource code_resource = {
137 .name = "Kernel code",
140 .flags = IORESOURCE_RAM,
143 #ifdef CONFIG_PROC_VMCORE
144 /* elfcorehdr= specifies the location of elf core header
145 * stored by the crashed kernel. This option will be passed
146 * by kexec loader to the capture kernel.
148 static int __init setup_elfcorehdr(char *arg)
153 elfcorehdr_addr = memparse(arg, &end);
154 return end > arg ? 0 : -EINVAL;
156 early_param("elfcorehdr", setup_elfcorehdr);
161 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
163 unsigned long bootmap_size, bootmap;
165 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
166 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
168 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
169 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
170 e820_register_active_regions(0, start_pfn, end_pfn);
171 free_bootmem_with_active_regions(0, end_pfn);
172 reserve_bootmem(bootmap, bootmap_size);
176 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
178 #ifdef CONFIG_EDD_MODULE
182 * copy_edd() - Copy the BIOS EDD information
183 * from boot_params into a safe place.
186 static inline void copy_edd(void)
188 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
189 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
190 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
191 edd.edd_info_nr = EDD_NR;
194 static inline void copy_edd(void)
199 #define EBDA_ADDR_POINTER 0x40E
201 unsigned __initdata ebda_addr;
202 unsigned __initdata ebda_size;
204 static void discover_ebda(void)
207 * there is a real-mode segmented pointer pointing to the
208 * 4K EBDA area at 0x40E
210 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
213 ebda_size = *(unsigned short *)__va(ebda_addr);
215 /* Round EBDA up to pages */
219 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
220 if (ebda_size > 64*1024)
224 void __init setup_arch(char **cmdline_p)
226 printk(KERN_INFO "Command line: %s\n", boot_command_line);
228 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
229 screen_info = SCREEN_INFO;
230 edid_info = EDID_INFO;
231 saved_video_mode = SAVED_VIDEO_MODE;
232 bootloader_type = LOADER_TYPE;
234 #ifdef CONFIG_BLK_DEV_RAM
235 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
236 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
237 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
239 setup_memory_region();
242 if (!MOUNT_ROOT_RDONLY)
243 root_mountflags &= ~MS_RDONLY;
244 init_mm.start_code = (unsigned long) &_text;
245 init_mm.end_code = (unsigned long) &_etext;
246 init_mm.end_data = (unsigned long) &_edata;
247 init_mm.brk = (unsigned long) &_end;
249 code_resource.start = virt_to_phys(&_text);
250 code_resource.end = virt_to_phys(&_etext)-1;
251 data_resource.start = virt_to_phys(&_etext);
252 data_resource.end = virt_to_phys(&_edata)-1;
254 early_identify_cpu(&boot_cpu_data);
256 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
257 *cmdline_p = command_line;
261 finish_e820_parsing();
263 e820_register_active_regions(0, 0, -1UL);
265 * partially used pages are not usable - thus
266 * we are rounding upwards:
268 end_pfn = e820_end_of_ram();
269 num_physpages = end_pfn;
275 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
281 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
282 * Call this early for SRAT node setup.
284 acpi_boot_table_init();
287 /* How many end-of-memory variables you have, grandma! */
288 max_low_pfn = end_pfn;
290 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
292 /* Remove active ranges so rediscovery with NUMA-awareness happens */
293 remove_all_active_ranges();
295 #ifdef CONFIG_ACPI_NUMA
297 * Parse SRAT to discover nodes.
303 numa_initmem_init(0, end_pfn);
305 contig_initmem_init(0, end_pfn);
308 /* Reserve direct mapping */
309 reserve_bootmem_generic(table_start << PAGE_SHIFT,
310 (table_end - table_start) << PAGE_SHIFT);
313 reserve_bootmem_generic(__pa_symbol(&_text),
314 __pa_symbol(&_end) - __pa_symbol(&_text));
317 * reserve physical page 0 - it's a special BIOS page on many boxes,
318 * enabling clean reboots, SMP operation, laptop functions.
320 reserve_bootmem_generic(0, PAGE_SIZE);
322 /* reserve ebda region */
324 reserve_bootmem_generic(ebda_addr, ebda_size);
326 /* reserve nodemap region */
328 reserve_bootmem_generic(nodemap_addr, nodemap_size);
332 /* Reserve SMP trampoline */
333 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
336 #ifdef CONFIG_ACPI_SLEEP
338 * Reserve low memory region for sleep support.
340 acpi_reserve_bootmem();
343 * Find and reserve possible boot-time SMP configuration:
346 #ifdef CONFIG_BLK_DEV_INITRD
347 if (LOADER_TYPE && INITRD_START) {
348 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
349 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
350 initrd_start = INITRD_START + PAGE_OFFSET;
351 initrd_end = initrd_start+INITRD_SIZE;
354 printk(KERN_ERR "initrd extends beyond end of memory "
355 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
356 (unsigned long)(INITRD_START + INITRD_SIZE),
357 (unsigned long)(end_pfn << PAGE_SHIFT));
363 if (crashk_res.start != crashk_res.end) {
364 reserve_bootmem_generic(crashk_res.start,
365 crashk_res.end - crashk_res.start + 1);
376 * set this early, so we dont allocate cpu0
377 * if MADT list doesnt list BSP first
378 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
380 cpu_set(0, cpu_present_map);
383 * Read APIC and some other early information from ACPI tables.
391 * get boot-time SMP configuration:
393 if (smp_found_config)
395 init_apic_mappings();
398 * We trust e820 completely. No explicit ROM probing in memory.
400 e820_reserve_resources();
401 e820_mark_nosave_regions();
405 /* request I/O space for devices used on all i[345]86 PCs */
406 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
407 request_resource(&ioport_resource, &standard_io_resources[i]);
413 #if defined(CONFIG_VGA_CONSOLE)
414 conswitchp = &vga_con;
415 #elif defined(CONFIG_DUMMY_CONSOLE)
416 conswitchp = &dummy_con;
421 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
425 if (c->extended_cpuid_level < 0x80000004)
428 v = (unsigned int *) c->x86_model_id;
429 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
430 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
431 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
432 c->x86_model_id[48] = 0;
437 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
439 unsigned int n, dummy, eax, ebx, ecx, edx;
441 n = c->extended_cpuid_level;
443 if (n >= 0x80000005) {
444 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
445 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
446 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
447 c->x86_cache_size=(ecx>>24)+(edx>>24);
448 /* On K8 L1 TLB is inclusive, so don't count it */
452 if (n >= 0x80000006) {
453 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
454 ecx = cpuid_ecx(0x80000006);
455 c->x86_cache_size = ecx >> 16;
456 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
458 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
459 c->x86_cache_size, ecx & 0xFF);
463 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
464 if (n >= 0x80000008) {
465 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
466 c->x86_virt_bits = (eax >> 8) & 0xff;
467 c->x86_phys_bits = eax & 0xff;
472 static int nearby_node(int apicid)
475 for (i = apicid - 1; i >= 0; i--) {
476 int node = apicid_to_node[i];
477 if (node != NUMA_NO_NODE && node_online(node))
480 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
481 int node = apicid_to_node[i];
482 if (node != NUMA_NO_NODE && node_online(node))
485 return first_node(node_online_map); /* Shouldn't happen */
490 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
491 * Assumes number of cores is a power of two.
493 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
498 int cpu = smp_processor_id();
500 unsigned apicid = hard_smp_processor_id();
502 unsigned ecx = cpuid_ecx(0x80000008);
504 c->x86_max_cores = (ecx & 0xff) + 1;
506 /* CPU telling us the core id bits shift? */
507 bits = (ecx >> 12) & 0xF;
509 /* Otherwise recompute */
511 while ((1 << bits) < c->x86_max_cores)
515 /* Low order bits define the core id (index of core in socket) */
516 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
517 /* Convert the APIC ID into the socket ID */
518 c->phys_proc_id = phys_pkg_id(bits);
521 node = c->phys_proc_id;
522 if (apicid_to_node[apicid] != NUMA_NO_NODE)
523 node = apicid_to_node[apicid];
524 if (!node_online(node)) {
525 /* Two possibilities here:
526 - The CPU is missing memory and no node was created.
527 In that case try picking one from a nearby CPU
528 - The APIC IDs differ from the HyperTransport node IDs
529 which the K8 northbridge parsing fills in.
530 Assume they are all increased by a constant offset,
531 but in the same order as the HT nodeids.
532 If that doesn't result in a usable node fall back to the
533 path for the previous case. */
534 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
535 if (ht_nodeid >= 0 &&
536 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
537 node = apicid_to_node[ht_nodeid];
538 /* Pick a nearby node */
539 if (!node_online(node))
540 node = nearby_node(apicid);
542 numa_set_node(cpu, node);
544 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
549 #define ENABLE_C1E_MASK 0x18000000
550 #define CPUID_PROCESSOR_SIGNATURE 1
551 #define CPUID_XFAM 0x0ff00000
552 #define CPUID_XFAM_K8 0x00000000
553 #define CPUID_XFAM_10H 0x00100000
554 #define CPUID_XFAM_11H 0x00200000
555 #define CPUID_XMOD 0x000f0000
556 #define CPUID_XMOD_REV_F 0x00040000
558 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
559 static __cpuinit int amd_apic_timer_broken(void)
562 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
563 switch (eax & CPUID_XFAM) {
565 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
569 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
570 if (lo & ENABLE_C1E_MASK)
574 /* err on the side of caution */
580 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
588 * Disable TLB flush filter by setting HWCR.FFDIS on K8
589 * bit 6 of msr C001_0015
591 * Errata 63 for SH-B3 steppings
592 * Errata 122 for all steppings (F+ have it disabled by default)
595 rdmsrl(MSR_K8_HWCR, value);
597 wrmsrl(MSR_K8_HWCR, value);
601 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
602 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
603 clear_bit(0*32+31, &c->x86_capability);
605 /* On C+ stepping K8 rep microcode works well for copy/memset */
606 level = cpuid_eax(1);
607 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
608 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
610 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
612 /* Enable workaround for FXSAVE leak */
614 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
616 level = get_model_name(c);
620 /* Should distinguish Models here, but this is only
621 a fallback anyways. */
622 strcpy(c->x86_model_id, "Hammer");
626 display_cacheinfo(c);
628 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
629 if (c->x86_power & (1<<8))
630 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
632 /* Multi core CPU? */
633 if (c->extended_cpuid_level >= 0x80000008)
636 if (c->extended_cpuid_level >= 0x80000006 &&
637 (cpuid_edx(0x80000006) & 0xf000))
638 num_cache_leaves = 4;
640 num_cache_leaves = 3;
642 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
643 set_bit(X86_FEATURE_K8, &c->x86_capability);
645 /* RDTSC can be speculated around */
646 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
648 /* Family 10 doesn't support C states in MWAIT so don't use it */
649 if (c->x86 == 0x10 && !force_mwait)
650 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
652 if (amd_apic_timer_broken())
653 disable_apic_timer = 1;
656 static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
659 u32 eax, ebx, ecx, edx;
660 int index_msb, core_bits;
662 cpuid(1, &eax, &ebx, &ecx, &edx);
665 if (!cpu_has(c, X86_FEATURE_HT))
667 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
670 smp_num_siblings = (ebx & 0xff0000) >> 16;
672 if (smp_num_siblings == 1) {
673 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
674 } else if (smp_num_siblings > 1 ) {
676 if (smp_num_siblings > NR_CPUS) {
677 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
678 smp_num_siblings = 1;
682 index_msb = get_count_order(smp_num_siblings);
683 c->phys_proc_id = phys_pkg_id(index_msb);
685 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
687 index_msb = get_count_order(smp_num_siblings) ;
689 core_bits = get_count_order(c->x86_max_cores);
691 c->cpu_core_id = phys_pkg_id(index_msb) &
692 ((1 << core_bits) - 1);
695 if ((c->x86_max_cores * smp_num_siblings) > 1) {
696 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
697 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
704 * find out the number of processor cores on the die
706 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
710 if (c->cpuid_level < 4)
713 cpuid_count(4, 0, &eax, &t, &t, &t);
716 return ((eax >> 26) + 1);
721 static void srat_detect_node(void)
725 int cpu = smp_processor_id();
726 int apicid = hard_smp_processor_id();
728 /* Don't do the funky fallback heuristics the AMD version employs
730 node = apicid_to_node[apicid];
731 if (node == NUMA_NO_NODE)
732 node = first_node(node_online_map);
733 numa_set_node(cpu, node);
735 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
739 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
744 init_intel_cacheinfo(c);
745 if (c->cpuid_level > 9 ) {
746 unsigned eax = cpuid_eax(10);
747 /* Check for version and the number of counters */
748 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
749 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
754 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
756 set_bit(X86_FEATURE_BTS, c->x86_capability);
758 set_bit(X86_FEATURE_PEBS, c->x86_capability);
761 n = c->extended_cpuid_level;
762 if (n >= 0x80000008) {
763 unsigned eax = cpuid_eax(0x80000008);
764 c->x86_virt_bits = (eax >> 8) & 0xff;
765 c->x86_phys_bits = eax & 0xff;
766 /* CPUID workaround for Intel 0F34 CPU */
767 if (c->x86_vendor == X86_VENDOR_INTEL &&
768 c->x86 == 0xF && c->x86_model == 0x3 &&
770 c->x86_phys_bits = 36;
774 c->x86_cache_alignment = c->x86_clflush_size * 2;
775 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
776 (c->x86 == 0x6 && c->x86_model >= 0x0e))
777 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
779 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
781 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
783 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
784 c->x86_max_cores = intel_num_cpu_cores(c);
789 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
791 char *v = c->x86_vendor_id;
793 if (!strcmp(v, "AuthenticAMD"))
794 c->x86_vendor = X86_VENDOR_AMD;
795 else if (!strcmp(v, "GenuineIntel"))
796 c->x86_vendor = X86_VENDOR_INTEL;
798 c->x86_vendor = X86_VENDOR_UNKNOWN;
801 struct cpu_model_info {
804 char *model_names[16];
807 /* Do some early cpuid on the boot CPU to get some parameter that are
808 needed before check_bugs. Everything advanced is in identify_cpu
810 void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
814 c->loops_per_jiffy = loops_per_jiffy;
815 c->x86_cache_size = -1;
816 c->x86_vendor = X86_VENDOR_UNKNOWN;
817 c->x86_model = c->x86_mask = 0; /* So far unknown... */
818 c->x86_vendor_id[0] = '\0'; /* Unset */
819 c->x86_model_id[0] = '\0'; /* Unset */
820 c->x86_clflush_size = 64;
821 c->x86_cache_alignment = c->x86_clflush_size;
822 c->x86_max_cores = 1;
823 c->extended_cpuid_level = 0;
824 memset(&c->x86_capability, 0, sizeof c->x86_capability);
826 /* Get vendor name */
827 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
828 (unsigned int *)&c->x86_vendor_id[0],
829 (unsigned int *)&c->x86_vendor_id[8],
830 (unsigned int *)&c->x86_vendor_id[4]);
834 /* Initialize the standard set of capabilities */
835 /* Note that the vendor-specific code below might override */
837 /* Intel-defined flags: level 0x00000001 */
838 if (c->cpuid_level >= 0x00000001) {
840 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
841 &c->x86_capability[0]);
842 c->x86 = (tfms >> 8) & 0xf;
843 c->x86_model = (tfms >> 4) & 0xf;
844 c->x86_mask = tfms & 0xf;
846 c->x86 += (tfms >> 20) & 0xff;
848 c->x86_model += ((tfms >> 16) & 0xF) << 4;
849 if (c->x86_capability[0] & (1<<19))
850 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
852 /* Have CPUID level 0 only - unheard of */
857 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
862 * This does the hard work of actually picking apart the CPU stuff...
864 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
869 early_identify_cpu(c);
871 /* AMD-defined flags: level 0x80000001 */
872 xlvl = cpuid_eax(0x80000000);
873 c->extended_cpuid_level = xlvl;
874 if ((xlvl & 0xffff0000) == 0x80000000) {
875 if (xlvl >= 0x80000001) {
876 c->x86_capability[1] = cpuid_edx(0x80000001);
877 c->x86_capability[6] = cpuid_ecx(0x80000001);
879 if (xlvl >= 0x80000004)
880 get_model_name(c); /* Default name */
883 /* Transmeta-defined flags: level 0x80860001 */
884 xlvl = cpuid_eax(0x80860000);
885 if ((xlvl & 0xffff0000) == 0x80860000) {
886 /* Don't set x86_cpuid_level here for now to not confuse. */
887 if (xlvl >= 0x80860001)
888 c->x86_capability[2] = cpuid_edx(0x80860001);
891 init_scattered_cpuid_features(c);
893 c->apicid = phys_pkg_id(0);
896 * Vendor-specific initialization. In this section we
897 * canonicalize the feature flags, meaning if there are
898 * features a certain CPU supports which CPUID doesn't
899 * tell us, CPUID claiming incorrect flags, or other bugs,
900 * we handle them here.
902 * At the end of this section, c->x86_capability better
903 * indicate the features this CPU genuinely supports!
905 switch (c->x86_vendor) {
910 case X86_VENDOR_INTEL:
914 case X86_VENDOR_UNKNOWN:
916 display_cacheinfo(c);
920 select_idle_routine(c);
924 * On SMP, boot_cpu_data holds the common feature set between
925 * all CPUs; so make sure that we indicate which features are
926 * common between the CPUs. The first time this routine gets
927 * executed, c == &boot_cpu_data.
929 if (c != &boot_cpu_data) {
930 /* AND the already accumulated flags with these */
931 for (i = 0 ; i < NCAPINTS ; i++)
932 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
935 #ifdef CONFIG_X86_MCE
938 if (c != &boot_cpu_data)
941 numa_add_cpu(smp_processor_id());
946 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
948 if (c->x86_model_id[0])
949 printk("%s", c->x86_model_id);
951 if (c->x86_mask || c->cpuid_level >= 0)
952 printk(" stepping %02x\n", c->x86_mask);
958 * Get CPU information for use by the procfs.
961 static int show_cpuinfo(struct seq_file *m, void *v)
963 struct cpuinfo_x86 *c = v;
966 * These flag bits must match the definitions in <asm/cpufeature.h>.
967 * NULL means this bit is undefined or reserved; either way it doesn't
968 * have meaning as far as Linux is concerned. Note that it's important
969 * to realize there is a difference between this table and CPUID -- if
970 * applications want to get the raw CPUID data, they should access
971 * /dev/cpu/<cpu_nr>/cpuid instead.
973 static char *x86_cap_flags[] = {
975 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
976 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
977 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
978 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
981 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
982 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
983 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
984 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
987 /* Transmeta-defined */
988 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
993 /* Other (Linux-defined) */
994 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
995 NULL, NULL, NULL, NULL,
996 "constant_tsc", "up", NULL, "arch_perfmon",
997 "pebs", "bts", NULL, "sync_rdtsc",
998 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1001 /* Intel-defined (#2) */
1002 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1003 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1004 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
1005 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1007 /* VIA/Cyrix/Centaur-defined */
1008 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1009 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1010 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1011 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1013 /* AMD-defined (#2) */
1014 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
1015 "altmovcr8", "abm", "sse4a",
1016 "misalignsse", "3dnowprefetch",
1017 "osvw", "ibs", NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1019 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1021 /* Auxiliary (Linux-defined) */
1022 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1024 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1027 static char *x86_power_flags[] = {
1028 "ts", /* temperature sensor */
1029 "fid", /* frequency id control */
1030 "vid", /* voltage id control */
1031 "ttp", /* thermal trip */
1036 "", /* tsc invariant mapped to constant_tsc */
1042 if (!cpu_online(c-cpu_data))
1046 seq_printf(m,"processor\t: %u\n"
1048 "cpu family\t: %d\n"
1050 "model name\t: %s\n",
1051 (unsigned)(c-cpu_data),
1052 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1055 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1057 if (c->x86_mask || c->cpuid_level >= 0)
1058 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1060 seq_printf(m, "stepping\t: unknown\n");
1062 if (cpu_has(c,X86_FEATURE_TSC)) {
1063 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1066 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1067 freq / 1000, (freq % 1000));
1071 if (c->x86_cache_size >= 0)
1072 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1075 if (smp_num_siblings * c->x86_max_cores > 1) {
1076 int cpu = c - cpu_data;
1077 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1078 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
1079 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1080 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1086 "fpu_exception\t: yes\n"
1087 "cpuid level\t: %d\n"
1094 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1095 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1096 seq_printf(m, " %s", x86_cap_flags[i]);
1099 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1100 c->loops_per_jiffy/(500000/HZ),
1101 (c->loops_per_jiffy/(5000/HZ)) % 100);
1103 if (c->x86_tlbsize > 0)
1104 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1105 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1106 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1108 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1109 c->x86_phys_bits, c->x86_virt_bits);
1111 seq_printf(m, "power management:");
1114 for (i = 0; i < 32; i++)
1115 if (c->x86_power & (1 << i)) {
1116 if (i < ARRAY_SIZE(x86_power_flags) &&
1118 seq_printf(m, "%s%s",
1119 x86_power_flags[i][0]?" ":"",
1120 x86_power_flags[i]);
1122 seq_printf(m, " [%d]", i);
1126 seq_printf(m, "\n\n");
1131 static void *c_start(struct seq_file *m, loff_t *pos)
1133 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1136 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1139 return c_start(m, pos);
1142 static void c_stop(struct seq_file *m, void *v)
1146 struct seq_operations cpuinfo_op = {
1150 .show = show_cpuinfo,