2 * This file contains work-arounds for x86 and x86_64 platform bugs.
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
16 /* BIOS may enable hardware IRQ balancing for
17 * E7520/E7320/E7525(revision ID 0x9 and below)
19 * Disable SW irqbalance/affinity on those platforms.
21 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
25 /* enable access to config space*/
26 pci_read_config_byte(dev, 0xf4, &config);
27 pci_write_config_byte(dev, 0xf4, config|0x2);
29 /* read xTPR register */
30 raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
32 if (!(word & (1 << 13))) {
33 printk(KERN_INFO "Intel E7520/7320/7525 detected. "
34 "Disabling irq balancing and affinity\n");
35 #ifdef CONFIG_IRQBALANCE
36 irqbalance_disable("");
44 /* put back the original value for config space*/
46 pci_write_config_byte(dev, 0xf4, config);
48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
49 quirk_intel_irqbalance);
50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
51 quirk_intel_irqbalance);
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
53 quirk_intel_irqbalance);
56 #if defined(CONFIG_HPET_TIMER)
57 unsigned long force_hpet_address;
60 NONE_FORCE_HPET_RESUME,
61 OLD_ICH_FORCE_HPET_RESUME,
62 ICH_FORCE_HPET_RESUME,
63 VT8237_FORCE_HPET_RESUME
64 } force_hpet_resume_type;
66 static void __iomem *rcba_base;
68 static void ich_force_hpet_resume(void)
72 if (!force_hpet_address)
75 if (rcba_base == NULL)
78 /* read the Function Disable register, dword mode only */
79 val = readl(rcba_base + 0x3404);
81 /* HPET disabled in HPTC. Trying to enable */
82 writel(val | 0x80, rcba_base + 0x3404);
85 val = readl(rcba_base + 0x3404);
89 printk(KERN_DEBUG "Force enabled HPET at resume\n");
94 static void ich_force_enable_hpet(struct pci_dev *dev)
97 u32 uninitialized_var(rcba);
100 if (hpet_address || force_hpet_address)
103 pci_read_config_dword(dev, 0xF0, &rcba);
106 printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
110 /* use bits 31:14, 16 kB aligned */
111 rcba_base = ioremap_nocache(rcba, 0x4000);
112 if (rcba_base == NULL) {
113 printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
117 /* read the Function Disable register, dword mode only */
118 val = readl(rcba_base + 0x3404);
121 /* HPET is enabled in HPTC. Just not reported by BIOS */
123 force_hpet_address = 0xFED00000 | (val << 12);
124 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
130 /* HPET disabled in HPTC. Trying to enable */
131 writel(val | 0x80, rcba_base + 0x3404);
133 val = readl(rcba_base + 0x3404);
138 force_hpet_address = 0xFED00000 | (val << 12);
142 force_hpet_address = 0;
144 printk(KERN_DEBUG "Failed to force enable HPET\n");
146 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
147 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
153 ich_force_enable_hpet);
154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
155 ich_force_enable_hpet);
156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
157 ich_force_enable_hpet);
158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
159 ich_force_enable_hpet);
160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
161 ich_force_enable_hpet);
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
163 ich_force_enable_hpet);
166 static struct pci_dev *cached_dev;
168 static void old_ich_force_hpet_resume(void)
171 u32 uninitialized_var(gen_cntl);
173 if (!force_hpet_address || !cached_dev)
176 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
177 gen_cntl &= (~(0x7 << 15));
178 gen_cntl |= (0x4 << 15);
180 pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
181 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
182 val = gen_cntl >> 15;
185 printk(KERN_DEBUG "Force enabled HPET at resume\n");
190 static void old_ich_force_enable_hpet(struct pci_dev *dev)
193 u32 uninitialized_var(gen_cntl);
195 if (hpet_address || force_hpet_address)
198 pci_read_config_dword(dev, 0xD0, &gen_cntl);
200 * Bit 17 is HPET enable bit.
201 * Bit 16:15 control the HPET base address.
203 val = gen_cntl >> 15;
207 force_hpet_address = 0xFED00000 | (val << 12);
208 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
214 * HPET is disabled. Trying enabling at FED00000 and check
217 gen_cntl &= (~(0x7 << 15));
218 gen_cntl |= (0x4 << 15);
219 pci_write_config_dword(dev, 0xD0, gen_cntl);
221 pci_read_config_dword(dev, 0xD0, &gen_cntl);
223 val = gen_cntl >> 15;
226 /* HPET is enabled in HPTC. Just not reported by BIOS */
228 force_hpet_address = 0xFED00000 | (val << 12);
229 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
232 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
236 printk(KERN_DEBUG "Failed to force enable HPET\n");
239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
240 old_ich_force_enable_hpet);
241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
242 old_ich_force_enable_hpet);
245 static void vt8237_force_hpet_resume(void)
249 if (!force_hpet_address || !cached_dev)
252 val = 0xfed00000 | 0x80;
253 pci_write_config_dword(cached_dev, 0x68, val);
255 pci_read_config_dword(cached_dev, 0x68, &val);
257 printk(KERN_DEBUG "Force enabled HPET at resume\n");
262 static void vt8237_force_enable_hpet(struct pci_dev *dev)
264 u32 uninitialized_var(val);
266 if (!hpet_force_user || hpet_address || force_hpet_address)
269 pci_read_config_dword(dev, 0x68, &val);
271 * Bit 7 is HPET enable bit.
272 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
275 force_hpet_address = (val & ~0x3ff);
276 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
282 * HPET is disabled. Trying enabling at FED00000 and check
285 val = 0xfed00000 | 0x80;
286 pci_write_config_dword(dev, 0x68, val);
288 pci_read_config_dword(dev, 0x68, &val);
290 force_hpet_address = (val & ~0x3ff);
291 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
294 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
298 printk(KERN_DEBUG "Failed to force enable HPET\n");
301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
302 vt8237_force_enable_hpet);
303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
304 vt8237_force_enable_hpet);
307 void force_hpet_resume(void)
309 switch (force_hpet_resume_type) {
310 case ICH_FORCE_HPET_RESUME:
311 return ich_force_hpet_resume();
313 case OLD_ICH_FORCE_HPET_RESUME:
314 return old_ich_force_hpet_resume();
316 case VT8237_FORCE_HPET_RESUME:
317 return vt8237_force_hpet_resume();