err.no Git - linux-2.6/blob - arch/x86/kernel/quirks.c

   1 /*
   2  * This file contains work-arounds for x86 and x86_64 platform bugs.
   3  */
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6
   7 #include <asm/hpet.h>
   8
   9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
  10
  11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
  12 {
  13         u8 config, rev;
  14         u16 word;
  15
  16         /* BIOS may enable hardware IRQ balancing for
  17          * E7520/E7320/E7525(revision ID 0x9 and below)
  18          * based platforms.
  19          * Disable SW irqbalance/affinity on those platforms.
  20          */
  21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  22         if (rev > 0x9)
  23                 return;
  24
  25         /* enable access to config space*/
  26         pci_read_config_byte(dev, 0xf4, &config);
  27         pci_write_config_byte(dev, 0xf4, config|0x2);
  28
  29         /*
  30          * read xTPR register.  We may not have a pci_dev for device 8
  31          * because it might be hidden until the above write.
  32          */
  33         pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
  34
  35         if (!(word & (1 << 13))) {
  36                 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
  37                         "disabling irq balancing and affinity\n");
  38 #ifdef CONFIG_IRQBALANCE
  39                 irqbalance_disable("");
  40 #endif
  41                 noirqdebug_setup("");
  42 #ifdef CONFIG_PROC_FS
  43                 no_irq_affinity = 1;
  44 #endif
  45         }
  46
  47         /* put back the original value for config space*/
  48         if (!(config & 0x2))
  49                 pci_write_config_byte(dev, 0xf4, config);
  50 }
  51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  52                         quirk_intel_irqbalance);
  53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  54                         quirk_intel_irqbalance);
  55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  56                         quirk_intel_irqbalance);
  57 #endif
  58
  59 #if defined(CONFIG_HPET_TIMER)
  60 unsigned long force_hpet_address;
  61
  62 static enum {
  63         NONE_FORCE_HPET_RESUME,
  64         OLD_ICH_FORCE_HPET_RESUME,
  65         ICH_FORCE_HPET_RESUME,
  66         VT8237_FORCE_HPET_RESUME,
  67         NVIDIA_FORCE_HPET_RESUME,
  68         ATI_FORCE_HPET_RESUME,
  69 } force_hpet_resume_type;
  70
  71 static void __iomem *rcba_base;
  72
  73 static void ich_force_hpet_resume(void)
  74 {
  75         u32 val;
  76
  77         if (!force_hpet_address)
  78                 return;
  79
  80         if (rcba_base == NULL)
  81                 BUG();
  82
  83         /* read the Function Disable register, dword mode only */
  84         val = readl(rcba_base + 0x3404);
  85         if (!(val & 0x80)) {
  86                 /* HPET disabled in HPTC. Trying to enable */
  87                 writel(val | 0x80, rcba_base + 0x3404);
  88         }
  89
  90         val = readl(rcba_base + 0x3404);
  91         if (!(val & 0x80))
  92                 BUG();
  93         else
  94                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
  95
  96         return;
  97 }
  98
  99 static void ich_force_enable_hpet(struct pci_dev *dev)
 100 {
 101         u32 val;
 102         u32 uninitialized_var(rcba);
 103         int err = 0;
 104
 105         if (hpet_address || force_hpet_address)
 106                 return;
 107
 108         pci_read_config_dword(dev, 0xF0, &rcba);
 109         rcba &= 0xFFFFC000;
 110         if (rcba == 0) {
 111                 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
 112                         "cannot force enable HPET\n");
 113                 return;
 114         }
 115
 116         /* use bits 31:14, 16 kB aligned */
 117         rcba_base = ioremap_nocache(rcba, 0x4000);
 118         if (rcba_base == NULL) {
 119                 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
 120                         "cannot force enable HPET\n");
 121                 return;
 122         }
 123
 124         /* read the Function Disable register, dword mode only */
 125         val = readl(rcba_base + 0x3404);
 126
 127         if (val & 0x80) {
 128                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 129                 val = val & 0x3;
 130                 force_hpet_address = 0xFED00000 | (val << 12);
 131                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 132                         "0x%lx\n", force_hpet_address);
 133                 iounmap(rcba_base);
 134                 return;
 135         }
 136
 137         /* HPET disabled in HPTC. Trying to enable */
 138         writel(val | 0x80, rcba_base + 0x3404);
 139
 140         val = readl(rcba_base + 0x3404);
 141         if (!(val & 0x80)) {
 142                 err = 1;
 143         } else {
 144                 val = val & 0x3;
 145                 force_hpet_address = 0xFED00000 | (val << 12);
 146         }
 147
 148         if (err) {
 149                 force_hpet_address = 0;
 150                 iounmap(rcba_base);
 151                 dev_printk(KERN_DEBUG, &dev->dev,
 152                         "Failed to force enable HPET\n");
 153         } else {
 154                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
 155                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 156                         "0x%lx\n", force_hpet_address);
 157         }
 158 }
 159
 160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 161                          ich_force_enable_hpet);
 162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
 163                          ich_force_enable_hpet);
 164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
 165                          ich_force_enable_hpet);
 166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
 167                          ich_force_enable_hpet);
 168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
 169                          ich_force_enable_hpet);
 170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
 171                          ich_force_enable_hpet);
 172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
 173                          ich_force_enable_hpet);
 174
 175
 176 static struct pci_dev *cached_dev;
 177
 178 static void hpet_print_force_info(void)
 179 {
 180         printk(KERN_INFO "HPET not enabled in BIOS. "
 181                "You might try hpet=force boot option\n");
 182 }
 183
 184 static void old_ich_force_hpet_resume(void)
 185 {
 186         u32 val;
 187         u32 uninitialized_var(gen_cntl);
 188
 189         if (!force_hpet_address || !cached_dev)
 190                 return;
 191
 192         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 193         gen_cntl &= (~(0x7 << 15));
 194         gen_cntl |= (0x4 << 15);
 195
 196         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
 197         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 198         val = gen_cntl >> 15;
 199         val &= 0x7;
 200         if (val == 0x4)
 201                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 202         else
 203                 BUG();
 204 }
 205
 206 static void old_ich_force_enable_hpet(struct pci_dev *dev)
 207 {
 208         u32 val;
 209         u32 uninitialized_var(gen_cntl);
 210
 211         if (hpet_address || force_hpet_address)
 212                 return;
 213
 214         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 215         /*
 216          * Bit 17 is HPET enable bit.
 217          * Bit 16:15 control the HPET base address.
 218          */
 219         val = gen_cntl >> 15;
 220         val &= 0x7;
 221         if (val & 0x4) {
 222                 val &= 0x3;
 223                 force_hpet_address = 0xFED00000 | (val << 12);
 224                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 225                         force_hpet_address);
 226                 return;
 227         }
 228
 229         /*
 230          * HPET is disabled. Trying enabling at FED00000 and check
 231          * whether it sticks
 232          */
 233         gen_cntl &= (~(0x7 << 15));
 234         gen_cntl |= (0x4 << 15);
 235         pci_write_config_dword(dev, 0xD0, gen_cntl);
 236
 237         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 238
 239         val = gen_cntl >> 15;
 240         val &= 0x7;
 241         if (val & 0x4) {
 242                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 243                 val &= 0x3;
 244                 force_hpet_address = 0xFED00000 | (val << 12);
 245                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 246                         "0x%lx\n", force_hpet_address);
 247                 cached_dev = dev;
 248                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
 249                 return;
 250         }
 251
 252         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 253 }
 254
 255 /*
 256  * Undocumented chipset features. Make sure that the user enforced
 257  * this.
 258  */
 259 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
 260 {
 261         if (hpet_force_user)
 262                 old_ich_force_enable_hpet(dev);
 263         else
 264                 hpet_print_force_info();
 265 }
 266
 267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
 268                          old_ich_force_enable_hpet_user);
 269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
 270                          old_ich_force_enable_hpet_user);
 271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 272                          old_ich_force_enable_hpet_user);
 273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
 274                          old_ich_force_enable_hpet_user);
 275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 276                          old_ich_force_enable_hpet);
 277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
 278                          old_ich_force_enable_hpet);
 279
 280
 281 static void vt8237_force_hpet_resume(void)
 282 {
 283         u32 val;
 284
 285         if (!force_hpet_address || !cached_dev)
 286                 return;
 287
 288         val = 0xfed00000 | 0x80;
 289         pci_write_config_dword(cached_dev, 0x68, val);
 290
 291         pci_read_config_dword(cached_dev, 0x68, &val);
 292         if (val & 0x80)
 293                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 294         else
 295                 BUG();
 296 }
 297
 298 static void vt8237_force_enable_hpet(struct pci_dev *dev)
 299 {
 300         u32 uninitialized_var(val);
 301
 302         if (hpet_address || force_hpet_address)
 303                 return;
 304
 305         if (!hpet_force_user) {
 306                 hpet_print_force_info();
 307                 return;
 308         }
 309
 310         pci_read_config_dword(dev, 0x68, &val);
 311         /*
 312          * Bit 7 is HPET enable bit.
 313          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
 314          */
 315         if (val & 0x80) {
 316                 force_hpet_address = (val & ~0x3ff);
 317                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 318                         force_hpet_address);
 319                 return;
 320         }
 321
 322         /*
 323          * HPET is disabled. Trying enabling at FED00000 and check
 324          * whether it sticks
 325          */
 326         val = 0xfed00000 | 0x80;
 327         pci_write_config_dword(dev, 0x68, val);
 328
 329         pci_read_config_dword(dev, 0x68, &val);
 330         if (val & 0x80) {
 331                 force_hpet_address = (val & ~0x3ff);
 332                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 333                         "0x%lx\n", force_hpet_address);
 334                 cached_dev = dev;
 335                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
 336                 return;
 337         }
 338
 339         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 340 }
 341
 342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
 343                          vt8237_force_enable_hpet);
 344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
 345                          vt8237_force_enable_hpet);
 346
 347 static void ati_force_hpet_resume(void)
 348 {
 349         pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
 350         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 351 }
 352
 353 static void ati_force_enable_hpet(struct pci_dev *dev)
 354 {
 355         u32 uninitialized_var(val);
 356
 357         if (hpet_address || force_hpet_address)
 358                 return;
 359
 360         if (!hpet_force_user) {
 361                 hpet_print_force_info();
 362                 return;
 363         }
 364
 365         pci_write_config_dword(dev, 0x14, 0xfed00000);
 366         pci_read_config_dword(dev, 0x14, &val);
 367         force_hpet_address = val;
 368         force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
 369         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 370                    force_hpet_address);
 371         cached_dev = dev;
 372         return;
 373 }
 374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
 375                          ati_force_enable_hpet);
 376
 377 /*
 378  * Undocumented chipset feature taken from LinuxBIOS.
 379  */
 380 static void nvidia_force_hpet_resume(void)
 381 {
 382         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
 383         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 384 }
 385
 386 static void nvidia_force_enable_hpet(struct pci_dev *dev)
 387 {
 388         u32 uninitialized_var(val);
 389
 390         if (hpet_address || force_hpet_address)
 391                 return;
 392
 393         if (!hpet_force_user) {
 394                 hpet_print_force_info();
 395                 return;
 396         }
 397
 398         pci_write_config_dword(dev, 0x44, 0xfed00001);
 399         pci_read_config_dword(dev, 0x44, &val);
 400         force_hpet_address = val & 0xfffffffe;
 401         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
 402         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 403                 force_hpet_address);
 404         cached_dev = dev;
 405         return;
 406 }
 407
 408 /* ISA Bridges */
 409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
 410                         nvidia_force_enable_hpet);
 411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
 412                         nvidia_force_enable_hpet);
 413
 414 /* LPC bridges */
 415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
 416                         nvidia_force_enable_hpet);
 417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
 418                         nvidia_force_enable_hpet);
 419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
 420                         nvidia_force_enable_hpet);
 421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
 422                         nvidia_force_enable_hpet);
 423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
 424                         nvidia_force_enable_hpet);
 425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
 426                         nvidia_force_enable_hpet);
 427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
 428                         nvidia_force_enable_hpet);
 429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
 430                         nvidia_force_enable_hpet);
 431 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
 432                         nvidia_force_enable_hpet);
 433
 434 void force_hpet_resume(void)
 435 {
 436         switch (force_hpet_resume_type) {
 437         case ICH_FORCE_HPET_RESUME:
 438                 ich_force_hpet_resume();
 439                 return;
 440         case OLD_ICH_FORCE_HPET_RESUME:
 441                 old_ich_force_hpet_resume();
 442                 return;
 443         case VT8237_FORCE_HPET_RESUME:
 444                 vt8237_force_hpet_resume();
 445                 return;
 446         case NVIDIA_FORCE_HPET_RESUME:
 447                 nvidia_force_hpet_resume();
 448                 return;
 449         case ATI_FORCE_HPET_RESUME:
 450                 ati_force_hpet_resume();
 451                 return;
 452         default:
 453                 break;
 454         }
 455 }
 456
 457 #endif