err.no Git - linux-2.6/blob - arch/x86/kernel/quirks.c

   1 /*
   2  * This file contains work-arounds for x86 and x86_64 platform bugs.
   3  */
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6
   7 #include <asm/hpet.h>
   8
   9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
  10
  11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
  12 {
  13         u8 config, rev;
  14         u32 word;
  15
  16         /* BIOS may enable hardware IRQ balancing for
  17          * E7520/E7320/E7525(revision ID 0x9 and below)
  18          * based platforms.
  19          * Disable SW irqbalance/affinity on those platforms.
  20          */
  21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  22         if (rev > 0x9)
  23                 return;
  24
  25         /* enable access to config space*/
  26         pci_read_config_byte(dev, 0xf4, &config);
  27         pci_write_config_byte(dev, 0xf4, config|0x2);
  28
  29         /* read xTPR register */
  30         raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
  31
  32         if (!(word & (1 << 13))) {
  33                 printk(KERN_INFO "Intel E7520/7320/7525 detected. "
  34                         "Disabling irq balancing and affinity\n");
  35 #ifdef CONFIG_IRQBALANCE
  36                 irqbalance_disable("");
  37 #endif
  38                 noirqdebug_setup("");
  39 #ifdef CONFIG_PROC_FS
  40                 no_irq_affinity = 1;
  41 #endif
  42         }
  43
  44         /* put back the original value for config space*/
  45         if (!(config & 0x2))
  46                 pci_write_config_byte(dev, 0xf4, config);
  47 }
  48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  49                         quirk_intel_irqbalance);
  50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  51                         quirk_intel_irqbalance);
  52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  53                         quirk_intel_irqbalance);
  54 #endif
  55
  56 #if defined(CONFIG_HPET_TIMER)
  57 unsigned long force_hpet_address;
  58
  59 static enum {
  60         NONE_FORCE_HPET_RESUME,
  61         OLD_ICH_FORCE_HPET_RESUME,
  62         ICH_FORCE_HPET_RESUME
  63 } force_hpet_resume_type;
  64
  65 static void __iomem *rcba_base;
  66
  67 static void ich_force_hpet_resume(void)
  68 {
  69         u32 val;
  70
  71         if (!force_hpet_address)
  72                 return;
  73
  74         if (rcba_base == NULL)
  75                 BUG();
  76
  77         /* read the Function Disable register, dword mode only */
  78         val = readl(rcba_base + 0x3404);
  79         if (!(val & 0x80)) {
  80                 /* HPET disabled in HPTC. Trying to enable */
  81                 writel(val | 0x80, rcba_base + 0x3404);
  82         }
  83
  84         val = readl(rcba_base + 0x3404);
  85         if (!(val & 0x80))
  86                 BUG();
  87         else
  88                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
  89
  90         return;
  91 }
  92
  93 static void ich_force_enable_hpet(struct pci_dev *dev)
  94 {
  95         u32 val;
  96         u32 uninitialized_var(rcba);
  97         int err = 0;
  98
  99         if (hpet_address || force_hpet_address)
 100                 return;
 101
 102         pci_read_config_dword(dev, 0xF0, &rcba);
 103         rcba &= 0xFFFFC000;
 104         if (rcba == 0) {
 105                 printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
 106                 return;
 107         }
 108
 109         /* use bits 31:14, 16 kB aligned */
 110         rcba_base = ioremap_nocache(rcba, 0x4000);
 111         if (rcba_base == NULL) {
 112                 printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
 113                 return;
 114         }
 115
 116         /* read the Function Disable register, dword mode only */
 117         val = readl(rcba_base + 0x3404);
 118
 119         if (val & 0x80) {
 120                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 121                 val = val & 0x3;
 122                 force_hpet_address = 0xFED00000 | (val << 12);
 123                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
 124                                force_hpet_address);
 125                 iounmap(rcba_base);
 126                 return;
 127         }
 128
 129         /* HPET disabled in HPTC. Trying to enable */
 130         writel(val | 0x80, rcba_base + 0x3404);
 131
 132         val = readl(rcba_base + 0x3404);
 133         if (!(val & 0x80)) {
 134                 err = 1;
 135         } else {
 136                 val = val & 0x3;
 137                 force_hpet_address = 0xFED00000 | (val << 12);
 138         }
 139
 140         if (err) {
 141                 force_hpet_address = 0;
 142                 iounmap(rcba_base);
 143                 printk(KERN_DEBUG "Failed to force enable HPET\n");
 144         } else {
 145                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
 146                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
 147                                force_hpet_address);
 148         }
 149 }
 150
 151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 152                          ich_force_enable_hpet);
 153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
 154                          ich_force_enable_hpet);
 155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
 156                          ich_force_enable_hpet);
 157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
 158                          ich_force_enable_hpet);
 159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
 160                          ich_force_enable_hpet);
 161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
 162                          ich_force_enable_hpet);
 163
 164
 165 static struct pci_dev *cached_dev;
 166
 167 static void old_ich_force_hpet_resume(void)
 168 {
 169         u32 val;
 170         u32 uninitialized_var(gen_cntl);
 171
 172         if (!force_hpet_address || !cached_dev)
 173                 return;
 174
 175         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 176         gen_cntl &= (~(0x7 << 15));
 177         gen_cntl |= (0x4 << 15);
 178
 179         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
 180         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 181         val = gen_cntl >> 15;
 182         val &= 0x7;
 183         if (val == 0x4)
 184                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 185         else
 186                 BUG();
 187 }
 188
 189 static void old_ich_force_enable_hpet(struct pci_dev *dev)
 190 {
 191         u32 val;
 192         u32 uninitialized_var(gen_cntl);
 193
 194         if (hpet_address || force_hpet_address)
 195                 return;
 196
 197         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 198         /*
 199          * Bit 17 is HPET enable bit.
 200          * Bit 16:15 control the HPET base address.
 201          */
 202         val = gen_cntl >> 15;
 203         val &= 0x7;
 204         if (val & 0x4) {
 205                 val &= 0x3;
 206                 force_hpet_address = 0xFED00000 | (val << 12);
 207                 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
 208                                force_hpet_address);
 209                 return;
 210         }
 211
 212         /*
 213          * HPET is disabled. Trying enabling at FED00000 and check
 214          * whether it sticks
 215          */
 216         gen_cntl &= (~(0x7 << 15));
 217         gen_cntl |= (0x4 << 15);
 218         pci_write_config_dword(dev, 0xD0, gen_cntl);
 219
 220         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 221
 222         val = gen_cntl >> 15;
 223         val &= 0x7;
 224         if (val & 0x4) {
 225                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 226                 val &= 0x3;
 227                 force_hpet_address = 0xFED00000 | (val << 12);
 228                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
 229                                force_hpet_address);
 230                 cached_dev = dev;
 231                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
 232                 return;
 233         }
 234
 235         printk(KERN_DEBUG "Failed to force enable HPET\n");
 236 }
 237
 238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 239                          old_ich_force_enable_hpet);
 240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
 241                          old_ich_force_enable_hpet);
 242
 243 void force_hpet_resume(void)
 244 {
 245         switch (force_hpet_resume_type) {
 246             case ICH_FORCE_HPET_RESUME:
 247                 return ich_force_hpet_resume();
 248
 249             case OLD_ICH_FORCE_HPET_RESUME:
 250                 return old_ich_force_hpet_resume();
 251
 252             default:
 253                 break;
 254         }
 255 }
 256
 257 #endif