2 * This file contains work-arounds for x86 and x86_64 platform bugs.
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
16 /* BIOS may enable hardware IRQ balancing for
17 * E7520/E7320/E7525(revision ID 0x9 and below)
19 * Disable SW irqbalance/affinity on those platforms.
21 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
25 /* enable access to config space*/
26 pci_read_config_byte(dev, 0xf4, &config);
27 pci_write_config_byte(dev, 0xf4, config|0x2);
29 /* read xTPR register */
30 raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
32 if (!(word & (1 << 13))) {
33 printk(KERN_INFO "Intel E7520/7320/7525 detected. "
34 "Disabling irq balancing and affinity\n");
35 #ifdef CONFIG_IRQBALANCE
36 irqbalance_disable("");
44 /* put back the original value for config space*/
46 pci_write_config_byte(dev, 0xf4, config);
48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_intel_irqbalance);
49 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_intel_irqbalance);
50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_intel_irqbalance);
53 #if defined(CONFIG_HPET_TIMER)
54 unsigned long force_hpet_address;
57 NONE_FORCE_HPET_RESUME,
58 OLD_ICH_FORCE_HPET_RESUME,
60 } force_hpet_resume_type;
62 static void __iomem *rcba_base;
64 static void ich_force_hpet_resume(void)
68 if (!force_hpet_address)
71 if (rcba_base == NULL)
74 /* read the Function Disable register, dword mode only */
75 val = readl(rcba_base + 0x3404);
77 /* HPET disabled in HPTC. Trying to enable */
78 writel(val | 0x80, rcba_base + 0x3404);
81 val = readl(rcba_base + 0x3404);
85 printk(KERN_DEBUG "Force enabled HPET at resume\n");
90 static void ich_force_enable_hpet(struct pci_dev *dev)
93 u32 uninitialized_var(rcba);
96 if (hpet_address || force_hpet_address)
99 pci_read_config_dword(dev, 0xF0, &rcba);
102 printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
106 /* use bits 31:14, 16 kB aligned */
107 rcba_base = ioremap_nocache(rcba, 0x4000);
108 if (rcba_base == NULL) {
109 printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
113 /* read the Function Disable register, dword mode only */
114 val = readl(rcba_base + 0x3404);
117 /* HPET is enabled in HPTC. Just not reported by BIOS */
119 force_hpet_address = 0xFED00000 | (val << 12);
120 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
126 /* HPET disabled in HPTC. Trying to enable */
127 writel(val | 0x80, rcba_base + 0x3404);
129 val = readl(rcba_base + 0x3404);
134 force_hpet_address = 0xFED00000 | (val << 12);
138 force_hpet_address = 0;
140 printk(KERN_DEBUG "Failed to force enable HPET\n");
142 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
143 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
149 ich_force_enable_hpet);
150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
151 ich_force_enable_hpet);
152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
153 ich_force_enable_hpet);
154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
155 ich_force_enable_hpet);
156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
157 ich_force_enable_hpet);
160 static struct pci_dev *cached_dev;
162 static void old_ich_force_hpet_resume(void)
165 u32 uninitialized_var(gen_cntl);
167 if (!force_hpet_address || !cached_dev)
170 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
171 gen_cntl &= (~(0x7 << 15));
172 gen_cntl |= (0x4 << 15);
174 pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
175 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
176 val = gen_cntl >> 15;
179 printk(KERN_DEBUG "Force enabled HPET at resume\n");
184 static void old_ich_force_enable_hpet(struct pci_dev *dev)
187 u32 uninitialized_var(gen_cntl);
189 if (hpet_address || force_hpet_address)
192 pci_read_config_dword(dev, 0xD0, &gen_cntl);
194 * Bit 17 is HPET enable bit.
195 * Bit 16:15 control the HPET base address.
197 val = gen_cntl >> 15;
201 force_hpet_address = 0xFED00000 | (val << 12);
202 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
208 * HPET is disabled. Trying enabling at FED00000 and check
211 gen_cntl &= (~(0x7 << 15));
212 gen_cntl |= (0x4 << 15);
213 pci_write_config_dword(dev, 0xD0, gen_cntl);
215 pci_read_config_dword(dev, 0xD0, &gen_cntl);
217 val = gen_cntl >> 15;
220 /* HPET is enabled in HPTC. Just not reported by BIOS */
222 force_hpet_address = 0xFED00000 | (val << 12);
223 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
226 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
230 printk(KERN_DEBUG "Failed to force enable HPET\n");
233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
234 old_ich_force_enable_hpet);
235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
236 old_ich_force_enable_hpet);
238 void force_hpet_resume(void)
240 switch (force_hpet_resume_type) {
241 case ICH_FORCE_HPET_RESUME:
242 return ich_force_hpet_resume();
244 case OLD_ICH_FORCE_HPET_RESUME:
245 return old_ich_force_hpet_resume();