err.no Git - linux-2.6/blob - arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <asm/iommu.h>
  40 #include <asm/calgary.h>
  41 #include <asm/tce.h>
  42 #include <asm/pci-direct.h>
  43 #include <asm/system.h>
  44 #include <asm/dma.h>
  45 #include <asm/rio.h>
  46
  47 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  48 int use_calgary __read_mostly = 1;
  49 #else
  50 int use_calgary __read_mostly = 0;
  51 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  52
  53 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  54 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  55
  56 /* register offsets inside the host bridge space */
  57 #define CALGARY_CONFIG_REG      0x0108
  58 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  59 #define PHB_PLSSR_OFFSET        0x0120
  60 #define PHB_CONFIG_RW_OFFSET    0x0160
  61 #define PHB_IOBASE_BAR_LOW      0x0170
  62 #define PHB_IOBASE_BAR_HIGH     0x0180
  63 #define PHB_MEM_1_LOW           0x0190
  64 #define PHB_MEM_1_HIGH          0x01A0
  65 #define PHB_IO_ADDR_SIZE        0x01B0
  66 #define PHB_MEM_1_SIZE          0x01C0
  67 #define PHB_MEM_ST_OFFSET       0x01D0
  68 #define PHB_AER_OFFSET          0x0200
  69 #define PHB_CONFIG_0_HIGH       0x0220
  70 #define PHB_CONFIG_0_LOW        0x0230
  71 #define PHB_CONFIG_0_END        0x0240
  72 #define PHB_MEM_2_LOW           0x02B0
  73 #define PHB_MEM_2_HIGH          0x02C0
  74 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  75 #define PHB_MEM_2_SIZE_LOW      0x02E0
  76 #define PHB_DOSHOLE_OFFSET      0x08E0
  77
  78 /* CalIOC2 specific */
  79 #define PHB_SAVIOR_L2           0x0DB0
  80 #define PHB_PAGE_MIG_CTRL       0x0DA8
  81 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  82 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  83
  84 /* PHB_CONFIG_RW */
  85 #define PHB_TCE_ENABLE          0x20000000
  86 #define PHB_SLOT_DISABLE        0x1C000000
  87 #define PHB_DAC_DISABLE         0x01000000
  88 #define PHB_MEM2_ENABLE         0x00400000
  89 #define PHB_MCSR_ENABLE         0x00100000
  90 /* TAR (Table Address Register) */
  91 #define TAR_SW_BITS             0x0000ffffffff800fUL
  92 #define TAR_VALID               0x0000000000000008UL
  93 /* CSR (Channel/DMA Status Register) */
  94 #define CSR_AGENT_MASK          0xffe0ffff
  95 /* CCR (Calgary Configuration Register) */
  96 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  97 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  98 #define PMR_SOFTSTOP            0x80000000
  99 #define PMR_SOFTSTOPFAULT       0x40000000
 100 #define PMR_HARDSTOP            0x20000000
 101
 102 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 103 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 104 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 105 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 106 #define PHBS_PER_CALGARY        4
 107
 108 /* register offsets in Calgary's internal register space */
 109 static const unsigned long tar_offsets[] = {
 110         0x0580 /* TAR0 */,
 111         0x0588 /* TAR1 */,
 112         0x0590 /* TAR2 */,
 113         0x0598 /* TAR3 */
 114 };
 115
 116 static const unsigned long split_queue_offsets[] = {
 117         0x4870 /* SPLIT QUEUE 0 */,
 118         0x5870 /* SPLIT QUEUE 1 */,
 119         0x6870 /* SPLIT QUEUE 2 */,
 120         0x7870 /* SPLIT QUEUE 3 */
 121 };
 122
 123 static const unsigned long phb_offsets[] = {
 124         0x8000 /* PHB0 */,
 125         0x9000 /* PHB1 */,
 126         0xA000 /* PHB2 */,
 127         0xB000 /* PHB3 */
 128 };
 129
 130 /* PHB debug registers */
 131
 132 static const unsigned long phb_debug_offsets[] = {
 133         0x4000  /* PHB 0 DEBUG */,
 134         0x5000  /* PHB 1 DEBUG */,
 135         0x6000  /* PHB 2 DEBUG */,
 136         0x7000  /* PHB 3 DEBUG */
 137 };
 138
 139 /*
 140  * STUFF register for each debug PHB,
 141  * byte 1 = start bus number, byte 2 = end bus number
 142  */
 143
 144 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 145
 146 #define EMERGENCY_PAGES 32 /* = 128KB */
 147
 148 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 149 static int translate_empty_slots __read_mostly = 0;
 150 static int calgary_detected __read_mostly = 0;
 151
 152 static struct rio_table_hdr     *rio_table_hdr __initdata;
 153 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 154 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 155
 156 struct calgary_bus_info {
 157         void *tce_space;
 158         unsigned char translation_disabled;
 159         signed char phbid;
 160         void __iomem *bbar;
 161 };
 162
 163 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 164 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 165 static void calgary_dump_error_regs(struct iommu_table *tbl);
 166 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 168 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 169
 170 static struct cal_chipset_ops calgary_chip_ops = {
 171         .handle_quirks = calgary_handle_quirks,
 172         .tce_cache_blast = calgary_tce_cache_blast,
 173         .dump_error_regs = calgary_dump_error_regs
 174 };
 175
 176 static struct cal_chipset_ops calioc2_chip_ops = {
 177         .handle_quirks = calioc2_handle_quirks,
 178         .tce_cache_blast = calioc2_tce_cache_blast,
 179         .dump_error_regs = calioc2_dump_error_regs
 180 };
 181
 182 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 183
 184 /* enable this to stress test the chip's TCE cache */
 185 #ifdef CONFIG_IOMMU_DEBUG
 186 int debugging __read_mostly = 1;
 187
 188 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 189         int expected, unsigned long start, unsigned long end)
 190 {
 191         unsigned long idx = start;
 192
 193         BUG_ON(start >= end);
 194
 195         while (idx < end) {
 196                 if (!!test_bit(idx, bitmap) != expected)
 197                         return idx;
 198                 ++idx;
 199         }
 200
 201         /* all bits have the expected value */
 202         return ~0UL;
 203 }
 204 #else /* debugging is disabled */
 205 int debugging __read_mostly = 0;
 206
 207 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 208         int expected, unsigned long start, unsigned long end)
 209 {
 210         return ~0UL;
 211 }
 212
 213 #endif /* CONFIG_IOMMU_DEBUG */
 214
 215 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 216 {
 217         unsigned int npages;
 218
 219         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 220         npages >>= PAGE_SHIFT;
 221
 222         return npages;
 223 }
 224
 225 static inline int translation_enabled(struct iommu_table *tbl)
 226 {
 227         /* only PHBs with translation enabled have an IOMMU table */
 228         return (tbl != NULL);
 229 }
 230
 231 static inline int translate_phb(struct pci_dev* dev)
 232 {
 233         int disabled = bus_info[dev->bus->number].translation_disabled;
 234         return !disabled;
 235 }
 236
 237 static void iommu_range_reserve(struct iommu_table *tbl,
 238         unsigned long start_addr, unsigned int npages)
 239 {
 240         unsigned long index;
 241         unsigned long end;
 242         unsigned long badbit;
 243         unsigned long flags;
 244
 245         index = start_addr >> PAGE_SHIFT;
 246
 247         /* bail out if we're asked to reserve a region we don't cover */
 248         if (index >= tbl->it_size)
 249                 return;
 250
 251         end = index + npages;
 252         if (end > tbl->it_size) /* don't go off the table */
 253                 end = tbl->it_size;
 254
 255         spin_lock_irqsave(&tbl->it_lock, flags);
 256
 257         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 258         if (badbit != ~0UL) {
 259                 if (printk_ratelimit())
 260                         printk(KERN_ERR "Calgary: entry already allocated at "
 261                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 262                                badbit, tbl, start_addr, npages);
 263         }
 264
 265         set_bit_string(tbl->it_map, index, npages);
 266
 267         spin_unlock_irqrestore(&tbl->it_lock, flags);
 268 }
 269
 270 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 271         unsigned int npages)
 272 {
 273         unsigned long flags;
 274         unsigned long offset;
 275
 276         BUG_ON(npages == 0);
 277
 278         spin_lock_irqsave(&tbl->it_lock, flags);
 279
 280         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 281                                        tbl->it_size, npages);
 282         if (offset == ~0UL) {
 283                 tbl->chip_ops->tce_cache_blast(tbl);
 284                 offset = find_next_zero_string(tbl->it_map, 0,
 285                                                tbl->it_size, npages);
 286                 if (offset == ~0UL) {
 287                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 288                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 289                         if (panic_on_overflow)
 290                                 panic("Calgary: fix the allocator.\n");
 291                         else
 292                                 return bad_dma_address;
 293                 }
 294         }
 295
 296         set_bit_string(tbl->it_map, offset, npages);
 297         tbl->it_hint = offset + npages;
 298         BUG_ON(tbl->it_hint > tbl->it_size);
 299
 300         spin_unlock_irqrestore(&tbl->it_lock, flags);
 301
 302         return offset;
 303 }
 304
 305 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 306         unsigned int npages, int direction)
 307 {
 308         unsigned long entry;
 309         dma_addr_t ret = bad_dma_address;
 310
 311         entry = iommu_range_alloc(tbl, npages);
 312
 313         if (unlikely(entry == bad_dma_address))
 314                 goto error;
 315
 316         /* set the return dma address */
 317         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 318
 319         /* put the TCEs in the HW table */
 320         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 321                   direction);
 322
 323         return ret;
 324
 325 error:
 326         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 327                "iommu %p\n", npages, tbl);
 328         return bad_dma_address;
 329 }
 330
 331 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 332         unsigned int npages)
 333 {
 334         unsigned long entry;
 335         unsigned long badbit;
 336         unsigned long badend;
 337         unsigned long flags;
 338
 339         /* were we called with bad_dma_address? */
 340         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 341         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 342                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 343                        "address 0x%Lx\n", dma_addr);
 344                 WARN_ON(1);
 345                 return;
 346         }
 347
 348         entry = dma_addr >> PAGE_SHIFT;
 349
 350         BUG_ON(entry + npages > tbl->it_size);
 351
 352         tce_free(tbl, entry, npages);
 353
 354         spin_lock_irqsave(&tbl->it_lock, flags);
 355
 356         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 357         if (badbit != ~0UL) {
 358                 if (printk_ratelimit())
 359                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 360                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 361                                badbit, tbl, dma_addr, entry, npages);
 362         }
 363
 364         __clear_bit_string(tbl->it_map, entry, npages);
 365
 366         spin_unlock_irqrestore(&tbl->it_lock, flags);
 367 }
 368
 369 static inline struct iommu_table *find_iommu_table(struct device *dev)
 370 {
 371         struct pci_dev *pdev;
 372         struct pci_bus *pbus;
 373         struct iommu_table *tbl;
 374
 375         pdev = to_pci_dev(dev);
 376
 377         pbus = pdev->bus;
 378
 379         /* is the device behind a bridge? Look for the root bus */
 380         while (pbus->parent)
 381                 pbus = pbus->parent;
 382
 383         tbl = pci_iommu(pbus);
 384
 385         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 386
 387         return tbl;
 388 }
 389
 390 static void calgary_unmap_sg(struct device *dev,
 391         struct scatterlist *sglist, int nelems, int direction)
 392 {
 393         struct iommu_table *tbl = find_iommu_table(dev);
 394         struct scatterlist *s;
 395         int i;
 396
 397         if (!translate_enabled(tbl))
 398                 return;
 399
 400         for_each_sg(sglist, s, nelems, i) {
 401                 unsigned int npages;
 402                 dma_addr_t dma = s->dma_address;
 403                 unsigned int dmalen = s->dma_length;
 404
 405                 if (dmalen == 0)
 406                         break;
 407
 408                 npages = num_dma_pages(dma, dmalen);
 409                 iommu_free(tbl, dma, npages);
 410         }
 411 }
 412
 413 static int calgary_nontranslate_map_sg(struct device* dev,
 414         struct scatterlist *sg, int nelems, int direction)
 415 {
 416         struct scatterlist *s;
 417         int i;
 418
 419         for_each_sg(sg, s, nelems, i) {
 420                 BUG_ON(!s->page);
 421                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 422                 s->dma_length = s->length;
 423         }
 424         return nelems;
 425 }
 426
 427 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 428         int nelems, int direction)
 429 {
 430         struct iommu_table *tbl = find_iommu_table(dev);
 431         struct scatterlist *s;
 432         unsigned long vaddr;
 433         unsigned int npages;
 434         unsigned long entry;
 435         int i;
 436
 437         if (!translation_enabled(tbl))
 438                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 439
 440         for_each_sg(sg, s, nelems, i) {
 441                 BUG_ON(!s->page);
 442
 443                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 444                 npages = num_dma_pages(vaddr, s->length);
 445
 446                 entry = iommu_range_alloc(tbl, npages);
 447                 if (entry == bad_dma_address) {
 448                         /* makes sure unmap knows to stop */
 449                         s->dma_length = 0;
 450                         goto error;
 451                 }
 452
 453                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 454
 455                 /* insert into HW table */
 456                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 457                           direction);
 458
 459                 s->dma_length = s->length;
 460         }
 461
 462         return nelems;
 463 error:
 464         calgary_unmap_sg(dev, sg, nelems, direction);
 465         for_each_sg(sg, s, nelems, i) {
 466                 sg->dma_address = bad_dma_address;
 467                 sg->dma_length = 0;
 468         }
 469         return 0;
 470 }
 471
 472 static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 473         size_t size, int direction)
 474 {
 475         dma_addr_t dma_handle = bad_dma_address;
 476         unsigned long uaddr;
 477         unsigned int npages;
 478         struct iommu_table *tbl = find_iommu_table(dev);
 479
 480         uaddr = (unsigned long)vaddr;
 481         npages = num_dma_pages(uaddr, size);
 482
 483         if (translation_enabled(tbl))
 484                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 485         else
 486                 dma_handle = virt_to_bus(vaddr);
 487
 488         return dma_handle;
 489 }
 490
 491 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 492         size_t size, int direction)
 493 {
 494         struct iommu_table *tbl = find_iommu_table(dev);
 495         unsigned int npages;
 496
 497         if (!translation_enabled(tbl))
 498                 return;
 499
 500         npages = num_dma_pages(dma_handle, size);
 501         iommu_free(tbl, dma_handle, npages);
 502 }
 503
 504 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 505         dma_addr_t *dma_handle, gfp_t flag)
 506 {
 507         void *ret = NULL;
 508         dma_addr_t mapping;
 509         unsigned int npages, order;
 510         struct iommu_table *tbl = find_iommu_table(dev);
 511
 512         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 513         npages = size >> PAGE_SHIFT;
 514         order = get_order(size);
 515
 516         /* alloc enough pages (and possibly more) */
 517         ret = (void *)__get_free_pages(flag, order);
 518         if (!ret)
 519                 goto error;
 520         memset(ret, 0, size);
 521
 522         if (translation_enabled(tbl)) {
 523                 /* set up tces to cover the allocated range */
 524                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 525                 if (mapping == bad_dma_address)
 526                         goto free;
 527
 528                 *dma_handle = mapping;
 529         } else /* non translated slot */
 530                 *dma_handle = virt_to_bus(ret);
 531
 532         return ret;
 533
 534 free:
 535         free_pages((unsigned long)ret, get_order(size));
 536         ret = NULL;
 537 error:
 538         return ret;
 539 }
 540
 541 static const struct dma_mapping_ops calgary_dma_ops = {
 542         .alloc_coherent = calgary_alloc_coherent,
 543         .map_single = calgary_map_single,
 544         .unmap_single = calgary_unmap_single,
 545         .map_sg = calgary_map_sg,
 546         .unmap_sg = calgary_unmap_sg,
 547 };
 548
 549 static inline void __iomem * busno_to_bbar(unsigned char num)
 550 {
 551         return bus_info[num].bbar;
 552 }
 553
 554 static inline int busno_to_phbid(unsigned char num)
 555 {
 556         return bus_info[num].phbid;
 557 }
 558
 559 static inline unsigned long split_queue_offset(unsigned char num)
 560 {
 561         size_t idx = busno_to_phbid(num);
 562
 563         return split_queue_offsets[idx];
 564 }
 565
 566 static inline unsigned long tar_offset(unsigned char num)
 567 {
 568         size_t idx = busno_to_phbid(num);
 569
 570         return tar_offsets[idx];
 571 }
 572
 573 static inline unsigned long phb_offset(unsigned char num)
 574 {
 575         size_t idx = busno_to_phbid(num);
 576
 577         return phb_offsets[idx];
 578 }
 579
 580 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 581 {
 582         unsigned long target = ((unsigned long)bar) | offset;
 583         return (void __iomem*)target;
 584 }
 585
 586 static inline int is_calioc2(unsigned short device)
 587 {
 588         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 589 }
 590
 591 static inline int is_calgary(unsigned short device)
 592 {
 593         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 594 }
 595
 596 static inline int is_cal_pci_dev(unsigned short device)
 597 {
 598         return (is_calgary(device) || is_calioc2(device));
 599 }
 600
 601 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 602 {
 603         u64 val;
 604         u32 aer;
 605         int i = 0;
 606         void __iomem *bbar = tbl->bbar;
 607         void __iomem *target;
 608
 609         /* disable arbitration on the bus */
 610         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 611         aer = readl(target);
 612         writel(0, target);
 613
 614         /* read plssr to ensure it got there */
 615         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 616         val = readl(target);
 617
 618         /* poll split queues until all DMA activity is done */
 619         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 620         do {
 621                 val = readq(target);
 622                 i++;
 623         } while ((val & 0xff) != 0xff && i < 100);
 624         if (i == 100)
 625                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 626                        "continuing anyway\n");
 627
 628         /* invalidate TCE cache */
 629         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 630         writeq(tbl->tar_val, target);
 631
 632         /* enable arbitration */
 633         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 634         writel(aer, target);
 635         (void)readl(target); /* flush */
 636 }
 637
 638 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 639 {
 640         void __iomem *bbar = tbl->bbar;
 641         void __iomem *target;
 642         u64 val64;
 643         u32 val;
 644         int i = 0;
 645         int count = 1;
 646         unsigned char bus = tbl->it_busno;
 647
 648 begin:
 649         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 650                "sequence - count %d\n", bus, count);
 651
 652         /* 1. using the Page Migration Control reg set SoftStop */
 653         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 654         val = be32_to_cpu(readl(target));
 655         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 656         val |= PMR_SOFTSTOP;
 657         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 658         writel(cpu_to_be32(val), target);
 659
 660         /* 2. poll split queues until all DMA activity is done */
 661         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 662         target = calgary_reg(bbar, split_queue_offset(bus));
 663         do {
 664                 val64 = readq(target);
 665                 i++;
 666         } while ((val64 & 0xff) != 0xff && i < 100);
 667         if (i == 100)
 668                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 669                        "continuing anyway\n");
 670
 671         /* 3. poll Page Migration DEBUG for SoftStopFault */
 672         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 673         val = be32_to_cpu(readl(target));
 674         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 675
 676         /* 4. if SoftStopFault - goto (1) */
 677         if (val & PMR_SOFTSTOPFAULT) {
 678                 if (++count < 100)
 679                         goto begin;
 680                 else {
 681                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 682                                "aborting TCE cache flush sequence!\n");
 683                         return; /* pray for the best */
 684                 }
 685         }
 686
 687         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 688         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 689         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 690         val = be32_to_cpu(readl(target));
 691         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 692         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 693         val = be32_to_cpu(readl(target));
 694         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 695
 696         /* 6. invalidate TCE cache */
 697         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 698         target = calgary_reg(bbar, tar_offset(bus));
 699         writeq(tbl->tar_val, target);
 700
 701         /* 7. Re-read PMCR */
 702         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 703         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 704         val = be32_to_cpu(readl(target));
 705         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 706
 707         /* 8. Remove HardStop */
 708         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 709         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 710         val = 0;
 711         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 712         writel(cpu_to_be32(val), target);
 713         val = be32_to_cpu(readl(target));
 714         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 715 }
 716
 717 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 718         u64 limit)
 719 {
 720         unsigned int numpages;
 721
 722         limit = limit | 0xfffff;
 723         limit++;
 724
 725         numpages = ((limit - start) >> PAGE_SHIFT);
 726         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 727 }
 728
 729 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 730 {
 731         void __iomem *target;
 732         u64 low, high, sizelow;
 733         u64 start, limit;
 734         struct iommu_table *tbl = pci_iommu(dev->bus);
 735         unsigned char busnum = dev->bus->number;
 736         void __iomem *bbar = tbl->bbar;
 737
 738         /* peripheral MEM_1 region */
 739         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 740         low = be32_to_cpu(readl(target));
 741         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 742         high = be32_to_cpu(readl(target));
 743         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 744         sizelow = be32_to_cpu(readl(target));
 745
 746         start = (high << 32) | low;
 747         limit = sizelow;
 748
 749         calgary_reserve_mem_region(dev, start, limit);
 750 }
 751
 752 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 753 {
 754         void __iomem *target;
 755         u32 val32;
 756         u64 low, high, sizelow, sizehigh;
 757         u64 start, limit;
 758         struct iommu_table *tbl = pci_iommu(dev->bus);
 759         unsigned char busnum = dev->bus->number;
 760         void __iomem *bbar = tbl->bbar;
 761
 762         /* is it enabled? */
 763         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 764         val32 = be32_to_cpu(readl(target));
 765         if (!(val32 & PHB_MEM2_ENABLE))
 766                 return;
 767
 768         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 769         low = be32_to_cpu(readl(target));
 770         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 771         high = be32_to_cpu(readl(target));
 772         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 773         sizelow = be32_to_cpu(readl(target));
 774         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 775         sizehigh = be32_to_cpu(readl(target));
 776
 777         start = (high << 32) | low;
 778         limit = (sizehigh << 32) | sizelow;
 779
 780         calgary_reserve_mem_region(dev, start, limit);
 781 }
 782
 783 /*
 784  * some regions of the IO address space do not get translated, so we
 785  * must not give devices IO addresses in those regions. The regions
 786  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 787  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 788  * later.
 789  */
 790 static void __init calgary_reserve_regions(struct pci_dev *dev)
 791 {
 792         unsigned int npages;
 793         u64 start;
 794         struct iommu_table *tbl = pci_iommu(dev->bus);
 795
 796         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 797         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 798
 799         /* avoid the BIOS/VGA first 640KB-1MB region */
 800         /* for CalIOC2 - avoid the entire first MB */
 801         if (is_calgary(dev->device)) {
 802                 start = (640 * 1024);
 803                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 804         } else { /* calioc2 */
 805                 start = 0;
 806                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 807         }
 808         iommu_range_reserve(tbl, start, npages);
 809
 810         /* reserve the two PCI peripheral memory regions in IO space */
 811         calgary_reserve_peripheral_mem_1(dev);
 812         calgary_reserve_peripheral_mem_2(dev);
 813 }
 814
 815 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 816 {
 817         u64 val64;
 818         u64 table_phys;
 819         void __iomem *target;
 820         int ret;
 821         struct iommu_table *tbl;
 822
 823         /* build TCE tables for each PHB */
 824         ret = build_tce_table(dev, bbar);
 825         if (ret)
 826                 return ret;
 827
 828         tbl = pci_iommu(dev->bus);
 829         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 830         tce_free(tbl, 0, tbl->it_size);
 831
 832         if (is_calgary(dev->device))
 833                 tbl->chip_ops = &calgary_chip_ops;
 834         else if (is_calioc2(dev->device))
 835                 tbl->chip_ops = &calioc2_chip_ops;
 836         else
 837                 BUG();
 838
 839         calgary_reserve_regions(dev);
 840
 841         /* set TARs for each PHB */
 842         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 843         val64 = be64_to_cpu(readq(target));
 844
 845         /* zero out all TAR bits under sw control */
 846         val64 &= ~TAR_SW_BITS;
 847         table_phys = (u64)__pa(tbl->it_base);
 848
 849         val64 |= table_phys;
 850
 851         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 852         val64 |= (u64) specified_table_size;
 853
 854         tbl->tar_val = cpu_to_be64(val64);
 855
 856         writeq(tbl->tar_val, target);
 857         readq(target); /* flush */
 858
 859         return 0;
 860 }
 861
 862 static void __init calgary_free_bus(struct pci_dev *dev)
 863 {
 864         u64 val64;
 865         struct iommu_table *tbl = pci_iommu(dev->bus);
 866         void __iomem *target;
 867         unsigned int bitmapsz;
 868
 869         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 870         val64 = be64_to_cpu(readq(target));
 871         val64 &= ~TAR_SW_BITS;
 872         writeq(cpu_to_be64(val64), target);
 873         readq(target); /* flush */
 874
 875         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 876         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 877         tbl->it_map = NULL;
 878
 879         kfree(tbl);
 880
 881         set_pci_iommu(dev->bus, NULL);
 882
 883         /* Can't free bootmem allocated memory after system is up :-( */
 884         bus_info[dev->bus->number].tce_space = NULL;
 885 }
 886
 887 static void calgary_dump_error_regs(struct iommu_table *tbl)
 888 {
 889         void __iomem *bbar = tbl->bbar;
 890         void __iomem *target;
 891         u32 csr, plssr;
 892
 893         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 894         csr = be32_to_cpu(readl(target));
 895
 896         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 897         plssr = be32_to_cpu(readl(target));
 898
 899         /* If no error, the agent ID in the CSR is not valid */
 900         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 901                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 902 }
 903
 904 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 905 {
 906         void __iomem *bbar = tbl->bbar;
 907         u32 csr, csmr, plssr, mck, rcstat;
 908         void __iomem *target;
 909         unsigned long phboff = phb_offset(tbl->it_busno);
 910         unsigned long erroff;
 911         u32 errregs[7];
 912         int i;
 913
 914         /* dump CSR */
 915         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 916         csr = be32_to_cpu(readl(target));
 917         /* dump PLSSR */
 918         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 919         plssr = be32_to_cpu(readl(target));
 920         /* dump CSMR */
 921         target = calgary_reg(bbar, phboff | 0x290);
 922         csmr = be32_to_cpu(readl(target));
 923         /* dump mck */
 924         target = calgary_reg(bbar, phboff | 0x800);
 925         mck = be32_to_cpu(readl(target));
 926
 927         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 928                tbl->it_busno);
 929
 930         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 931                csr, plssr, csmr, mck);
 932
 933         /* dump rest of error regs */
 934         printk(KERN_EMERG "Calgary: ");
 935         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 936                 /* err regs are at 0x810 - 0x870 */
 937                 erroff = (0x810 + (i * 0x10));
 938                 target = calgary_reg(bbar, phboff | erroff);
 939                 errregs[i] = be32_to_cpu(readl(target));
 940                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 941         }
 942         printk("\n");
 943
 944         /* root complex status */
 945         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 946         rcstat = be32_to_cpu(readl(target));
 947         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 948                PHB_ROOT_COMPLEX_STATUS);
 949 }
 950
 951 static void calgary_watchdog(unsigned long data)
 952 {
 953         struct pci_dev *dev = (struct pci_dev *)data;
 954         struct iommu_table *tbl = pci_iommu(dev->bus);
 955         void __iomem *bbar = tbl->bbar;
 956         u32 val32;
 957         void __iomem *target;
 958
 959         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 960         val32 = be32_to_cpu(readl(target));
 961
 962         /* If no error, the agent ID in the CSR is not valid */
 963         if (val32 & CSR_AGENT_MASK) {
 964                 tbl->chip_ops->dump_error_regs(tbl);
 965
 966                 /* reset error */
 967                 writel(0, target);
 968
 969                 /* Disable bus that caused the error */
 970                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 971                                      PHB_CONFIG_RW_OFFSET);
 972                 val32 = be32_to_cpu(readl(target));
 973                 val32 |= PHB_SLOT_DISABLE;
 974                 writel(cpu_to_be32(val32), target);
 975                 readl(target); /* flush */
 976         } else {
 977                 /* Reset the timer */
 978                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 979         }
 980 }
 981
 982 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 983         unsigned char busnum, unsigned long timeout)
 984 {
 985         u64 val64;
 986         void __iomem *target;
 987         unsigned int phb_shift = ~0; /* silence gcc */
 988         u64 mask;
 989
 990         switch (busno_to_phbid(busnum)) {
 991         case 0: phb_shift = (63 - 19);
 992                 break;
 993         case 1: phb_shift = (63 - 23);
 994                 break;
 995         case 2: phb_shift = (63 - 27);
 996                 break;
 997         case 3: phb_shift = (63 - 35);
 998                 break;
 999         default:
1000                 BUG_ON(busno_to_phbid(busnum));
1001         }
1002
1003         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
1004         val64 = be64_to_cpu(readq(target));
1005
1006         /* zero out this PHB's timer bits */
1007         mask = ~(0xFUL << phb_shift);
1008         val64 &= mask;
1009         val64 |= (timeout << phb_shift);
1010         writeq(cpu_to_be64(val64), target);
1011         readq(target); /* flush */
1012 }
1013
1014 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1015 {
1016         unsigned char busnum = dev->bus->number;
1017         void __iomem *bbar = tbl->bbar;
1018         void __iomem *target;
1019         u32 val;
1020
1021         /*
1022          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1023          */
1024         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1025         val = cpu_to_be32(readl(target));
1026         val |= 0x00800000;
1027         writel(cpu_to_be32(val), target);
1028 }
1029
1030 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1031 {
1032         unsigned char busnum = dev->bus->number;
1033
1034         /*
1035          * Give split completion a longer timeout on bus 1 for aic94xx
1036          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1037          */
1038         if (is_calgary(dev->device) && (busnum == 1))
1039                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1040                                                      CCR_2SEC_TIMEOUT);
1041 }
1042
1043 static void __init calgary_enable_translation(struct pci_dev *dev)
1044 {
1045         u32 val32;
1046         unsigned char busnum;
1047         void __iomem *target;
1048         void __iomem *bbar;
1049         struct iommu_table *tbl;
1050
1051         busnum = dev->bus->number;
1052         tbl = pci_iommu(dev->bus);
1053         bbar = tbl->bbar;
1054
1055         /* enable TCE in PHB Config Register */
1056         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1057         val32 = be32_to_cpu(readl(target));
1058         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1059
1060         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1061                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1062                "Calgary" : "CalIOC2", busnum);
1063         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1064                "bus.\n");
1065
1066         writel(cpu_to_be32(val32), target);
1067         readl(target); /* flush */
1068
1069         init_timer(&tbl->watchdog_timer);
1070         tbl->watchdog_timer.function = &calgary_watchdog;
1071         tbl->watchdog_timer.data = (unsigned long)dev;
1072         mod_timer(&tbl->watchdog_timer, jiffies);
1073 }
1074
1075 static void __init calgary_disable_translation(struct pci_dev *dev)
1076 {
1077         u32 val32;
1078         unsigned char busnum;
1079         void __iomem *target;
1080         void __iomem *bbar;
1081         struct iommu_table *tbl;
1082
1083         busnum = dev->bus->number;
1084         tbl = pci_iommu(dev->bus);
1085         bbar = tbl->bbar;
1086
1087         /* disable TCE in PHB Config Register */
1088         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1089         val32 = be32_to_cpu(readl(target));
1090         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1091
1092         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1093         writel(cpu_to_be32(val32), target);
1094         readl(target); /* flush */
1095
1096         del_timer_sync(&tbl->watchdog_timer);
1097 }
1098
1099 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1100 {
1101         pci_dev_get(dev);
1102         set_pci_iommu(dev->bus, NULL);
1103
1104         /* is the device behind a bridge? */
1105         if (dev->bus->parent)
1106                 dev->bus->parent->self = dev;
1107         else
1108                 dev->bus->self = dev;
1109 }
1110
1111 static int __init calgary_init_one(struct pci_dev *dev)
1112 {
1113         void __iomem *bbar;
1114         struct iommu_table *tbl;
1115         int ret;
1116
1117         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1118
1119         bbar = busno_to_bbar(dev->bus->number);
1120         ret = calgary_setup_tar(dev, bbar);
1121         if (ret)
1122                 goto done;
1123
1124         pci_dev_get(dev);
1125
1126         if (dev->bus->parent) {
1127                 if (dev->bus->parent->self)
1128                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1129                                "bus->parent->self!\n", dev);
1130                 dev->bus->parent->self = dev;
1131         } else
1132                 dev->bus->self = dev;
1133
1134         tbl = pci_iommu(dev->bus);
1135         tbl->chip_ops->handle_quirks(tbl, dev);
1136
1137         calgary_enable_translation(dev);
1138
1139         return 0;
1140
1141 done:
1142         return ret;
1143 }
1144
1145 static int __init calgary_locate_bbars(void)
1146 {
1147         int ret;
1148         int rioidx, phb, bus;
1149         void __iomem *bbar;
1150         void __iomem *target;
1151         unsigned long offset;
1152         u8 start_bus, end_bus;
1153         u32 val;
1154
1155         ret = -ENODATA;
1156         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1157                 struct rio_detail *rio = rio_devs[rioidx];
1158
1159                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1160                         continue;
1161
1162                 /* map entire 1MB of Calgary config space */
1163                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1164                 if (!bbar)
1165                         goto error;
1166
1167                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1168                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1169                         target = calgary_reg(bbar, offset);
1170
1171                         val = be32_to_cpu(readl(target));
1172
1173                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1174                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1175
1176                         if (end_bus) {
1177                                 for (bus = start_bus; bus <= end_bus; bus++) {
1178                                         bus_info[bus].bbar = bbar;
1179                                         bus_info[bus].phbid = phb;
1180                                 }
1181                         } else {
1182                                 bus_info[start_bus].bbar = bbar;
1183                                 bus_info[start_bus].phbid = phb;
1184                         }
1185                 }
1186         }
1187
1188         return 0;
1189
1190 error:
1191         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1192         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1193                 if (bus_info[bus].bbar)
1194                         iounmap(bus_info[bus].bbar);
1195
1196         return ret;
1197 }
1198
1199 static int __init calgary_init(void)
1200 {
1201         int ret;
1202         struct pci_dev *dev = NULL;
1203         void *tce_space;
1204
1205         ret = calgary_locate_bbars();
1206         if (ret)
1207                 return ret;
1208
1209         do {
1210                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1211                 if (!dev)
1212                         break;
1213                 if (!is_cal_pci_dev(dev->device))
1214                         continue;
1215                 if (!translate_phb(dev)) {
1216                         calgary_init_one_nontraslated(dev);
1217                         continue;
1218                 }
1219                 tce_space = bus_info[dev->bus->number].tce_space;
1220                 if (!tce_space && !translate_empty_slots)
1221                         continue;
1222
1223                 ret = calgary_init_one(dev);
1224                 if (ret)
1225                         goto error;
1226         } while (1);
1227
1228         return ret;
1229
1230 error:
1231         do {
1232                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1233                                              PCI_ANY_ID, dev);
1234                 if (!dev)
1235                         break;
1236                 if (!is_cal_pci_dev(dev->device))
1237                         continue;
1238                 if (!translate_phb(dev)) {
1239                         pci_dev_put(dev);
1240                         continue;
1241                 }
1242                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1243                         continue;
1244
1245                 calgary_disable_translation(dev);
1246                 calgary_free_bus(dev);
1247                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1248         } while (1);
1249
1250         return ret;
1251 }
1252
1253 static inline int __init determine_tce_table_size(u64 ram)
1254 {
1255         int ret;
1256
1257         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1258                 return specified_table_size;
1259
1260         /*
1261          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1262          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1263          * larger table size has twice as many entries, so shift the
1264          * max ram address by 13 to divide by 8K and then look at the
1265          * order of the result to choose between 0-7.
1266          */
1267         ret = get_order(ram >> 13);
1268         if (ret > TCE_TABLE_SIZE_8M)
1269                 ret = TCE_TABLE_SIZE_8M;
1270
1271         return ret;
1272 }
1273
1274 static int __init build_detail_arrays(void)
1275 {
1276         unsigned long ptr;
1277         int i, scal_detail_size, rio_detail_size;
1278
1279         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1280                 printk(KERN_WARNING
1281                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1282                         "but system has %d nodes.\n",
1283                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1284                 return -ENODEV;
1285         }
1286
1287         switch (rio_table_hdr->version){
1288         case 2:
1289                 scal_detail_size = 11;
1290                 rio_detail_size = 13;
1291                 break;
1292         case 3:
1293                 scal_detail_size = 12;
1294                 rio_detail_size = 15;
1295                 break;
1296         default:
1297                 printk(KERN_WARNING
1298                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1299                        rio_table_hdr->version);
1300                 return -EPROTO;
1301         }
1302
1303         ptr = ((unsigned long)rio_table_hdr) + 3;
1304         for (i = 0; i < rio_table_hdr->num_scal_dev;
1305                     i++, ptr += scal_detail_size)
1306                 scal_devs[i] = (struct scal_detail *)ptr;
1307
1308         for (i = 0; i < rio_table_hdr->num_rio_dev;
1309                     i++, ptr += rio_detail_size)
1310                 rio_devs[i] = (struct rio_detail *)ptr;
1311
1312         return 0;
1313 }
1314
1315 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1316 {
1317         int dev;
1318         u32 val;
1319
1320         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1321                 /*
1322                  * FIXME: properly scan for devices accross the
1323                  * PCI-to-PCI bridge on every CalIOC2 port.
1324                  */
1325                 return 1;
1326         }
1327
1328         for (dev = 1; dev < 8; dev++) {
1329                 val = read_pci_config(bus, dev, 0, 0);
1330                 if (val != 0xffffffff)
1331                         break;
1332         }
1333         return (val != 0xffffffff);
1334 }
1335
1336 void __init detect_calgary(void)
1337 {
1338         int bus;
1339         void *tbl;
1340         int calgary_found = 0;
1341         unsigned long ptr;
1342         unsigned int offset, prev_offset;
1343         int ret;
1344
1345         /*
1346          * if the user specified iommu=off or iommu=soft or we found
1347          * another HW IOMMU already, bail out.
1348          */
1349         if (swiotlb || no_iommu || iommu_detected)
1350                 return;
1351
1352         if (!use_calgary)
1353                 return;
1354
1355         if (!early_pci_allowed())
1356                 return;
1357
1358         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1359
1360         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1361
1362         rio_table_hdr = NULL;
1363         prev_offset = 0;
1364         offset = 0x180;
1365         /*
1366          * The next offset is stored in the 1st word.
1367          * Only parse up until the offset increases:
1368          */
1369         while (offset > prev_offset) {
1370                 /* The block id is stored in the 2nd word */
1371                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1372                         /* set the pointer past the offset & block id */
1373                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1374                         break;
1375                 }
1376                 prev_offset = offset;
1377                 offset = *((unsigned short *)(ptr + offset));
1378         }
1379         if (!rio_table_hdr) {
1380                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1381                        "in EBDA - bailing!\n");
1382                 return;
1383         }
1384
1385         ret = build_detail_arrays();
1386         if (ret) {
1387                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1388                 return;
1389         }
1390
1391         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1392
1393         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1394                 struct calgary_bus_info *info = &bus_info[bus];
1395                 unsigned short pci_device;
1396                 u32 val;
1397
1398                 val = read_pci_config(bus, 0, 0, 0);
1399                 pci_device = (val & 0xFFFF0000) >> 16;
1400
1401                 if (!is_cal_pci_dev(pci_device))
1402                         continue;
1403
1404                 if (info->translation_disabled)
1405                         continue;
1406
1407                 if (calgary_bus_has_devices(bus, pci_device) ||
1408                     translate_empty_slots) {
1409                         tbl = alloc_tce_table();
1410                         if (!tbl)
1411                                 goto cleanup;
1412                         info->tce_space = tbl;
1413                         calgary_found = 1;
1414                 }
1415         }
1416
1417         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1418                calgary_found ? "found" : "not found");
1419
1420         if (calgary_found) {
1421                 iommu_detected = 1;
1422                 calgary_detected = 1;
1423                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1424                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1425                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1426                        debugging ? "enabled" : "disabled");
1427         }
1428         return;
1429
1430 cleanup:
1431         for (--bus; bus >= 0; --bus) {
1432                 struct calgary_bus_info *info = &bus_info[bus];
1433
1434                 if (info->tce_space)
1435                         free_tce_table(info->tce_space);
1436         }
1437 }
1438
1439 int __init calgary_iommu_init(void)
1440 {
1441         int ret;
1442
1443         if (no_iommu || swiotlb)
1444                 return -ENODEV;
1445
1446         if (!calgary_detected)
1447                 return -ENODEV;
1448
1449         /* ok, we're trying to use Calgary - let's roll */
1450         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1451
1452         ret = calgary_init();
1453         if (ret) {
1454                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1455                        "falling back to no_iommu\n", ret);
1456                 if (end_pfn > MAX_DMA32_PFN)
1457                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1458                                         "32bit PCI may malfunction.\n");
1459                 return ret;
1460         }
1461
1462         force_iommu = 1;
1463         bad_dma_address = 0x0;
1464         dma_ops = &calgary_dma_ops;
1465
1466         return 0;
1467 }
1468
1469 static int __init calgary_parse_options(char *p)
1470 {
1471         unsigned int bridge;
1472         size_t len;
1473         char* endp;
1474
1475         while (*p) {
1476                 if (!strncmp(p, "64k", 3))
1477                         specified_table_size = TCE_TABLE_SIZE_64K;
1478                 else if (!strncmp(p, "128k", 4))
1479                         specified_table_size = TCE_TABLE_SIZE_128K;
1480                 else if (!strncmp(p, "256k", 4))
1481                         specified_table_size = TCE_TABLE_SIZE_256K;
1482                 else if (!strncmp(p, "512k", 4))
1483                         specified_table_size = TCE_TABLE_SIZE_512K;
1484                 else if (!strncmp(p, "1M", 2))
1485                         specified_table_size = TCE_TABLE_SIZE_1M;
1486                 else if (!strncmp(p, "2M", 2))
1487                         specified_table_size = TCE_TABLE_SIZE_2M;
1488                 else if (!strncmp(p, "4M", 2))
1489                         specified_table_size = TCE_TABLE_SIZE_4M;
1490                 else if (!strncmp(p, "8M", 2))
1491                         specified_table_size = TCE_TABLE_SIZE_8M;
1492
1493                 len = strlen("translate_empty_slots");
1494                 if (!strncmp(p, "translate_empty_slots", len))
1495                         translate_empty_slots = 1;
1496
1497                 len = strlen("disable");
1498                 if (!strncmp(p, "disable", len)) {
1499                         p += len;
1500                         if (*p == '=')
1501                                 ++p;
1502                         if (*p == '\0')
1503                                 break;
1504                         bridge = simple_strtol(p, &endp, 0);
1505                         if (p == endp)
1506                                 break;
1507
1508                         if (bridge < MAX_PHB_BUS_NUM) {
1509                                 printk(KERN_INFO "Calgary: disabling "
1510                                        "translation for PHB %#x\n", bridge);
1511                                 bus_info[bridge].translation_disabled = 1;
1512                         }
1513                 }
1514
1515                 p = strpbrk(p, ",");
1516                 if (!p)
1517                         break;
1518
1519                 p++; /* skip ',' */
1520         }
1521         return 1;
1522 }
1523 __setup("calgary=", calgary_parse_options);
1524
1525 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1526 {
1527         struct iommu_table *tbl;
1528         unsigned int npages;
1529         int i;
1530
1531         tbl = pci_iommu(dev->bus);
1532
1533         for (i = 0; i < 4; i++) {
1534                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1535
1536                 /* Don't give out TCEs that map MEM resources */
1537                 if (!(r->flags & IORESOURCE_MEM))
1538                         continue;
1539
1540                 /* 0-based? we reserve the whole 1st MB anyway */
1541                 if (!r->start)
1542                         continue;
1543
1544                 /* cover the whole region */
1545                 npages = (r->end - r->start) >> PAGE_SHIFT;
1546                 npages++;
1547
1548                 iommu_range_reserve(tbl, r->start, npages);
1549         }
1550 }
1551
1552 static int __init calgary_fixup_tce_spaces(void)
1553 {
1554         struct pci_dev *dev = NULL;
1555         void *tce_space;
1556
1557         if (no_iommu || swiotlb || !calgary_detected)
1558                 return -ENODEV;
1559
1560         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1561
1562         do {
1563                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1564                 if (!dev)
1565                         break;
1566                 if (!is_cal_pci_dev(dev->device))
1567                         continue;
1568                 if (!translate_phb(dev))
1569                         continue;
1570
1571                 tce_space = bus_info[dev->bus->number].tce_space;
1572                 if (!tce_space)
1573                         continue;
1574
1575                 calgary_fixup_one_tce_space(dev);
1576
1577         } while (1);
1578
1579         return 0;
1580 }
1581
1582 /*
1583  * We need to be call after pcibios_assign_resources (fs_initcall level)
1584  * and before device_initcall.
1585  */
1586 rootfs_initcall(calgary_fixup_tce_spaces);