2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/scatterlist.h>
39 #include <asm/iommu.h>
40 #include <asm/calgary.h>
42 #include <asm/pci-direct.h>
43 #include <asm/system.h>
47 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
48 int use_calgary __read_mostly = 1;
50 int use_calgary __read_mostly = 0;
51 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
53 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
54 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
56 /* register offsets inside the host bridge space */
57 #define CALGARY_CONFIG_REG 0x0108
58 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
59 #define PHB_PLSSR_OFFSET 0x0120
60 #define PHB_CONFIG_RW_OFFSET 0x0160
61 #define PHB_IOBASE_BAR_LOW 0x0170
62 #define PHB_IOBASE_BAR_HIGH 0x0180
63 #define PHB_MEM_1_LOW 0x0190
64 #define PHB_MEM_1_HIGH 0x01A0
65 #define PHB_IO_ADDR_SIZE 0x01B0
66 #define PHB_MEM_1_SIZE 0x01C0
67 #define PHB_MEM_ST_OFFSET 0x01D0
68 #define PHB_AER_OFFSET 0x0200
69 #define PHB_CONFIG_0_HIGH 0x0220
70 #define PHB_CONFIG_0_LOW 0x0230
71 #define PHB_CONFIG_0_END 0x0240
72 #define PHB_MEM_2_LOW 0x02B0
73 #define PHB_MEM_2_HIGH 0x02C0
74 #define PHB_MEM_2_SIZE_HIGH 0x02D0
75 #define PHB_MEM_2_SIZE_LOW 0x02E0
76 #define PHB_DOSHOLE_OFFSET 0x08E0
78 /* CalIOC2 specific */
79 #define PHB_SAVIOR_L2 0x0DB0
80 #define PHB_PAGE_MIG_CTRL 0x0DA8
81 #define PHB_PAGE_MIG_DEBUG 0x0DA0
82 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
85 #define PHB_TCE_ENABLE 0x20000000
86 #define PHB_SLOT_DISABLE 0x1C000000
87 #define PHB_DAC_DISABLE 0x01000000
88 #define PHB_MEM2_ENABLE 0x00400000
89 #define PHB_MCSR_ENABLE 0x00100000
90 /* TAR (Table Address Register) */
91 #define TAR_SW_BITS 0x0000ffffffff800fUL
92 #define TAR_VALID 0x0000000000000008UL
93 /* CSR (Channel/DMA Status Register) */
94 #define CSR_AGENT_MASK 0xffe0ffff
95 /* CCR (Calgary Configuration Register) */
96 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
97 /* PMCR/PMDR (Page Migration Control/Debug Registers */
98 #define PMR_SOFTSTOP 0x80000000
99 #define PMR_SOFTSTOPFAULT 0x40000000
100 #define PMR_HARDSTOP 0x20000000
102 #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
103 #define MAX_NUM_CHASSIS 8 /* max number of chassis */
104 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
105 #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
106 #define PHBS_PER_CALGARY 4
108 /* register offsets in Calgary's internal register space */
109 static const unsigned long tar_offsets[] = {
116 static const unsigned long split_queue_offsets[] = {
117 0x4870 /* SPLIT QUEUE 0 */,
118 0x5870 /* SPLIT QUEUE 1 */,
119 0x6870 /* SPLIT QUEUE 2 */,
120 0x7870 /* SPLIT QUEUE 3 */
123 static const unsigned long phb_offsets[] = {
130 /* PHB debug registers */
132 static const unsigned long phb_debug_offsets[] = {
133 0x4000 /* PHB 0 DEBUG */,
134 0x5000 /* PHB 1 DEBUG */,
135 0x6000 /* PHB 2 DEBUG */,
136 0x7000 /* PHB 3 DEBUG */
140 * STUFF register for each debug PHB,
141 * byte 1 = start bus number, byte 2 = end bus number
144 #define PHB_DEBUG_STUFF_OFFSET 0x0020
146 #define EMERGENCY_PAGES 32 /* = 128KB */
148 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
149 static int translate_empty_slots __read_mostly = 0;
150 static int calgary_detected __read_mostly = 0;
152 static struct rio_table_hdr *rio_table_hdr __initdata;
153 static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
154 static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
156 struct calgary_bus_info {
158 unsigned char translation_disabled;
163 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
164 static void calgary_tce_cache_blast(struct iommu_table *tbl);
165 static void calgary_dump_error_regs(struct iommu_table *tbl);
166 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
167 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
168 static void calioc2_dump_error_regs(struct iommu_table *tbl);
170 static struct cal_chipset_ops calgary_chip_ops = {
171 .handle_quirks = calgary_handle_quirks,
172 .tce_cache_blast = calgary_tce_cache_blast,
173 .dump_error_regs = calgary_dump_error_regs
176 static struct cal_chipset_ops calioc2_chip_ops = {
177 .handle_quirks = calioc2_handle_quirks,
178 .tce_cache_blast = calioc2_tce_cache_blast,
179 .dump_error_regs = calioc2_dump_error_regs
182 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
184 /* enable this to stress test the chip's TCE cache */
185 #ifdef CONFIG_IOMMU_DEBUG
186 int debugging __read_mostly = 1;
188 static inline unsigned long verify_bit_range(unsigned long* bitmap,
189 int expected, unsigned long start, unsigned long end)
191 unsigned long idx = start;
193 BUG_ON(start >= end);
196 if (!!test_bit(idx, bitmap) != expected)
201 /* all bits have the expected value */
204 #else /* debugging is disabled */
205 int debugging __read_mostly = 0;
207 static inline unsigned long verify_bit_range(unsigned long* bitmap,
208 int expected, unsigned long start, unsigned long end)
213 #endif /* CONFIG_IOMMU_DEBUG */
215 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
219 npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
220 npages >>= PAGE_SHIFT;
225 static inline int translate_phb(struct pci_dev* dev)
227 int disabled = bus_info[dev->bus->number].translation_disabled;
231 static void iommu_range_reserve(struct iommu_table *tbl,
232 unsigned long start_addr, unsigned int npages)
236 unsigned long badbit;
239 index = start_addr >> PAGE_SHIFT;
241 /* bail out if we're asked to reserve a region we don't cover */
242 if (index >= tbl->it_size)
245 end = index + npages;
246 if (end > tbl->it_size) /* don't go off the table */
249 spin_lock_irqsave(&tbl->it_lock, flags);
251 badbit = verify_bit_range(tbl->it_map, 0, index, end);
252 if (badbit != ~0UL) {
253 if (printk_ratelimit())
254 printk(KERN_ERR "Calgary: entry already allocated at "
255 "0x%lx tbl %p dma 0x%lx npages %u\n",
256 badbit, tbl, start_addr, npages);
259 set_bit_string(tbl->it_map, index, npages);
261 spin_unlock_irqrestore(&tbl->it_lock, flags);
264 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
268 unsigned long offset;
272 spin_lock_irqsave(&tbl->it_lock, flags);
274 offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
275 tbl->it_size, npages);
276 if (offset == ~0UL) {
277 tbl->chip_ops->tce_cache_blast(tbl);
278 offset = find_next_zero_string(tbl->it_map, 0,
279 tbl->it_size, npages);
280 if (offset == ~0UL) {
281 printk(KERN_WARNING "Calgary: IOMMU full.\n");
282 spin_unlock_irqrestore(&tbl->it_lock, flags);
283 if (panic_on_overflow)
284 panic("Calgary: fix the allocator.\n");
286 return bad_dma_address;
290 set_bit_string(tbl->it_map, offset, npages);
291 tbl->it_hint = offset + npages;
292 BUG_ON(tbl->it_hint > tbl->it_size);
294 spin_unlock_irqrestore(&tbl->it_lock, flags);
299 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
300 unsigned int npages, int direction)
303 dma_addr_t ret = bad_dma_address;
305 entry = iommu_range_alloc(tbl, npages);
307 if (unlikely(entry == bad_dma_address))
310 /* set the return dma address */
311 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
313 /* put the TCEs in the HW table */
314 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
320 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
321 "iommu %p\n", npages, tbl);
322 return bad_dma_address;
325 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
329 unsigned long badbit;
330 unsigned long badend;
333 /* were we called with bad_dma_address? */
334 badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
335 if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
336 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
337 "address 0x%Lx\n", dma_addr);
342 entry = dma_addr >> PAGE_SHIFT;
344 BUG_ON(entry + npages > tbl->it_size);
346 tce_free(tbl, entry, npages);
348 spin_lock_irqsave(&tbl->it_lock, flags);
350 badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
351 if (badbit != ~0UL) {
352 if (printk_ratelimit())
353 printk(KERN_ERR "Calgary: bit is off at 0x%lx "
354 "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
355 badbit, tbl, dma_addr, entry, npages);
358 __clear_bit_string(tbl->it_map, entry, npages);
360 spin_unlock_irqrestore(&tbl->it_lock, flags);
363 static inline struct iommu_table *find_iommu_table(struct device *dev)
365 struct pci_dev *pdev;
366 struct pci_bus *pbus;
367 struct iommu_table *tbl;
369 pdev = to_pci_dev(dev);
373 /* is the device behind a bridge? Look for the root bus */
377 tbl = pci_iommu(pbus);
379 BUG_ON(tbl && (tbl->it_busno != pbus->number));
384 static void calgary_unmap_sg(struct device *dev,
385 struct scatterlist *sglist, int nelems, int direction)
387 struct iommu_table *tbl = find_iommu_table(dev);
388 struct scatterlist *s;
391 if (!translate_phb(to_pci_dev(dev)))
394 for_each_sg(sglist, s, nelems, i) {
396 dma_addr_t dma = s->dma_address;
397 unsigned int dmalen = s->dma_length;
402 npages = num_dma_pages(dma, dmalen);
403 iommu_free(tbl, dma, npages);
407 static int calgary_nontranslate_map_sg(struct device* dev,
408 struct scatterlist *sg, int nelems, int direction)
410 struct scatterlist *s;
413 for_each_sg(sg, s, nelems, i) {
415 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
416 s->dma_length = s->length;
421 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
422 int nelems, int direction)
424 struct iommu_table *tbl = find_iommu_table(dev);
425 struct scatterlist *s;
431 if (!translate_phb(to_pci_dev(dev)))
432 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
434 for_each_sg(sg, s, nelems, i) {
437 vaddr = (unsigned long)page_address(s->page) + s->offset;
438 npages = num_dma_pages(vaddr, s->length);
440 entry = iommu_range_alloc(tbl, npages);
441 if (entry == bad_dma_address) {
442 /* makes sure unmap knows to stop */
447 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
449 /* insert into HW table */
450 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
453 s->dma_length = s->length;
458 calgary_unmap_sg(dev, sg, nelems, direction);
459 for_each_sg(sg, s, nelems, i) {
460 sg->dma_address = bad_dma_address;
466 static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
467 size_t size, int direction)
469 dma_addr_t dma_handle = bad_dma_address;
472 struct iommu_table *tbl = find_iommu_table(dev);
474 uaddr = (unsigned long)vaddr;
475 npages = num_dma_pages(uaddr, size);
477 if (translate_phb(to_pci_dev(dev)))
478 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
480 dma_handle = virt_to_bus(vaddr);
485 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
486 size_t size, int direction)
488 struct iommu_table *tbl = find_iommu_table(dev);
491 if (!translate_phb(to_pci_dev(dev)))
494 npages = num_dma_pages(dma_handle, size);
495 iommu_free(tbl, dma_handle, npages);
498 static void* calgary_alloc_coherent(struct device *dev, size_t size,
499 dma_addr_t *dma_handle, gfp_t flag)
503 unsigned int npages, order;
504 struct iommu_table *tbl = find_iommu_table(dev);
506 size = PAGE_ALIGN(size); /* size rounded up to full pages */
507 npages = size >> PAGE_SHIFT;
508 order = get_order(size);
510 /* alloc enough pages (and possibly more) */
511 ret = (void *)__get_free_pages(flag, order);
514 memset(ret, 0, size);
516 if (translate_phb(to_pci_dev(dev))) {
517 /* set up tces to cover the allocated range */
518 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
519 if (mapping == bad_dma_address)
522 *dma_handle = mapping;
523 } else /* non translated slot */
524 *dma_handle = virt_to_bus(ret);
529 free_pages((unsigned long)ret, get_order(size));
535 static const struct dma_mapping_ops calgary_dma_ops = {
536 .alloc_coherent = calgary_alloc_coherent,
537 .map_single = calgary_map_single,
538 .unmap_single = calgary_unmap_single,
539 .map_sg = calgary_map_sg,
540 .unmap_sg = calgary_unmap_sg,
543 static inline void __iomem * busno_to_bbar(unsigned char num)
545 return bus_info[num].bbar;
548 static inline int busno_to_phbid(unsigned char num)
550 return bus_info[num].phbid;
553 static inline unsigned long split_queue_offset(unsigned char num)
555 size_t idx = busno_to_phbid(num);
557 return split_queue_offsets[idx];
560 static inline unsigned long tar_offset(unsigned char num)
562 size_t idx = busno_to_phbid(num);
564 return tar_offsets[idx];
567 static inline unsigned long phb_offset(unsigned char num)
569 size_t idx = busno_to_phbid(num);
571 return phb_offsets[idx];
574 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
576 unsigned long target = ((unsigned long)bar) | offset;
577 return (void __iomem*)target;
580 static inline int is_calioc2(unsigned short device)
582 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
585 static inline int is_calgary(unsigned short device)
587 return (device == PCI_DEVICE_ID_IBM_CALGARY);
590 static inline int is_cal_pci_dev(unsigned short device)
592 return (is_calgary(device) || is_calioc2(device));
595 static void calgary_tce_cache_blast(struct iommu_table *tbl)
600 void __iomem *bbar = tbl->bbar;
601 void __iomem *target;
603 /* disable arbitration on the bus */
604 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
608 /* read plssr to ensure it got there */
609 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
612 /* poll split queues until all DMA activity is done */
613 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
617 } while ((val & 0xff) != 0xff && i < 100);
619 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
620 "continuing anyway\n");
622 /* invalidate TCE cache */
623 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
624 writeq(tbl->tar_val, target);
626 /* enable arbitration */
627 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
629 (void)readl(target); /* flush */
632 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
634 void __iomem *bbar = tbl->bbar;
635 void __iomem *target;
640 unsigned char bus = tbl->it_busno;
643 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
644 "sequence - count %d\n", bus, count);
646 /* 1. using the Page Migration Control reg set SoftStop */
647 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
648 val = be32_to_cpu(readl(target));
649 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
651 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
652 writel(cpu_to_be32(val), target);
654 /* 2. poll split queues until all DMA activity is done */
655 printk(KERN_DEBUG "2a. starting to poll split queues\n");
656 target = calgary_reg(bbar, split_queue_offset(bus));
658 val64 = readq(target);
660 } while ((val64 & 0xff) != 0xff && i < 100);
662 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
663 "continuing anyway\n");
665 /* 3. poll Page Migration DEBUG for SoftStopFault */
666 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
667 val = be32_to_cpu(readl(target));
668 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
670 /* 4. if SoftStopFault - goto (1) */
671 if (val & PMR_SOFTSTOPFAULT) {
675 printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
676 "aborting TCE cache flush sequence!\n");
677 return; /* pray for the best */
681 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
682 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
683 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
684 val = be32_to_cpu(readl(target));
685 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
686 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
687 val = be32_to_cpu(readl(target));
688 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
690 /* 6. invalidate TCE cache */
691 printk(KERN_DEBUG "6. invalidating TCE cache\n");
692 target = calgary_reg(bbar, tar_offset(bus));
693 writeq(tbl->tar_val, target);
695 /* 7. Re-read PMCR */
696 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
697 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
698 val = be32_to_cpu(readl(target));
699 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
701 /* 8. Remove HardStop */
702 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
703 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
705 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
706 writel(cpu_to_be32(val), target);
707 val = be32_to_cpu(readl(target));
708 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
711 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
714 unsigned int numpages;
716 limit = limit | 0xfffff;
719 numpages = ((limit - start) >> PAGE_SHIFT);
720 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
723 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
725 void __iomem *target;
726 u64 low, high, sizelow;
728 struct iommu_table *tbl = pci_iommu(dev->bus);
729 unsigned char busnum = dev->bus->number;
730 void __iomem *bbar = tbl->bbar;
732 /* peripheral MEM_1 region */
733 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
734 low = be32_to_cpu(readl(target));
735 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
736 high = be32_to_cpu(readl(target));
737 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
738 sizelow = be32_to_cpu(readl(target));
740 start = (high << 32) | low;
743 calgary_reserve_mem_region(dev, start, limit);
746 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
748 void __iomem *target;
750 u64 low, high, sizelow, sizehigh;
752 struct iommu_table *tbl = pci_iommu(dev->bus);
753 unsigned char busnum = dev->bus->number;
754 void __iomem *bbar = tbl->bbar;
757 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
758 val32 = be32_to_cpu(readl(target));
759 if (!(val32 & PHB_MEM2_ENABLE))
762 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
763 low = be32_to_cpu(readl(target));
764 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
765 high = be32_to_cpu(readl(target));
766 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
767 sizelow = be32_to_cpu(readl(target));
768 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
769 sizehigh = be32_to_cpu(readl(target));
771 start = (high << 32) | low;
772 limit = (sizehigh << 32) | sizelow;
774 calgary_reserve_mem_region(dev, start, limit);
778 * some regions of the IO address space do not get translated, so we
779 * must not give devices IO addresses in those regions. The regions
780 * are the 640KB-1MB region and the two PCI peripheral memory holes.
781 * Reserve all of them in the IOMMU bitmap to avoid giving them out
784 static void __init calgary_reserve_regions(struct pci_dev *dev)
788 struct iommu_table *tbl = pci_iommu(dev->bus);
790 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
791 iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
793 /* avoid the BIOS/VGA first 640KB-1MB region */
794 /* for CalIOC2 - avoid the entire first MB */
795 if (is_calgary(dev->device)) {
796 start = (640 * 1024);
797 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
798 } else { /* calioc2 */
800 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
802 iommu_range_reserve(tbl, start, npages);
804 /* reserve the two PCI peripheral memory regions in IO space */
805 calgary_reserve_peripheral_mem_1(dev);
806 calgary_reserve_peripheral_mem_2(dev);
809 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
813 void __iomem *target;
815 struct iommu_table *tbl;
817 /* build TCE tables for each PHB */
818 ret = build_tce_table(dev, bbar);
822 tbl = pci_iommu(dev->bus);
823 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
824 tce_free(tbl, 0, tbl->it_size);
826 if (is_calgary(dev->device))
827 tbl->chip_ops = &calgary_chip_ops;
828 else if (is_calioc2(dev->device))
829 tbl->chip_ops = &calioc2_chip_ops;
833 calgary_reserve_regions(dev);
835 /* set TARs for each PHB */
836 target = calgary_reg(bbar, tar_offset(dev->bus->number));
837 val64 = be64_to_cpu(readq(target));
839 /* zero out all TAR bits under sw control */
840 val64 &= ~TAR_SW_BITS;
841 table_phys = (u64)__pa(tbl->it_base);
845 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
846 val64 |= (u64) specified_table_size;
848 tbl->tar_val = cpu_to_be64(val64);
850 writeq(tbl->tar_val, target);
851 readq(target); /* flush */
856 static void __init calgary_free_bus(struct pci_dev *dev)
859 struct iommu_table *tbl = pci_iommu(dev->bus);
860 void __iomem *target;
861 unsigned int bitmapsz;
863 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
864 val64 = be64_to_cpu(readq(target));
865 val64 &= ~TAR_SW_BITS;
866 writeq(cpu_to_be64(val64), target);
867 readq(target); /* flush */
869 bitmapsz = tbl->it_size / BITS_PER_BYTE;
870 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
875 set_pci_iommu(dev->bus, NULL);
877 /* Can't free bootmem allocated memory after system is up :-( */
878 bus_info[dev->bus->number].tce_space = NULL;
881 static void calgary_dump_error_regs(struct iommu_table *tbl)
883 void __iomem *bbar = tbl->bbar;
884 void __iomem *target;
887 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
888 csr = be32_to_cpu(readl(target));
890 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
891 plssr = be32_to_cpu(readl(target));
893 /* If no error, the agent ID in the CSR is not valid */
894 printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
895 "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
898 static void calioc2_dump_error_regs(struct iommu_table *tbl)
900 void __iomem *bbar = tbl->bbar;
901 u32 csr, csmr, plssr, mck, rcstat;
902 void __iomem *target;
903 unsigned long phboff = phb_offset(tbl->it_busno);
904 unsigned long erroff;
909 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
910 csr = be32_to_cpu(readl(target));
912 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
913 plssr = be32_to_cpu(readl(target));
915 target = calgary_reg(bbar, phboff | 0x290);
916 csmr = be32_to_cpu(readl(target));
918 target = calgary_reg(bbar, phboff | 0x800);
919 mck = be32_to_cpu(readl(target));
921 printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
924 printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
925 csr, plssr, csmr, mck);
927 /* dump rest of error regs */
928 printk(KERN_EMERG "Calgary: ");
929 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
930 /* err regs are at 0x810 - 0x870 */
931 erroff = (0x810 + (i * 0x10));
932 target = calgary_reg(bbar, phboff | erroff);
933 errregs[i] = be32_to_cpu(readl(target));
934 printk("0x%08x@0x%lx ", errregs[i], erroff);
938 /* root complex status */
939 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
940 rcstat = be32_to_cpu(readl(target));
941 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
942 PHB_ROOT_COMPLEX_STATUS);
945 static void calgary_watchdog(unsigned long data)
947 struct pci_dev *dev = (struct pci_dev *)data;
948 struct iommu_table *tbl = pci_iommu(dev->bus);
949 void __iomem *bbar = tbl->bbar;
951 void __iomem *target;
953 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
954 val32 = be32_to_cpu(readl(target));
956 /* If no error, the agent ID in the CSR is not valid */
957 if (val32 & CSR_AGENT_MASK) {
958 tbl->chip_ops->dump_error_regs(tbl);
963 /* Disable bus that caused the error */
964 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
965 PHB_CONFIG_RW_OFFSET);
966 val32 = be32_to_cpu(readl(target));
967 val32 |= PHB_SLOT_DISABLE;
968 writel(cpu_to_be32(val32), target);
969 readl(target); /* flush */
971 /* Reset the timer */
972 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
976 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
977 unsigned char busnum, unsigned long timeout)
980 void __iomem *target;
981 unsigned int phb_shift = ~0; /* silence gcc */
984 switch (busno_to_phbid(busnum)) {
985 case 0: phb_shift = (63 - 19);
987 case 1: phb_shift = (63 - 23);
989 case 2: phb_shift = (63 - 27);
991 case 3: phb_shift = (63 - 35);
994 BUG_ON(busno_to_phbid(busnum));
997 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
998 val64 = be64_to_cpu(readq(target));
1000 /* zero out this PHB's timer bits */
1001 mask = ~(0xFUL << phb_shift);
1003 val64 |= (timeout << phb_shift);
1004 writeq(cpu_to_be64(val64), target);
1005 readq(target); /* flush */
1008 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1010 unsigned char busnum = dev->bus->number;
1011 void __iomem *bbar = tbl->bbar;
1012 void __iomem *target;
1016 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1018 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1019 val = cpu_to_be32(readl(target));
1021 writel(cpu_to_be32(val), target);
1024 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1026 unsigned char busnum = dev->bus->number;
1029 * Give split completion a longer timeout on bus 1 for aic94xx
1030 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1032 if (is_calgary(dev->device) && (busnum == 1))
1033 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1037 static void __init calgary_enable_translation(struct pci_dev *dev)
1040 unsigned char busnum;
1041 void __iomem *target;
1043 struct iommu_table *tbl;
1045 busnum = dev->bus->number;
1046 tbl = pci_iommu(dev->bus);
1049 /* enable TCE in PHB Config Register */
1050 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1051 val32 = be32_to_cpu(readl(target));
1052 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1054 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1055 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1056 "Calgary" : "CalIOC2", busnum);
1057 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1060 writel(cpu_to_be32(val32), target);
1061 readl(target); /* flush */
1063 init_timer(&tbl->watchdog_timer);
1064 tbl->watchdog_timer.function = &calgary_watchdog;
1065 tbl->watchdog_timer.data = (unsigned long)dev;
1066 mod_timer(&tbl->watchdog_timer, jiffies);
1069 static void __init calgary_disable_translation(struct pci_dev *dev)
1072 unsigned char busnum;
1073 void __iomem *target;
1075 struct iommu_table *tbl;
1077 busnum = dev->bus->number;
1078 tbl = pci_iommu(dev->bus);
1081 /* disable TCE in PHB Config Register */
1082 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1083 val32 = be32_to_cpu(readl(target));
1084 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1086 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1087 writel(cpu_to_be32(val32), target);
1088 readl(target); /* flush */
1090 del_timer_sync(&tbl->watchdog_timer);
1093 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1096 set_pci_iommu(dev->bus, NULL);
1098 /* is the device behind a bridge? */
1099 if (dev->bus->parent)
1100 dev->bus->parent->self = dev;
1102 dev->bus->self = dev;
1105 static int __init calgary_init_one(struct pci_dev *dev)
1108 struct iommu_table *tbl;
1111 BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1113 bbar = busno_to_bbar(dev->bus->number);
1114 ret = calgary_setup_tar(dev, bbar);
1120 if (dev->bus->parent) {
1121 if (dev->bus->parent->self)
1122 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1123 "bus->parent->self!\n", dev);
1124 dev->bus->parent->self = dev;
1126 dev->bus->self = dev;
1128 tbl = pci_iommu(dev->bus);
1129 tbl->chip_ops->handle_quirks(tbl, dev);
1131 calgary_enable_translation(dev);
1139 static int __init calgary_locate_bbars(void)
1142 int rioidx, phb, bus;
1144 void __iomem *target;
1145 unsigned long offset;
1146 u8 start_bus, end_bus;
1150 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1151 struct rio_detail *rio = rio_devs[rioidx];
1153 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1156 /* map entire 1MB of Calgary config space */
1157 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1161 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1162 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1163 target = calgary_reg(bbar, offset);
1165 val = be32_to_cpu(readl(target));
1167 start_bus = (u8)((val & 0x00FF0000) >> 16);
1168 end_bus = (u8)((val & 0x0000FF00) >> 8);
1171 for (bus = start_bus; bus <= end_bus; bus++) {
1172 bus_info[bus].bbar = bbar;
1173 bus_info[bus].phbid = phb;
1176 bus_info[start_bus].bbar = bbar;
1177 bus_info[start_bus].phbid = phb;
1185 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1186 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1187 if (bus_info[bus].bbar)
1188 iounmap(bus_info[bus].bbar);
1193 static int __init calgary_init(void)
1196 struct pci_dev *dev = NULL;
1199 ret = calgary_locate_bbars();
1204 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1207 if (!is_cal_pci_dev(dev->device))
1209 if (!translate_phb(dev)) {
1210 calgary_init_one_nontraslated(dev);
1213 tce_space = bus_info[dev->bus->number].tce_space;
1214 if (!tce_space && !translate_empty_slots)
1217 ret = calgary_init_one(dev);
1226 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1230 if (!is_cal_pci_dev(dev->device))
1232 if (!translate_phb(dev)) {
1236 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1239 calgary_disable_translation(dev);
1240 calgary_free_bus(dev);
1241 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1247 static inline int __init determine_tce_table_size(u64 ram)
1251 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1252 return specified_table_size;
1255 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1256 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1257 * larger table size has twice as many entries, so shift the
1258 * max ram address by 13 to divide by 8K and then look at the
1259 * order of the result to choose between 0-7.
1261 ret = get_order(ram >> 13);
1262 if (ret > TCE_TABLE_SIZE_8M)
1263 ret = TCE_TABLE_SIZE_8M;
1268 static int __init build_detail_arrays(void)
1271 int i, scal_detail_size, rio_detail_size;
1273 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1275 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1276 "but system has %d nodes.\n",
1277 MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1281 switch (rio_table_hdr->version){
1283 scal_detail_size = 11;
1284 rio_detail_size = 13;
1287 scal_detail_size = 12;
1288 rio_detail_size = 15;
1292 "Calgary: Invalid Rio Grande Table Version: %d\n",
1293 rio_table_hdr->version);
1297 ptr = ((unsigned long)rio_table_hdr) + 3;
1298 for (i = 0; i < rio_table_hdr->num_scal_dev;
1299 i++, ptr += scal_detail_size)
1300 scal_devs[i] = (struct scal_detail *)ptr;
1302 for (i = 0; i < rio_table_hdr->num_rio_dev;
1303 i++, ptr += rio_detail_size)
1304 rio_devs[i] = (struct rio_detail *)ptr;
1309 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1314 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1316 * FIXME: properly scan for devices accross the
1317 * PCI-to-PCI bridge on every CalIOC2 port.
1322 for (dev = 1; dev < 8; dev++) {
1323 val = read_pci_config(bus, dev, 0, 0);
1324 if (val != 0xffffffff)
1327 return (val != 0xffffffff);
1330 void __init detect_calgary(void)
1334 int calgary_found = 0;
1336 unsigned int offset, prev_offset;
1340 * if the user specified iommu=off or iommu=soft or we found
1341 * another HW IOMMU already, bail out.
1343 if (swiotlb || no_iommu || iommu_detected)
1349 if (!early_pci_allowed())
1352 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1354 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1356 rio_table_hdr = NULL;
1360 * The next offset is stored in the 1st word.
1361 * Only parse up until the offset increases:
1363 while (offset > prev_offset) {
1364 /* The block id is stored in the 2nd word */
1365 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1366 /* set the pointer past the offset & block id */
1367 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1370 prev_offset = offset;
1371 offset = *((unsigned short *)(ptr + offset));
1373 if (!rio_table_hdr) {
1374 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1375 "in EBDA - bailing!\n");
1379 ret = build_detail_arrays();
1381 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1385 specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1387 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1388 struct calgary_bus_info *info = &bus_info[bus];
1389 unsigned short pci_device;
1392 val = read_pci_config(bus, 0, 0, 0);
1393 pci_device = (val & 0xFFFF0000) >> 16;
1395 if (!is_cal_pci_dev(pci_device))
1398 if (info->translation_disabled)
1401 if (calgary_bus_has_devices(bus, pci_device) ||
1402 translate_empty_slots) {
1403 tbl = alloc_tce_table();
1406 info->tce_space = tbl;
1411 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1412 calgary_found ? "found" : "not found");
1414 if (calgary_found) {
1416 calgary_detected = 1;
1417 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1418 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1419 "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1420 debugging ? "enabled" : "disabled");
1425 for (--bus; bus >= 0; --bus) {
1426 struct calgary_bus_info *info = &bus_info[bus];
1428 if (info->tce_space)
1429 free_tce_table(info->tce_space);
1433 int __init calgary_iommu_init(void)
1437 if (no_iommu || swiotlb)
1440 if (!calgary_detected)
1443 /* ok, we're trying to use Calgary - let's roll */
1444 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1446 ret = calgary_init();
1448 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1449 "falling back to no_iommu\n", ret);
1450 if (end_pfn > MAX_DMA32_PFN)
1451 printk(KERN_ERR "WARNING more than 4GB of memory, "
1452 "32bit PCI may malfunction.\n");
1457 bad_dma_address = 0x0;
1458 dma_ops = &calgary_dma_ops;
1463 static int __init calgary_parse_options(char *p)
1465 unsigned int bridge;
1470 if (!strncmp(p, "64k", 3))
1471 specified_table_size = TCE_TABLE_SIZE_64K;
1472 else if (!strncmp(p, "128k", 4))
1473 specified_table_size = TCE_TABLE_SIZE_128K;
1474 else if (!strncmp(p, "256k", 4))
1475 specified_table_size = TCE_TABLE_SIZE_256K;
1476 else if (!strncmp(p, "512k", 4))
1477 specified_table_size = TCE_TABLE_SIZE_512K;
1478 else if (!strncmp(p, "1M", 2))
1479 specified_table_size = TCE_TABLE_SIZE_1M;
1480 else if (!strncmp(p, "2M", 2))
1481 specified_table_size = TCE_TABLE_SIZE_2M;
1482 else if (!strncmp(p, "4M", 2))
1483 specified_table_size = TCE_TABLE_SIZE_4M;
1484 else if (!strncmp(p, "8M", 2))
1485 specified_table_size = TCE_TABLE_SIZE_8M;
1487 len = strlen("translate_empty_slots");
1488 if (!strncmp(p, "translate_empty_slots", len))
1489 translate_empty_slots = 1;
1491 len = strlen("disable");
1492 if (!strncmp(p, "disable", len)) {
1498 bridge = simple_strtol(p, &endp, 0);
1502 if (bridge < MAX_PHB_BUS_NUM) {
1503 printk(KERN_INFO "Calgary: disabling "
1504 "translation for PHB %#x\n", bridge);
1505 bus_info[bridge].translation_disabled = 1;
1509 p = strpbrk(p, ",");
1517 __setup("calgary=", calgary_parse_options);
1519 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1521 struct iommu_table *tbl;
1522 unsigned int npages;
1525 tbl = pci_iommu(dev->bus);
1527 for (i = 0; i < 4; i++) {
1528 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1530 /* Don't give out TCEs that map MEM resources */
1531 if (!(r->flags & IORESOURCE_MEM))
1534 /* 0-based? we reserve the whole 1st MB anyway */
1538 /* cover the whole region */
1539 npages = (r->end - r->start) >> PAGE_SHIFT;
1542 iommu_range_reserve(tbl, r->start, npages);
1546 static int __init calgary_fixup_tce_spaces(void)
1548 struct pci_dev *dev = NULL;
1551 if (no_iommu || swiotlb || !calgary_detected)
1554 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1557 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1560 if (!is_cal_pci_dev(dev->device))
1562 if (!translate_phb(dev))
1565 tce_space = bus_info[dev->bus->number].tce_space;
1569 calgary_fixup_one_tce_space(dev);
1577 * We need to be call after pcibios_assign_resources (fs_initcall level)
1578 * and before device_initcall.
1580 rootfs_initcall(calgary_fixup_tce_spaces);