2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
31 #include <mach_apic.h>
32 #include <mach_apicdef.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 int apic_version [MAX_APICS];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
48 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
49 int mp_bus_id_to_node [MAX_MP_BUSSES];
50 int mp_bus_id_to_local [MAX_MP_BUSSES];
51 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
52 static int mp_current_pci_id;
54 /* I/O APIC entries */
55 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
57 /* # of MP IRQ source entries */
58 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
60 /* MP IRQ source entries */
66 unsigned long mp_lapic_addr;
68 unsigned int def_to_bigsmp = 0;
70 /* Processor that is doing the boot up */
71 unsigned int boot_cpu_physical_apicid = -1U;
72 /* Internal processor count */
73 unsigned int num_processors;
75 unsigned disabled_cpus __cpuinitdata;
77 /* Bitmask of physically existing CPUs */
78 physid_mask_t phys_cpu_present_map;
80 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
83 * Intel MP BIOS table parsing routines:
88 * Checksum an MP configuration block.
91 static int __init mpf_checksum(unsigned char *mp, int len)
102 * Have to match translation table entries to main table entries by counter
103 * hence the mpc_record variable .... can't see a less disgusting way of
107 static int mpc_record;
108 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
110 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
113 physid_mask_t phys_cpu;
115 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
120 apicid = mpc_apic_id(m, translation_table[mpc_record]);
122 if (m->mpc_featureflag&(1<<0))
123 Dprintk(" Floating point unit present.\n");
124 if (m->mpc_featureflag&(1<<7))
125 Dprintk(" Machine Exception supported.\n");
126 if (m->mpc_featureflag&(1<<8))
127 Dprintk(" 64 bit compare & exchange supported.\n");
128 if (m->mpc_featureflag&(1<<9))
129 Dprintk(" Internal APIC present.\n");
130 if (m->mpc_featureflag&(1<<11))
131 Dprintk(" SEP present.\n");
132 if (m->mpc_featureflag&(1<<12))
133 Dprintk(" MTRR present.\n");
134 if (m->mpc_featureflag&(1<<13))
135 Dprintk(" PGE present.\n");
136 if (m->mpc_featureflag&(1<<14))
137 Dprintk(" MCA present.\n");
138 if (m->mpc_featureflag&(1<<15))
139 Dprintk(" CMOV present.\n");
140 if (m->mpc_featureflag&(1<<16))
141 Dprintk(" PAT present.\n");
142 if (m->mpc_featureflag&(1<<17))
143 Dprintk(" PSE present.\n");
144 if (m->mpc_featureflag&(1<<18))
145 Dprintk(" PSN present.\n");
146 if (m->mpc_featureflag&(1<<19))
147 Dprintk(" Cache Line Flush Instruction present.\n");
149 if (m->mpc_featureflag&(1<<21))
150 Dprintk(" Debug Trace and EMON Store present.\n");
151 if (m->mpc_featureflag&(1<<22))
152 Dprintk(" ACPI Thermal Throttle Registers present.\n");
153 if (m->mpc_featureflag&(1<<23))
154 Dprintk(" MMX present.\n");
155 if (m->mpc_featureflag&(1<<24))
156 Dprintk(" FXSR present.\n");
157 if (m->mpc_featureflag&(1<<25))
158 Dprintk(" XMM present.\n");
159 if (m->mpc_featureflag&(1<<26))
160 Dprintk(" Willamette New Instructions present.\n");
161 if (m->mpc_featureflag&(1<<27))
162 Dprintk(" Self Snoop present.\n");
163 if (m->mpc_featureflag&(1<<28))
164 Dprintk(" HT present.\n");
165 if (m->mpc_featureflag&(1<<29))
166 Dprintk(" Thermal Monitor present.\n");
167 /* 30, 31 Reserved */
170 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
171 Dprintk(" Bootup CPU\n");
172 boot_cpu_physical_apicid = m->mpc_apicid;
175 ver = m->mpc_apicver;
181 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
182 "fixing up to 0x10. (tell your hw vendor)\n",
186 apic_version[m->mpc_apicid] = ver;
188 phys_cpu = apicid_to_cpu_present(apicid);
189 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
191 if (num_processors >= NR_CPUS) {
192 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
193 " Processor ignored.\n", NR_CPUS);
197 if (num_processors >= maxcpus) {
198 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
199 " Processor ignored.\n", maxcpus);
203 cpu_set(num_processors, cpu_possible_map);
207 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
208 * but we need to work other dependencies like SMP_SUSPEND etc
209 * before this can be done without some confusion.
210 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
211 * - Ashok Raj <ashok.raj@intel.com>
213 if (num_processors > 8) {
214 switch (boot_cpu_data.x86_vendor) {
215 case X86_VENDOR_INTEL:
216 if (!APIC_XAPIC(ver)) {
220 /* If P4 and above fall through */
225 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
228 static void __init MP_bus_info (struct mpc_config_bus *m)
232 memcpy(str, m->mpc_bustype, 6);
235 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
237 #if MAX_MP_BUSSES < 256
238 if (m->mpc_busid >= MAX_MP_BUSSES) {
239 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
240 " is too large, max. supported is %d\n",
241 m->mpc_busid, str, MAX_MP_BUSSES - 1);
246 set_bit(m->mpc_busid, mp_bus_not_pci);
247 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
248 mpc_oem_pci_bus(m, translation_table[mpc_record]);
249 clear_bit(m->mpc_busid, mp_bus_not_pci);
250 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
252 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
253 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
254 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
255 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
256 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
257 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
258 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
259 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
261 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
266 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
268 if (!(m->mpc_flags & MPC_APIC_USABLE))
271 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
272 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
273 if (nr_ioapics >= MAX_IO_APICS) {
274 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
275 MAX_IO_APICS, nr_ioapics);
276 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
278 if (!m->mpc_apicaddr) {
279 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
280 " found in MP table, skipping!\n");
283 mp_ioapics[nr_ioapics] = *m;
287 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
289 mp_irqs [mp_irq_entries] = *m;
290 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
291 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
292 m->mpc_irqtype, m->mpc_irqflag & 3,
293 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
294 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
295 if (++mp_irq_entries == MAX_IRQ_SOURCES)
296 panic("Max # of irq sources exceeded!!\n");
299 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
301 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
302 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
303 m->mpc_irqtype, m->mpc_irqflag & 3,
304 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
305 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
308 #ifdef CONFIG_X86_NUMAQ
309 static void __init MP_translation_info (struct mpc_config_translation *m)
311 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
313 if (mpc_record >= MAX_MPC_ENTRY)
314 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
316 translation_table[mpc_record] = m; /* stash this for later */
317 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
318 node_set_online(m->trans_quad);
322 * Read/parse the MPC oem tables
325 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
326 unsigned short oemsize)
328 int count = sizeof (*oemtable); /* the header size */
329 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
332 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
333 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
335 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
336 oemtable->oem_signature[0],
337 oemtable->oem_signature[1],
338 oemtable->oem_signature[2],
339 oemtable->oem_signature[3]);
342 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
344 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
347 while (count < oemtable->oem_length) {
351 struct mpc_config_translation *m=
352 (struct mpc_config_translation *)oemptr;
353 MP_translation_info(m);
354 oemptr += sizeof(*m);
361 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
368 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
371 if (strncmp(oem, "IBM NUMA", 8))
372 printk("Warning! May not be a NUMA-Q system!\n");
374 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
377 #endif /* CONFIG_X86_NUMAQ */
383 static int __init smp_read_mpc(struct mp_config_table *mpc)
387 int count=sizeof(*mpc);
388 unsigned char *mpt=((unsigned char *)mpc)+count;
390 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
391 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
392 *(u32 *)mpc->mpc_signature);
395 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
396 printk(KERN_ERR "SMP mptable: checksum error!\n");
399 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
400 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
404 if (!mpc->mpc_lapic) {
405 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
408 memcpy(oem,mpc->mpc_oem,8);
410 printk(KERN_INFO "OEM ID: %s ",oem);
412 memcpy(str,mpc->mpc_productid,12);
414 printk("Product ID: %s ",str);
416 mps_oem_check(mpc, oem, str);
418 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
421 * Save the local APIC address (it might be non-default) -- but only
422 * if we're not using ACPI.
425 mp_lapic_addr = mpc->mpc_lapic;
428 * Now process the configuration blocks.
431 while (count < mpc->mpc_length) {
435 struct mpc_config_processor *m=
436 (struct mpc_config_processor *)mpt;
437 /* ACPI may have already provided this data */
439 MP_processor_info(m);
446 struct mpc_config_bus *m=
447 (struct mpc_config_bus *)mpt;
455 struct mpc_config_ioapic *m=
456 (struct mpc_config_ioapic *)mpt;
464 struct mpc_config_intsrc *m=
465 (struct mpc_config_intsrc *)mpt;
474 struct mpc_config_lintsrc *m=
475 (struct mpc_config_lintsrc *)mpt;
483 count = mpc->mpc_length;
489 setup_apic_routing();
491 printk(KERN_ERR "SMP mptable: no processors registered!\n");
492 return num_processors;
495 static int __init ELCR_trigger(unsigned int irq)
499 port = 0x4d0 + (irq >> 3);
500 return (inb(port) >> (irq & 7)) & 1;
503 static void __init construct_default_ioirq_mptable(int mpc_default_type)
505 struct mpc_config_intsrc intsrc;
507 int ELCR_fallback = 0;
509 intsrc.mpc_type = MP_INTSRC;
510 intsrc.mpc_irqflag = 0; /* conforming */
511 intsrc.mpc_srcbus = 0;
512 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
514 intsrc.mpc_irqtype = mp_INT;
517 * If true, we have an ISA/PCI system with no IRQ entries
518 * in the MP table. To prevent the PCI interrupts from being set up
519 * incorrectly, we try to use the ELCR. The sanity check to see if
520 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
521 * never be level sensitive, so we simply see if the ELCR agrees.
522 * If it does, we assume it's valid.
524 if (mpc_default_type == 5) {
525 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
527 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
528 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
530 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
535 for (i = 0; i < 16; i++) {
536 switch (mpc_default_type) {
538 if (i == 0 || i == 13)
539 continue; /* IRQ0 & IRQ13 not connected */
543 continue; /* IRQ2 is never connected */
548 * If the ELCR indicates a level-sensitive interrupt, we
549 * copy that information over to the MP table in the
550 * irqflag field (level sensitive, active high polarity).
553 intsrc.mpc_irqflag = 13;
555 intsrc.mpc_irqflag = 0;
558 intsrc.mpc_srcbusirq = i;
559 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
560 MP_intsrc_info(&intsrc);
563 intsrc.mpc_irqtype = mp_ExtINT;
564 intsrc.mpc_srcbusirq = 0;
565 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
566 MP_intsrc_info(&intsrc);
569 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
571 struct mpc_config_processor processor;
572 struct mpc_config_bus bus;
573 struct mpc_config_ioapic ioapic;
574 struct mpc_config_lintsrc lintsrc;
575 int linttypes[2] = { mp_ExtINT, mp_NMI };
579 * local APIC has default address
581 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
584 * 2 CPUs, numbered 0 & 1.
586 processor.mpc_type = MP_PROCESSOR;
587 /* Either an integrated APIC or a discrete 82489DX. */
588 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
589 processor.mpc_cpuflag = CPU_ENABLED;
590 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
591 (boot_cpu_data.x86_model << 4) |
592 boot_cpu_data.x86_mask;
593 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
594 processor.mpc_reserved[0] = 0;
595 processor.mpc_reserved[1] = 0;
596 for (i = 0; i < 2; i++) {
597 processor.mpc_apicid = i;
598 MP_processor_info(&processor);
601 bus.mpc_type = MP_BUS;
603 switch (mpc_default_type) {
606 printk(KERN_ERR "Unknown standard configuration %d\n",
611 memcpy(bus.mpc_bustype, "ISA ", 6);
616 memcpy(bus.mpc_bustype, "EISA ", 6);
620 memcpy(bus.mpc_bustype, "MCA ", 6);
623 if (mpc_default_type > 4) {
625 memcpy(bus.mpc_bustype, "PCI ", 6);
629 ioapic.mpc_type = MP_IOAPIC;
630 ioapic.mpc_apicid = 2;
631 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
632 ioapic.mpc_flags = MPC_APIC_USABLE;
633 ioapic.mpc_apicaddr = 0xFEC00000;
634 MP_ioapic_info(&ioapic);
637 * We set up most of the low 16 IO-APIC pins according to MPS rules.
639 construct_default_ioirq_mptable(mpc_default_type);
641 lintsrc.mpc_type = MP_LINTSRC;
642 lintsrc.mpc_irqflag = 0; /* conforming */
643 lintsrc.mpc_srcbusid = 0;
644 lintsrc.mpc_srcbusirq = 0;
645 lintsrc.mpc_destapic = MP_APIC_ALL;
646 for (i = 0; i < 2; i++) {
647 lintsrc.mpc_irqtype = linttypes[i];
648 lintsrc.mpc_destapiclint = i;
649 MP_lintsrc_info(&lintsrc);
653 static struct intel_mp_floating *mpf_found;
656 * Scan the memory blocks for an SMP configuration block.
658 void __init get_smp_config (void)
660 struct intel_mp_floating *mpf = mpf_found;
663 * ACPI supports both logical (e.g. Hyper-Threading) and physical
664 * processors, where MPS only supports physical.
666 if (acpi_lapic && acpi_ioapic) {
667 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
671 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
673 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
674 if (mpf->mpf_feature2 & (1<<7)) {
675 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
678 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
683 * Now see if we need to read further.
685 if (mpf->mpf_feature1 != 0) {
687 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
688 construct_default_ISA_mptable(mpf->mpf_feature1);
690 } else if (mpf->mpf_physptr) {
693 * Read the physical hardware table. Anything here will
694 * override the defaults.
696 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
697 smp_found_config = 0;
698 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
699 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
703 * If there are no explicit MP IRQ entries, then we are
704 * broken. We set up most of the low 16 IO-APIC pins to
705 * ISA defaults and hope it will work.
707 if (!mp_irq_entries) {
708 struct mpc_config_bus bus;
710 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
712 bus.mpc_type = MP_BUS;
714 memcpy(bus.mpc_bustype, "ISA ", 6);
717 construct_default_ioirq_mptable(0);
723 printk(KERN_INFO "Processors: %d\n", num_processors);
725 * Only use the first configuration found.
729 static int __init smp_scan_config (unsigned long base, unsigned long length)
731 unsigned long *bp = phys_to_virt(base);
732 struct intel_mp_floating *mpf;
734 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
735 if (sizeof(*mpf) != 16)
736 printk("Error: MPF size\n");
739 mpf = (struct intel_mp_floating *)bp;
740 if ((*bp == SMP_MAGIC_IDENT) &&
741 (mpf->mpf_length == 1) &&
742 !mpf_checksum((unsigned char *)bp, 16) &&
743 ((mpf->mpf_specification == 1)
744 || (mpf->mpf_specification == 4)) ) {
746 smp_found_config = 1;
747 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
748 mpf, virt_to_phys(mpf));
749 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
751 if (mpf->mpf_physptr) {
753 * We cannot access to MPC table to compute
754 * table size yet, as only few megabytes from
755 * the bottom is mapped now.
756 * PC-9800's MPC table places on the very last
757 * of physical memory; so that simply reserving
758 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
759 * in reserve_bootmem.
761 unsigned long size = PAGE_SIZE;
762 unsigned long end = max_low_pfn * PAGE_SIZE;
763 if (mpf->mpf_physptr + size > end)
764 size = end - mpf->mpf_physptr;
765 reserve_bootmem(mpf->mpf_physptr, size,
778 void __init find_smp_config (void)
780 unsigned int address;
783 * FIXME: Linux assumes you have 640K of base ram..
784 * this continues the error...
786 * 1) Scan the bottom 1K for a signature
787 * 2) Scan the top 1K of base RAM
788 * 3) Scan the 64K of bios
790 if (smp_scan_config(0x0,0x400) ||
791 smp_scan_config(639*0x400,0x400) ||
792 smp_scan_config(0xF0000,0x10000))
795 * If it is an SMP machine we should know now, unless the
796 * configuration is in an EISA/MCA bus machine with an
797 * extended bios data area.
799 * there is a real-mode segmented pointer pointing to the
800 * 4K EBDA area at 0x40E, calculate and scan it here.
802 * NOTE! There are Linux loaders that will corrupt the EBDA
803 * area, and as such this kind of SMP config may be less
804 * trustworthy, simply because the SMP table may have been
805 * stomped on during early boot. These loaders are buggy and
808 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
811 address = get_bios_ebda();
813 smp_scan_config(address, 0x400);
818 /* --------------------------------------------------------------------------
819 ACPI-based MP Configuration
820 -------------------------------------------------------------------------- */
824 void __init mp_register_lapic_address(u64 address)
826 mp_lapic_addr = (unsigned long) address;
828 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
830 if (boot_cpu_physical_apicid == -1U)
831 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
833 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
836 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
838 struct mpc_config_processor processor;
841 if (MAX_APICS - id <= 0) {
842 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
847 if (id == boot_cpu_physical_apicid)
850 processor.mpc_type = MP_PROCESSOR;
851 processor.mpc_apicid = id;
852 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
853 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
854 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
855 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
856 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
857 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
858 processor.mpc_reserved[0] = 0;
859 processor.mpc_reserved[1] = 0;
861 MP_processor_info(&processor);
864 #ifdef CONFIG_X86_IO_APIC
867 #define MP_MAX_IOAPIC_PIN 127
869 static struct mp_ioapic_routing {
873 u32 pin_programmed[4];
874 } mp_ioapic_routing[MAX_IO_APICS];
876 static int mp_find_ioapic (int gsi)
880 /* Find the IOAPIC that manages this GSI. */
881 for (i = 0; i < nr_ioapics; i++) {
882 if ((gsi >= mp_ioapic_routing[i].gsi_base)
883 && (gsi <= mp_ioapic_routing[i].gsi_end))
887 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
892 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
897 if (nr_ioapics >= MAX_IO_APICS) {
898 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
899 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
900 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
903 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
904 " found in MADT table, skipping!\n");
910 mp_ioapics[idx].mpc_type = MP_IOAPIC;
911 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
912 mp_ioapics[idx].mpc_apicaddr = address;
914 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
915 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
916 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
917 tmpid = io_apic_get_unique_id(idx, id);
924 mp_ioapics[idx].mpc_apicid = tmpid;
925 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
928 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
929 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
931 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
932 mp_ioapic_routing[idx].gsi_base = gsi_base;
933 mp_ioapic_routing[idx].gsi_end = gsi_base +
934 io_apic_get_redir_entries(idx);
936 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
937 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
938 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
939 mp_ioapic_routing[idx].gsi_base,
940 mp_ioapic_routing[idx].gsi_end);
944 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
946 struct mpc_config_intsrc intsrc;
951 * Convert 'gsi' to 'ioapic.pin'.
953 ioapic = mp_find_ioapic(gsi);
956 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
959 * TBD: This check is for faulty timer entries, where the override
960 * erroneously sets the trigger to level, resulting in a HUGE
961 * increase of timer interrupts!
963 if ((bus_irq == 0) && (trigger == 3))
966 intsrc.mpc_type = MP_INTSRC;
967 intsrc.mpc_irqtype = mp_INT;
968 intsrc.mpc_irqflag = (trigger << 2) | polarity;
969 intsrc.mpc_srcbus = MP_ISA_BUS;
970 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
971 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
972 intsrc.mpc_dstirq = pin; /* INTIN# */
974 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
975 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
976 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
977 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
979 mp_irqs[mp_irq_entries] = intsrc;
980 if (++mp_irq_entries == MAX_IRQ_SOURCES)
981 panic("Max # of irq sources exceeded!\n");
984 void __init mp_config_acpi_legacy_irqs (void)
986 struct mpc_config_intsrc intsrc;
990 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
992 * Fabricate the legacy ISA bus (bus #31).
994 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
996 set_bit(MP_ISA_BUS, mp_bus_not_pci);
997 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1000 * Older generations of ES7000 have no legacy identity mappings
1002 if (es7000_plat == 1)
1006 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1008 ioapic = mp_find_ioapic(0);
1012 intsrc.mpc_type = MP_INTSRC;
1013 intsrc.mpc_irqflag = 0; /* Conforming */
1014 intsrc.mpc_srcbus = MP_ISA_BUS;
1015 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1018 * Use the default configuration for the IRQs 0-15. Unless
1019 * overridden by (MADT) interrupt source override entries.
1021 for (i = 0; i < 16; i++) {
1024 for (idx = 0; idx < mp_irq_entries; idx++) {
1025 struct mpc_config_intsrc *irq = mp_irqs + idx;
1027 /* Do we already have a mapping for this ISA IRQ? */
1028 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1031 /* Do we already have a mapping for this IOAPIC pin */
1032 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1033 (irq->mpc_dstirq == i))
1037 if (idx != mp_irq_entries) {
1038 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1039 continue; /* IRQ already used */
1042 intsrc.mpc_irqtype = mp_INT;
1043 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1044 intsrc.mpc_dstirq = i;
1046 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1047 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1048 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1049 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1052 mp_irqs[mp_irq_entries] = intsrc;
1053 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1054 panic("Max # of irq sources exceeded!\n");
1058 #define MAX_GSI_NUM 4096
1059 #define IRQ_COMPRESSION_START 64
1061 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1066 static int pci_irq = IRQ_COMPRESSION_START;
1068 * Mapping between Global System Interrupts, which
1069 * represent all possible interrupts, and IRQs
1070 * assigned to actual devices.
1072 static int gsi_to_irq[MAX_GSI_NUM];
1074 /* Don't set up the ACPI SCI because it's already set up */
1075 if (acpi_gbl_FADT.sci_interrupt == gsi)
1078 ioapic = mp_find_ioapic(gsi);
1080 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1084 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1086 if (ioapic_renumber_irq)
1087 gsi = ioapic_renumber_irq(ioapic, gsi);
1090 * Avoid pin reprogramming. PRTs typically include entries
1091 * with redundant pin->gsi mappings (but unique PCI devices);
1092 * we only program the IOAPIC on the first.
1094 bit = ioapic_pin % 32;
1095 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1097 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1098 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1102 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1103 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1104 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1105 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1108 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1111 * For GSI >= 64, use IRQ compression
1113 if ((gsi >= IRQ_COMPRESSION_START)
1114 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1116 * For PCI devices assign IRQs in order, avoiding gaps
1117 * due to unused I/O APIC pins.
1120 if (gsi < MAX_GSI_NUM) {
1122 * Retain the VIA chipset work-around (gsi > 15), but
1123 * avoid a problem where the 8254 timer (IRQ0) is setup
1124 * via an override (so it's not on pin 0 of the ioapic),
1125 * and at the same time, the pin 0 interrupt is a PCI
1126 * type. The gsi > 15 test could cause these two pins
1127 * to be shared as IRQ0, and they are not shareable.
1128 * So test for this condition, and if necessary, avoid
1129 * the pin collision.
1131 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1134 * Don't assign IRQ used by ACPI SCI
1136 if (gsi == acpi_gbl_FADT.sci_interrupt)
1138 gsi_to_irq[irq] = gsi;
1140 printk(KERN_ERR "GSI %u is too high\n", gsi);
1145 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1146 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1147 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1151 #endif /* CONFIG_X86_IO_APIC */
1152 #endif /* CONFIG_ACPI */