2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
31 #include <mach_apic.h>
32 #include <mach_apicdef.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 int apic_version [MAX_APICS];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
48 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58 /* MP IRQ source entries */
64 unsigned long mp_lapic_addr;
66 unsigned int def_to_bigsmp = 0;
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 unsigned int num_processors;
73 unsigned disabled_cpus __cpuinitdata;
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
79 * Intel MP BIOS table parsing routines:
84 * Checksum an MP configuration block.
87 static int __init mpf_checksum(unsigned char *mp, int len)
98 * Have to match translation table entries to main table entries by counter
99 * hence the mpc_record variable .... can't see a less disgusting way of
103 static int mpc_record;
104 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
106 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
109 physid_mask_t phys_cpu;
111 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
116 apicid = mpc_apic_id(m, translation_table[mpc_record]);
118 if (m->mpc_featureflag&(1<<0))
119 Dprintk(" Floating point unit present.\n");
120 if (m->mpc_featureflag&(1<<7))
121 Dprintk(" Machine Exception supported.\n");
122 if (m->mpc_featureflag&(1<<8))
123 Dprintk(" 64 bit compare & exchange supported.\n");
124 if (m->mpc_featureflag&(1<<9))
125 Dprintk(" Internal APIC present.\n");
126 if (m->mpc_featureflag&(1<<11))
127 Dprintk(" SEP present.\n");
128 if (m->mpc_featureflag&(1<<12))
129 Dprintk(" MTRR present.\n");
130 if (m->mpc_featureflag&(1<<13))
131 Dprintk(" PGE present.\n");
132 if (m->mpc_featureflag&(1<<14))
133 Dprintk(" MCA present.\n");
134 if (m->mpc_featureflag&(1<<15))
135 Dprintk(" CMOV present.\n");
136 if (m->mpc_featureflag&(1<<16))
137 Dprintk(" PAT present.\n");
138 if (m->mpc_featureflag&(1<<17))
139 Dprintk(" PSE present.\n");
140 if (m->mpc_featureflag&(1<<18))
141 Dprintk(" PSN present.\n");
142 if (m->mpc_featureflag&(1<<19))
143 Dprintk(" Cache Line Flush Instruction present.\n");
145 if (m->mpc_featureflag&(1<<21))
146 Dprintk(" Debug Trace and EMON Store present.\n");
147 if (m->mpc_featureflag&(1<<22))
148 Dprintk(" ACPI Thermal Throttle Registers present.\n");
149 if (m->mpc_featureflag&(1<<23))
150 Dprintk(" MMX present.\n");
151 if (m->mpc_featureflag&(1<<24))
152 Dprintk(" FXSR present.\n");
153 if (m->mpc_featureflag&(1<<25))
154 Dprintk(" XMM present.\n");
155 if (m->mpc_featureflag&(1<<26))
156 Dprintk(" Willamette New Instructions present.\n");
157 if (m->mpc_featureflag&(1<<27))
158 Dprintk(" Self Snoop present.\n");
159 if (m->mpc_featureflag&(1<<28))
160 Dprintk(" HT present.\n");
161 if (m->mpc_featureflag&(1<<29))
162 Dprintk(" Thermal Monitor present.\n");
163 /* 30, 31 Reserved */
166 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
167 Dprintk(" Bootup CPU\n");
168 boot_cpu_physical_apicid = m->mpc_apicid;
171 ver = m->mpc_apicver;
177 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
178 "fixing up to 0x10. (tell your hw vendor)\n",
182 apic_version[m->mpc_apicid] = ver;
184 phys_cpu = apicid_to_cpu_present(apicid);
185 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
187 if (num_processors >= NR_CPUS) {
188 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
189 " Processor ignored.\n", NR_CPUS);
193 if (num_processors >= maxcpus) {
194 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
195 " Processor ignored.\n", maxcpus);
199 cpu_set(num_processors, cpu_possible_map);
203 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
204 * but we need to work other dependencies like SMP_SUSPEND etc
205 * before this can be done without some confusion.
206 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
207 * - Ashok Raj <ashok.raj@intel.com>
209 if (num_processors > 8) {
210 switch (boot_cpu_data.x86_vendor) {
211 case X86_VENDOR_INTEL:
212 if (!APIC_XAPIC(ver)) {
216 /* If P4 and above fall through */
221 /* are we being called early in kernel startup? */
222 if (x86_cpu_to_apicid_early_ptr) {
223 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
224 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
226 int cpu = num_processors - 1;
227 per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid;
231 static void __init MP_bus_info (struct mpc_config_bus *m)
235 memcpy(str, m->mpc_bustype, 6);
238 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
240 #if MAX_MP_BUSSES < 256
241 if (m->mpc_busid >= MAX_MP_BUSSES) {
242 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
243 " is too large, max. supported is %d\n",
244 m->mpc_busid, str, MAX_MP_BUSSES - 1);
249 set_bit(m->mpc_busid, mp_bus_not_pci);
250 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
251 mpc_oem_pci_bus(m, translation_table[mpc_record]);
252 clear_bit(m->mpc_busid, mp_bus_not_pci);
253 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
255 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
256 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
257 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
258 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
259 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
260 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
261 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
262 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
264 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
269 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
271 if (!(m->mpc_flags & MPC_APIC_USABLE))
274 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
275 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
276 if (nr_ioapics >= MAX_IO_APICS) {
277 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
278 MAX_IO_APICS, nr_ioapics);
279 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
281 if (!m->mpc_apicaddr) {
282 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
283 " found in MP table, skipping!\n");
286 mp_ioapics[nr_ioapics] = *m;
290 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
292 mp_irqs [mp_irq_entries] = *m;
293 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
294 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
295 m->mpc_irqtype, m->mpc_irqflag & 3,
296 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
297 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
298 if (++mp_irq_entries == MAX_IRQ_SOURCES)
299 panic("Max # of irq sources exceeded!!\n");
302 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
304 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
305 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
306 m->mpc_irqtype, m->mpc_irqflag & 3,
307 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
308 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
311 #ifdef CONFIG_X86_NUMAQ
312 static void __init MP_translation_info (struct mpc_config_translation *m)
314 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
316 if (mpc_record >= MAX_MPC_ENTRY)
317 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
319 translation_table[mpc_record] = m; /* stash this for later */
320 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
321 node_set_online(m->trans_quad);
325 * Read/parse the MPC oem tables
328 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
329 unsigned short oemsize)
331 int count = sizeof (*oemtable); /* the header size */
332 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
335 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
336 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
338 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
339 oemtable->oem_signature[0],
340 oemtable->oem_signature[1],
341 oemtable->oem_signature[2],
342 oemtable->oem_signature[3]);
345 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
347 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
350 while (count < oemtable->oem_length) {
354 struct mpc_config_translation *m=
355 (struct mpc_config_translation *)oemptr;
356 MP_translation_info(m);
357 oemptr += sizeof(*m);
364 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
371 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
374 if (strncmp(oem, "IBM NUMA", 8))
375 printk("Warning! May not be a NUMA-Q system!\n");
377 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
380 #endif /* CONFIG_X86_NUMAQ */
386 static int __init smp_read_mpc(struct mp_config_table *mpc)
390 int count=sizeof(*mpc);
391 unsigned char *mpt=((unsigned char *)mpc)+count;
393 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
394 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
395 *(u32 *)mpc->mpc_signature);
398 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
399 printk(KERN_ERR "SMP mptable: checksum error!\n");
402 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
403 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
407 if (!mpc->mpc_lapic) {
408 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
411 memcpy(oem,mpc->mpc_oem,8);
413 printk(KERN_INFO "OEM ID: %s ",oem);
415 memcpy(str,mpc->mpc_productid,12);
417 printk("Product ID: %s ",str);
419 mps_oem_check(mpc, oem, str);
421 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
424 * Save the local APIC address (it might be non-default) -- but only
425 * if we're not using ACPI.
428 mp_lapic_addr = mpc->mpc_lapic;
431 * Now process the configuration blocks.
434 while (count < mpc->mpc_length) {
438 struct mpc_config_processor *m=
439 (struct mpc_config_processor *)mpt;
440 /* ACPI may have already provided this data */
442 MP_processor_info(m);
449 struct mpc_config_bus *m=
450 (struct mpc_config_bus *)mpt;
458 struct mpc_config_ioapic *m=
459 (struct mpc_config_ioapic *)mpt;
467 struct mpc_config_intsrc *m=
468 (struct mpc_config_intsrc *)mpt;
477 struct mpc_config_lintsrc *m=
478 (struct mpc_config_lintsrc *)mpt;
486 count = mpc->mpc_length;
492 setup_apic_routing();
494 printk(KERN_ERR "SMP mptable: no processors registered!\n");
495 return num_processors;
498 static int __init ELCR_trigger(unsigned int irq)
502 port = 0x4d0 + (irq >> 3);
503 return (inb(port) >> (irq & 7)) & 1;
506 static void __init construct_default_ioirq_mptable(int mpc_default_type)
508 struct mpc_config_intsrc intsrc;
510 int ELCR_fallback = 0;
512 intsrc.mpc_type = MP_INTSRC;
513 intsrc.mpc_irqflag = 0; /* conforming */
514 intsrc.mpc_srcbus = 0;
515 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
517 intsrc.mpc_irqtype = mp_INT;
520 * If true, we have an ISA/PCI system with no IRQ entries
521 * in the MP table. To prevent the PCI interrupts from being set up
522 * incorrectly, we try to use the ELCR. The sanity check to see if
523 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
524 * never be level sensitive, so we simply see if the ELCR agrees.
525 * If it does, we assume it's valid.
527 if (mpc_default_type == 5) {
528 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
530 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
531 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
533 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
538 for (i = 0; i < 16; i++) {
539 switch (mpc_default_type) {
541 if (i == 0 || i == 13)
542 continue; /* IRQ0 & IRQ13 not connected */
546 continue; /* IRQ2 is never connected */
551 * If the ELCR indicates a level-sensitive interrupt, we
552 * copy that information over to the MP table in the
553 * irqflag field (level sensitive, active high polarity).
556 intsrc.mpc_irqflag = 13;
558 intsrc.mpc_irqflag = 0;
561 intsrc.mpc_srcbusirq = i;
562 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
563 MP_intsrc_info(&intsrc);
566 intsrc.mpc_irqtype = mp_ExtINT;
567 intsrc.mpc_srcbusirq = 0;
568 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
569 MP_intsrc_info(&intsrc);
572 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
574 struct mpc_config_processor processor;
575 struct mpc_config_bus bus;
576 struct mpc_config_ioapic ioapic;
577 struct mpc_config_lintsrc lintsrc;
578 int linttypes[2] = { mp_ExtINT, mp_NMI };
582 * local APIC has default address
584 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
587 * 2 CPUs, numbered 0 & 1.
589 processor.mpc_type = MP_PROCESSOR;
590 /* Either an integrated APIC or a discrete 82489DX. */
591 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
592 processor.mpc_cpuflag = CPU_ENABLED;
593 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
594 (boot_cpu_data.x86_model << 4) |
595 boot_cpu_data.x86_mask;
596 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
597 processor.mpc_reserved[0] = 0;
598 processor.mpc_reserved[1] = 0;
599 for (i = 0; i < 2; i++) {
600 processor.mpc_apicid = i;
601 MP_processor_info(&processor);
604 bus.mpc_type = MP_BUS;
606 switch (mpc_default_type) {
609 printk(KERN_ERR "Unknown standard configuration %d\n",
614 memcpy(bus.mpc_bustype, "ISA ", 6);
619 memcpy(bus.mpc_bustype, "EISA ", 6);
623 memcpy(bus.mpc_bustype, "MCA ", 6);
626 if (mpc_default_type > 4) {
628 memcpy(bus.mpc_bustype, "PCI ", 6);
632 ioapic.mpc_type = MP_IOAPIC;
633 ioapic.mpc_apicid = 2;
634 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
635 ioapic.mpc_flags = MPC_APIC_USABLE;
636 ioapic.mpc_apicaddr = 0xFEC00000;
637 MP_ioapic_info(&ioapic);
640 * We set up most of the low 16 IO-APIC pins according to MPS rules.
642 construct_default_ioirq_mptable(mpc_default_type);
644 lintsrc.mpc_type = MP_LINTSRC;
645 lintsrc.mpc_irqflag = 0; /* conforming */
646 lintsrc.mpc_srcbusid = 0;
647 lintsrc.mpc_srcbusirq = 0;
648 lintsrc.mpc_destapic = MP_APIC_ALL;
649 for (i = 0; i < 2; i++) {
650 lintsrc.mpc_irqtype = linttypes[i];
651 lintsrc.mpc_destapiclint = i;
652 MP_lintsrc_info(&lintsrc);
656 static struct intel_mp_floating *mpf_found;
659 * Scan the memory blocks for an SMP configuration block.
661 void __init get_smp_config (void)
663 struct intel_mp_floating *mpf = mpf_found;
666 * ACPI supports both logical (e.g. Hyper-Threading) and physical
667 * processors, where MPS only supports physical.
669 if (acpi_lapic && acpi_ioapic) {
670 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
674 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
676 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
677 if (mpf->mpf_feature2 & (1<<7)) {
678 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
681 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
686 * Now see if we need to read further.
688 if (mpf->mpf_feature1 != 0) {
690 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
691 construct_default_ISA_mptable(mpf->mpf_feature1);
693 } else if (mpf->mpf_physptr) {
696 * Read the physical hardware table. Anything here will
697 * override the defaults.
699 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
700 smp_found_config = 0;
701 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
702 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
706 * If there are no explicit MP IRQ entries, then we are
707 * broken. We set up most of the low 16 IO-APIC pins to
708 * ISA defaults and hope it will work.
710 if (!mp_irq_entries) {
711 struct mpc_config_bus bus;
713 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
715 bus.mpc_type = MP_BUS;
717 memcpy(bus.mpc_bustype, "ISA ", 6);
720 construct_default_ioirq_mptable(0);
726 printk(KERN_INFO "Processors: %d\n", num_processors);
728 * Only use the first configuration found.
732 static int __init smp_scan_config (unsigned long base, unsigned long length)
734 unsigned long *bp = phys_to_virt(base);
735 struct intel_mp_floating *mpf;
737 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
738 if (sizeof(*mpf) != 16)
739 printk("Error: MPF size\n");
742 mpf = (struct intel_mp_floating *)bp;
743 if ((*bp == SMP_MAGIC_IDENT) &&
744 (mpf->mpf_length == 1) &&
745 !mpf_checksum((unsigned char *)bp, 16) &&
746 ((mpf->mpf_specification == 1)
747 || (mpf->mpf_specification == 4)) ) {
749 smp_found_config = 1;
750 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
751 mpf, virt_to_phys(mpf));
752 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
754 if (mpf->mpf_physptr) {
756 * We cannot access to MPC table to compute
757 * table size yet, as only few megabytes from
758 * the bottom is mapped now.
759 * PC-9800's MPC table places on the very last
760 * of physical memory; so that simply reserving
761 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
762 * in reserve_bootmem.
764 unsigned long size = PAGE_SIZE;
765 unsigned long end = max_low_pfn * PAGE_SIZE;
766 if (mpf->mpf_physptr + size > end)
767 size = end - mpf->mpf_physptr;
768 reserve_bootmem(mpf->mpf_physptr, size,
781 void __init find_smp_config (void)
783 unsigned int address;
786 * FIXME: Linux assumes you have 640K of base ram..
787 * this continues the error...
789 * 1) Scan the bottom 1K for a signature
790 * 2) Scan the top 1K of base RAM
791 * 3) Scan the 64K of bios
793 if (smp_scan_config(0x0,0x400) ||
794 smp_scan_config(639*0x400,0x400) ||
795 smp_scan_config(0xF0000,0x10000))
798 * If it is an SMP machine we should know now, unless the
799 * configuration is in an EISA/MCA bus machine with an
800 * extended bios data area.
802 * there is a real-mode segmented pointer pointing to the
803 * 4K EBDA area at 0x40E, calculate and scan it here.
805 * NOTE! There are Linux loaders that will corrupt the EBDA
806 * area, and as such this kind of SMP config may be less
807 * trustworthy, simply because the SMP table may have been
808 * stomped on during early boot. These loaders are buggy and
811 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
814 address = get_bios_ebda();
816 smp_scan_config(address, 0x400);
821 /* --------------------------------------------------------------------------
822 ACPI-based MP Configuration
823 -------------------------------------------------------------------------- */
827 void __init mp_register_lapic_address(u64 address)
829 mp_lapic_addr = (unsigned long) address;
831 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
833 if (boot_cpu_physical_apicid == -1U)
834 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
836 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
839 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
841 struct mpc_config_processor processor;
844 if (MAX_APICS - id <= 0) {
845 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
850 if (id == boot_cpu_physical_apicid)
853 processor.mpc_type = MP_PROCESSOR;
854 processor.mpc_apicid = id;
855 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
856 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
857 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
858 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
859 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
860 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
861 processor.mpc_reserved[0] = 0;
862 processor.mpc_reserved[1] = 0;
864 MP_processor_info(&processor);
867 #ifdef CONFIG_X86_IO_APIC
870 #define MP_MAX_IOAPIC_PIN 127
872 static struct mp_ioapic_routing {
876 u32 pin_programmed[4];
877 } mp_ioapic_routing[MAX_IO_APICS];
879 static int mp_find_ioapic (int gsi)
883 /* Find the IOAPIC that manages this GSI. */
884 for (i = 0; i < nr_ioapics; i++) {
885 if ((gsi >= mp_ioapic_routing[i].gsi_base)
886 && (gsi <= mp_ioapic_routing[i].gsi_end))
890 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
895 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
900 if (nr_ioapics >= MAX_IO_APICS) {
901 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
902 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
903 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
906 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
907 " found in MADT table, skipping!\n");
913 mp_ioapics[idx].mpc_type = MP_IOAPIC;
914 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
915 mp_ioapics[idx].mpc_apicaddr = address;
917 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
918 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
919 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
920 tmpid = io_apic_get_unique_id(idx, id);
927 mp_ioapics[idx].mpc_apicid = tmpid;
928 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
931 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
932 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
934 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
935 mp_ioapic_routing[idx].gsi_base = gsi_base;
936 mp_ioapic_routing[idx].gsi_end = gsi_base +
937 io_apic_get_redir_entries(idx);
939 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
940 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
941 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
942 mp_ioapic_routing[idx].gsi_base,
943 mp_ioapic_routing[idx].gsi_end);
947 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
949 struct mpc_config_intsrc intsrc;
954 * Convert 'gsi' to 'ioapic.pin'.
956 ioapic = mp_find_ioapic(gsi);
959 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
962 * TBD: This check is for faulty timer entries, where the override
963 * erroneously sets the trigger to level, resulting in a HUGE
964 * increase of timer interrupts!
966 if ((bus_irq == 0) && (trigger == 3))
969 intsrc.mpc_type = MP_INTSRC;
970 intsrc.mpc_irqtype = mp_INT;
971 intsrc.mpc_irqflag = (trigger << 2) | polarity;
972 intsrc.mpc_srcbus = MP_ISA_BUS;
973 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
974 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
975 intsrc.mpc_dstirq = pin; /* INTIN# */
977 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
978 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
979 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
980 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
982 mp_irqs[mp_irq_entries] = intsrc;
983 if (++mp_irq_entries == MAX_IRQ_SOURCES)
984 panic("Max # of irq sources exceeded!\n");
987 void __init mp_config_acpi_legacy_irqs (void)
989 struct mpc_config_intsrc intsrc;
993 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
995 * Fabricate the legacy ISA bus (bus #31).
997 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
999 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1000 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1003 * Older generations of ES7000 have no legacy identity mappings
1005 if (es7000_plat == 1)
1009 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1011 ioapic = mp_find_ioapic(0);
1015 intsrc.mpc_type = MP_INTSRC;
1016 intsrc.mpc_irqflag = 0; /* Conforming */
1017 intsrc.mpc_srcbus = MP_ISA_BUS;
1018 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1021 * Use the default configuration for the IRQs 0-15. Unless
1022 * overridden by (MADT) interrupt source override entries.
1024 for (i = 0; i < 16; i++) {
1027 for (idx = 0; idx < mp_irq_entries; idx++) {
1028 struct mpc_config_intsrc *irq = mp_irqs + idx;
1030 /* Do we already have a mapping for this ISA IRQ? */
1031 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1034 /* Do we already have a mapping for this IOAPIC pin */
1035 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1036 (irq->mpc_dstirq == i))
1040 if (idx != mp_irq_entries) {
1041 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1042 continue; /* IRQ already used */
1045 intsrc.mpc_irqtype = mp_INT;
1046 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1047 intsrc.mpc_dstirq = i;
1049 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1050 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1051 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1052 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1055 mp_irqs[mp_irq_entries] = intsrc;
1056 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1057 panic("Max # of irq sources exceeded!\n");
1061 #define MAX_GSI_NUM 4096
1062 #define IRQ_COMPRESSION_START 64
1064 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1069 static int pci_irq = IRQ_COMPRESSION_START;
1071 * Mapping between Global System Interrupts, which
1072 * represent all possible interrupts, and IRQs
1073 * assigned to actual devices.
1075 static int gsi_to_irq[MAX_GSI_NUM];
1077 /* Don't set up the ACPI SCI because it's already set up */
1078 if (acpi_gbl_FADT.sci_interrupt == gsi)
1081 ioapic = mp_find_ioapic(gsi);
1083 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1087 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1089 if (ioapic_renumber_irq)
1090 gsi = ioapic_renumber_irq(ioapic, gsi);
1093 * Avoid pin reprogramming. PRTs typically include entries
1094 * with redundant pin->gsi mappings (but unique PCI devices);
1095 * we only program the IOAPIC on the first.
1097 bit = ioapic_pin % 32;
1098 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1100 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1101 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1105 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1106 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1107 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1108 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1111 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1114 * For GSI >= 64, use IRQ compression
1116 if ((gsi >= IRQ_COMPRESSION_START)
1117 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1119 * For PCI devices assign IRQs in order, avoiding gaps
1120 * due to unused I/O APIC pins.
1123 if (gsi < MAX_GSI_NUM) {
1125 * Retain the VIA chipset work-around (gsi > 15), but
1126 * avoid a problem where the 8254 timer (IRQ0) is setup
1127 * via an override (so it's not on pin 0 of the ioapic),
1128 * and at the same time, the pin 0 interrupt is a PCI
1129 * type. The gsi > 15 test could cause these two pins
1130 * to be shared as IRQ0, and they are not shareable.
1131 * So test for this condition, and if necessary, avoid
1132 * the pin collision.
1134 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1137 * Don't assign IRQ used by ACPI SCI
1139 if (gsi == acpi_gbl_FADT.sci_interrupt)
1141 gsi_to_irq[irq] = gsi;
1143 printk(KERN_ERR "GSI %u is too high\n", gsi);
1148 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1149 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1150 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1154 #endif /* CONFIG_X86_IO_APIC */
1155 #endif /* CONFIG_ACPI */