2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
36 /* Have we found an MP table */
40 * Various Linux-internal data structures created from the
43 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
44 int mp_bus_id_to_type [MAX_MP_BUSSES];
46 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
47 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48 static int mp_current_pci_id;
50 /* I/O APIC entries */
51 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53 /* # of MP IRQ source entries */
54 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56 /* MP IRQ source entries */
63 /* Make it easy to share the UP and SMP code: */
64 #ifndef CONFIG_X86_SMP
65 unsigned int num_processors;
66 unsigned disabled_cpus __cpuinitdata;
67 #ifndef CONFIG_X86_LOCAL_APIC
68 unsigned int boot_cpu_physical_apicid = -1U;
72 /* Make it easy to share the UP and SMP code: */
73 #ifndef CONFIG_X86_SMP
74 physid_mask_t phys_cpu_present_map;
78 * Intel MP BIOS table parsing routines:
83 * Checksum an MP configuration block.
86 static int __init mpf_checksum(unsigned char *mp, int len)
96 #ifdef CONFIG_X86_NUMAQ
98 * Have to match translation table entries to main table entries by counter
99 * hence the mpc_record variable .... can't see a less disgusting way of
103 static int mpc_record;
104 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
107 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
111 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
112 #ifdef CONFIG_X86_SMP
118 #ifdef CONFIG_X86_NUMAQ
119 apicid = mpc_apic_id(m, translation_table[mpc_record]);
121 Dprintk("Processor #%d %u:%u APIC version %d\n",
123 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
124 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
126 apicid = m->mpc_apicid;
129 if (m->mpc_featureflag&(1<<0))
130 Dprintk(" Floating point unit present.\n");
131 if (m->mpc_featureflag&(1<<7))
132 Dprintk(" Machine Exception supported.\n");
133 if (m->mpc_featureflag&(1<<8))
134 Dprintk(" 64 bit compare & exchange supported.\n");
135 if (m->mpc_featureflag&(1<<9))
136 Dprintk(" Internal APIC present.\n");
137 if (m->mpc_featureflag&(1<<11))
138 Dprintk(" SEP present.\n");
139 if (m->mpc_featureflag&(1<<12))
140 Dprintk(" MTRR present.\n");
141 if (m->mpc_featureflag&(1<<13))
142 Dprintk(" PGE present.\n");
143 if (m->mpc_featureflag&(1<<14))
144 Dprintk(" MCA present.\n");
145 if (m->mpc_featureflag&(1<<15))
146 Dprintk(" CMOV present.\n");
147 if (m->mpc_featureflag&(1<<16))
148 Dprintk(" PAT present.\n");
149 if (m->mpc_featureflag&(1<<17))
150 Dprintk(" PSE present.\n");
151 if (m->mpc_featureflag&(1<<18))
152 Dprintk(" PSN present.\n");
153 if (m->mpc_featureflag&(1<<19))
154 Dprintk(" Cache Line Flush Instruction present.\n");
156 if (m->mpc_featureflag&(1<<21))
157 Dprintk(" Debug Trace and EMON Store present.\n");
158 if (m->mpc_featureflag&(1<<22))
159 Dprintk(" ACPI Thermal Throttle Registers present.\n");
160 if (m->mpc_featureflag&(1<<23))
161 Dprintk(" MMX present.\n");
162 if (m->mpc_featureflag&(1<<24))
163 Dprintk(" FXSR present.\n");
164 if (m->mpc_featureflag&(1<<25))
165 Dprintk(" XMM present.\n");
166 if (m->mpc_featureflag&(1<<26))
167 Dprintk(" Willamette New Instructions present.\n");
168 if (m->mpc_featureflag&(1<<27))
169 Dprintk(" Self Snoop present.\n");
170 if (m->mpc_featureflag&(1<<28))
171 Dprintk(" HT present.\n");
172 if (m->mpc_featureflag&(1<<29))
173 Dprintk(" Thermal Monitor present.\n");
174 /* 30, 31 Reserved */
177 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
178 Dprintk(" Bootup CPU\n");
179 boot_cpu_physical_apicid = m->mpc_apicid;
182 generic_processor_info(apicid, m->mpc_apicver);
185 static void __init MP_bus_info (struct mpc_config_bus *m)
189 memcpy(str, m->mpc_bustype, 6);
192 #ifdef CONFIG_X86_NUMAQ
193 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
195 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
198 #if MAX_MP_BUSSES < 256
199 if (m->mpc_busid >= MAX_MP_BUSSES) {
200 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
201 " is too large, max. supported is %d\n",
202 m->mpc_busid, str, MAX_MP_BUSSES - 1);
207 set_bit(m->mpc_busid, mp_bus_not_pci);
208 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
209 #ifdef CONFIG_X86_NUMAQ
210 mpc_oem_pci_bus(m, translation_table[mpc_record]);
212 clear_bit(m->mpc_busid, mp_bus_not_pci);
213 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
215 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
216 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
217 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
218 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
219 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
220 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
221 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
222 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
224 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
229 static int bad_ioapic(unsigned long address)
231 if (nr_ioapics >= MAX_IO_APICS) {
232 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
233 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
234 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
237 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
238 " found in table, skipping!\n");
244 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
246 if (!(m->mpc_flags & MPC_APIC_USABLE))
249 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
250 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
252 if (bad_ioapic(m->mpc_apicaddr))
255 mp_ioapics[nr_ioapics] = *m;
259 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
261 mp_irqs [mp_irq_entries] = *m;
262 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
263 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
264 m->mpc_irqtype, m->mpc_irqflag & 3,
265 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
266 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
267 if (++mp_irq_entries == MAX_IRQ_SOURCES)
268 panic("Max # of irq sources exceeded!!\n");
271 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
273 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
274 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
275 m->mpc_irqtype, m->mpc_irqflag & 3,
276 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
277 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
280 #ifdef CONFIG_X86_NUMAQ
281 static void __init MP_translation_info (struct mpc_config_translation *m)
283 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
285 if (mpc_record >= MAX_MPC_ENTRY)
286 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
288 translation_table[mpc_record] = m; /* stash this for later */
289 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
290 node_set_online(m->trans_quad);
294 * Read/parse the MPC oem tables
297 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
298 unsigned short oemsize)
300 int count = sizeof (*oemtable); /* the header size */
301 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
304 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
305 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
307 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
308 oemtable->oem_signature[0],
309 oemtable->oem_signature[1],
310 oemtable->oem_signature[2],
311 oemtable->oem_signature[3]);
314 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
316 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
319 while (count < oemtable->oem_length) {
323 struct mpc_config_translation *m=
324 (struct mpc_config_translation *)oemptr;
325 MP_translation_info(m);
326 oemptr += sizeof(*m);
333 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
340 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
343 if (strncmp(oem, "IBM NUMA", 8))
344 printk("Warning! May not be a NUMA-Q system!\n");
346 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
349 #endif /* CONFIG_X86_NUMAQ */
355 static int __init smp_read_mpc(struct mp_config_table *mpc)
359 int count=sizeof(*mpc);
360 unsigned char *mpt=((unsigned char *)mpc)+count;
362 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
363 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
364 *(u32 *)mpc->mpc_signature);
367 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
368 printk(KERN_ERR "SMP mptable: checksum error!\n");
371 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
372 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
376 if (!mpc->mpc_lapic) {
377 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
380 memcpy(oem,mpc->mpc_oem,8);
382 printk(KERN_INFO "OEM ID: %s ",oem);
384 memcpy(str,mpc->mpc_productid,12);
386 printk("Product ID: %s ",str);
388 mps_oem_check(mpc, oem, str);
390 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
393 * Save the local APIC address (it might be non-default) -- but only
394 * if we're not using ACPI.
397 mp_lapic_addr = mpc->mpc_lapic;
400 * Now process the configuration blocks.
402 #ifdef CONFIG_X86_NUMAQ
405 while (count < mpc->mpc_length) {
409 struct mpc_config_processor *m=
410 (struct mpc_config_processor *)mpt;
411 /* ACPI may have already provided this data */
413 MP_processor_info(m);
420 struct mpc_config_bus *m=
421 (struct mpc_config_bus *)mpt;
429 struct mpc_config_ioapic *m=
430 (struct mpc_config_ioapic *)mpt;
438 struct mpc_config_intsrc *m=
439 (struct mpc_config_intsrc *)mpt;
448 struct mpc_config_lintsrc *m=
449 (struct mpc_config_lintsrc *)mpt;
457 count = mpc->mpc_length;
461 #ifdef CONFIG_X86_NUMAQ
465 setup_apic_routing();
467 printk(KERN_ERR "SMP mptable: no processors registered!\n");
468 return num_processors;
471 static int __init ELCR_trigger(unsigned int irq)
475 port = 0x4d0 + (irq >> 3);
476 return (inb(port) >> (irq & 7)) & 1;
479 static void __init construct_default_ioirq_mptable(int mpc_default_type)
481 struct mpc_config_intsrc intsrc;
483 int ELCR_fallback = 0;
485 intsrc.mpc_type = MP_INTSRC;
486 intsrc.mpc_irqflag = 0; /* conforming */
487 intsrc.mpc_srcbus = 0;
488 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
490 intsrc.mpc_irqtype = mp_INT;
493 * If true, we have an ISA/PCI system with no IRQ entries
494 * in the MP table. To prevent the PCI interrupts from being set up
495 * incorrectly, we try to use the ELCR. The sanity check to see if
496 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
497 * never be level sensitive, so we simply see if the ELCR agrees.
498 * If it does, we assume it's valid.
500 if (mpc_default_type == 5) {
501 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
503 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
504 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
506 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
511 for (i = 0; i < 16; i++) {
512 switch (mpc_default_type) {
514 if (i == 0 || i == 13)
515 continue; /* IRQ0 & IRQ13 not connected */
519 continue; /* IRQ2 is never connected */
524 * If the ELCR indicates a level-sensitive interrupt, we
525 * copy that information over to the MP table in the
526 * irqflag field (level sensitive, active high polarity).
529 intsrc.mpc_irqflag = 13;
531 intsrc.mpc_irqflag = 0;
534 intsrc.mpc_srcbusirq = i;
535 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
536 MP_intsrc_info(&intsrc);
539 intsrc.mpc_irqtype = mp_ExtINT;
540 intsrc.mpc_srcbusirq = 0;
541 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
542 MP_intsrc_info(&intsrc);
545 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
547 struct mpc_config_processor processor;
548 struct mpc_config_bus bus;
549 struct mpc_config_ioapic ioapic;
550 struct mpc_config_lintsrc lintsrc;
551 int linttypes[2] = { mp_ExtINT, mp_NMI };
555 * local APIC has default address
557 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
560 * 2 CPUs, numbered 0 & 1.
562 processor.mpc_type = MP_PROCESSOR;
563 /* Either an integrated APIC or a discrete 82489DX. */
564 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
565 processor.mpc_cpuflag = CPU_ENABLED;
566 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
567 (boot_cpu_data.x86_model << 4) |
568 boot_cpu_data.x86_mask;
569 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
570 processor.mpc_reserved[0] = 0;
571 processor.mpc_reserved[1] = 0;
572 for (i = 0; i < 2; i++) {
573 processor.mpc_apicid = i;
574 MP_processor_info(&processor);
577 bus.mpc_type = MP_BUS;
579 switch (mpc_default_type) {
582 printk(KERN_ERR "Unknown standard configuration %d\n",
587 memcpy(bus.mpc_bustype, "ISA ", 6);
592 memcpy(bus.mpc_bustype, "EISA ", 6);
596 memcpy(bus.mpc_bustype, "MCA ", 6);
599 if (mpc_default_type > 4) {
601 memcpy(bus.mpc_bustype, "PCI ", 6);
605 ioapic.mpc_type = MP_IOAPIC;
606 ioapic.mpc_apicid = 2;
607 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
608 ioapic.mpc_flags = MPC_APIC_USABLE;
609 ioapic.mpc_apicaddr = 0xFEC00000;
610 MP_ioapic_info(&ioapic);
613 * We set up most of the low 16 IO-APIC pins according to MPS rules.
615 construct_default_ioirq_mptable(mpc_default_type);
617 lintsrc.mpc_type = MP_LINTSRC;
618 lintsrc.mpc_irqflag = 0; /* conforming */
619 lintsrc.mpc_srcbusid = 0;
620 lintsrc.mpc_srcbusirq = 0;
621 lintsrc.mpc_destapic = MP_APIC_ALL;
622 for (i = 0; i < 2; i++) {
623 lintsrc.mpc_irqtype = linttypes[i];
624 lintsrc.mpc_destapiclint = i;
625 MP_lintsrc_info(&lintsrc);
629 static struct intel_mp_floating *mpf_found;
632 * Scan the memory blocks for an SMP configuration block.
634 void __init get_smp_config (void)
636 struct intel_mp_floating *mpf = mpf_found;
639 * ACPI supports both logical (e.g. Hyper-Threading) and physical
640 * processors, where MPS only supports physical.
642 if (acpi_lapic && acpi_ioapic) {
643 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
647 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
649 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
650 if (mpf->mpf_feature2 & (1<<7)) {
651 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
654 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
659 * Now see if we need to read further.
661 if (mpf->mpf_feature1 != 0) {
663 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
664 construct_default_ISA_mptable(mpf->mpf_feature1);
666 } else if (mpf->mpf_physptr) {
669 * Read the physical hardware table. Anything here will
670 * override the defaults.
672 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
673 smp_found_config = 0;
674 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
675 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
679 * If there are no explicit MP IRQ entries, then we are
680 * broken. We set up most of the low 16 IO-APIC pins to
681 * ISA defaults and hope it will work.
683 if (!mp_irq_entries) {
684 struct mpc_config_bus bus;
686 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
688 bus.mpc_type = MP_BUS;
690 memcpy(bus.mpc_bustype, "ISA ", 6);
693 construct_default_ioirq_mptable(0);
699 printk(KERN_INFO "Processors: %d\n", num_processors);
701 * Only use the first configuration found.
705 static int __init smp_scan_config (unsigned long base, unsigned long length)
707 unsigned long *bp = phys_to_virt(base);
708 struct intel_mp_floating *mpf;
710 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
711 if (sizeof(*mpf) != 16)
712 printk("Error: MPF size\n");
715 mpf = (struct intel_mp_floating *)bp;
716 if ((*bp == SMP_MAGIC_IDENT) &&
717 (mpf->mpf_length == 1) &&
718 !mpf_checksum((unsigned char *)bp, 16) &&
719 ((mpf->mpf_specification == 1)
720 || (mpf->mpf_specification == 4)) ) {
722 smp_found_config = 1;
723 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
724 mpf, virt_to_phys(mpf));
725 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
727 if (mpf->mpf_physptr) {
729 * We cannot access to MPC table to compute
730 * table size yet, as only few megabytes from
731 * the bottom is mapped now.
732 * PC-9800's MPC table places on the very last
733 * of physical memory; so that simply reserving
734 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
735 * in reserve_bootmem.
737 unsigned long size = PAGE_SIZE;
738 unsigned long end = max_low_pfn * PAGE_SIZE;
739 if (mpf->mpf_physptr + size > end)
740 size = end - mpf->mpf_physptr;
741 reserve_bootmem(mpf->mpf_physptr, size,
754 void __init find_smp_config (void)
756 unsigned int address;
759 * FIXME: Linux assumes you have 640K of base ram..
760 * this continues the error...
762 * 1) Scan the bottom 1K for a signature
763 * 2) Scan the top 1K of base RAM
764 * 3) Scan the 64K of bios
766 if (smp_scan_config(0x0,0x400) ||
767 smp_scan_config(639*0x400,0x400) ||
768 smp_scan_config(0xF0000,0x10000))
771 * If it is an SMP machine we should know now, unless the
772 * configuration is in an EISA/MCA bus machine with an
773 * extended bios data area.
775 * there is a real-mode segmented pointer pointing to the
776 * 4K EBDA area at 0x40E, calculate and scan it here.
778 * NOTE! There are Linux loaders that will corrupt the EBDA
779 * area, and as such this kind of SMP config may be less
780 * trustworthy, simply because the SMP table may have been
781 * stomped on during early boot. These loaders are buggy and
784 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
787 address = get_bios_ebda();
789 smp_scan_config(address, 0x400);
792 /* --------------------------------------------------------------------------
793 ACPI-based MP Configuration
794 -------------------------------------------------------------------------- */
798 void __init mp_register_lapic_address(u64 address)
800 mp_lapic_addr = (unsigned long) address;
802 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
804 if (boot_cpu_physical_apicid == -1U)
805 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
807 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
810 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
812 if (MAX_APICS - id <= 0) {
813 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
819 #ifdef CONFIG_X86_SMP
825 generic_processor_info(id, GET_APIC_VERSION(apic_read(APIC_LVR)));
828 #ifdef CONFIG_X86_IO_APIC
831 #define MP_MAX_IOAPIC_PIN 127
833 static struct mp_ioapic_routing {
837 u32 pin_programmed[4];
838 } mp_ioapic_routing[MAX_IO_APICS];
840 static int mp_find_ioapic (int gsi)
844 /* Find the IOAPIC that manages this GSI. */
845 for (i = 0; i < nr_ioapics; i++) {
846 if ((gsi >= mp_ioapic_routing[i].gsi_base)
847 && (gsi <= mp_ioapic_routing[i].gsi_end))
851 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
856 static u8 uniq_ioapic_id(u8 id)
858 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
859 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
860 return io_apic_get_unique_id(nr_ioapics, id);
865 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
869 if (bad_ioapic(address))
874 mp_ioapics[idx].mpc_type = MP_IOAPIC;
875 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
876 mp_ioapics[idx].mpc_apicaddr = address;
878 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
879 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
880 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
883 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
884 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
886 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
887 mp_ioapic_routing[idx].gsi_base = gsi_base;
888 mp_ioapic_routing[idx].gsi_end = gsi_base +
889 io_apic_get_redir_entries(idx);
891 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
892 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
893 mp_ioapics[idx].mpc_apicver,
894 mp_ioapics[idx].mpc_apicaddr,
895 mp_ioapic_routing[idx].gsi_base,
896 mp_ioapic_routing[idx].gsi_end);
902 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
904 struct mpc_config_intsrc intsrc;
909 * Convert 'gsi' to 'ioapic.pin'.
911 ioapic = mp_find_ioapic(gsi);
914 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
917 * TBD: This check is for faulty timer entries, where the override
918 * erroneously sets the trigger to level, resulting in a HUGE
919 * increase of timer interrupts!
921 if ((bus_irq == 0) && (trigger == 3))
924 intsrc.mpc_type = MP_INTSRC;
925 intsrc.mpc_irqtype = mp_INT;
926 intsrc.mpc_irqflag = (trigger << 2) | polarity;
927 intsrc.mpc_srcbus = MP_ISA_BUS;
928 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
929 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
930 intsrc.mpc_dstirq = pin; /* INTIN# */
932 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
933 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
934 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
935 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
937 mp_irqs[mp_irq_entries] = intsrc;
938 if (++mp_irq_entries == MAX_IRQ_SOURCES)
939 panic("Max # of irq sources exceeded!\n");
944 void __init mp_config_acpi_legacy_irqs (void)
946 struct mpc_config_intsrc intsrc;
950 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
952 * Fabricate the legacy ISA bus (bus #31).
954 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
956 set_bit(MP_ISA_BUS, mp_bus_not_pci);
957 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
960 * Older generations of ES7000 have no legacy identity mappings
962 if (es7000_plat == 1)
966 * Locate the IOAPIC that manages the ISA IRQs (0-15).
968 ioapic = mp_find_ioapic(0);
972 intsrc.mpc_type = MP_INTSRC;
973 intsrc.mpc_irqflag = 0; /* Conforming */
974 intsrc.mpc_srcbus = MP_ISA_BUS;
975 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
978 * Use the default configuration for the IRQs 0-15. Unless
979 * overridden by (MADT) interrupt source override entries.
981 for (i = 0; i < 16; i++) {
984 for (idx = 0; idx < mp_irq_entries; idx++) {
985 struct mpc_config_intsrc *irq = mp_irqs + idx;
987 /* Do we already have a mapping for this ISA IRQ? */
988 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
991 /* Do we already have a mapping for this IOAPIC pin */
992 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
993 (irq->mpc_dstirq == i))
997 if (idx != mp_irq_entries) {
998 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
999 continue; /* IRQ already used */
1002 intsrc.mpc_irqtype = mp_INT;
1003 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1004 intsrc.mpc_dstirq = i;
1006 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1007 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1008 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1009 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1012 mp_irqs[mp_irq_entries] = intsrc;
1013 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1014 panic("Max # of irq sources exceeded!\n");
1018 #define MAX_GSI_NUM 4096
1019 #define IRQ_COMPRESSION_START 64
1021 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1026 static int pci_irq = IRQ_COMPRESSION_START;
1028 * Mapping between Global System Interrupts, which
1029 * represent all possible interrupts, and IRQs
1030 * assigned to actual devices.
1032 static int gsi_to_irq[MAX_GSI_NUM];
1034 /* Don't set up the ACPI SCI because it's already set up */
1035 if (acpi_gbl_FADT.sci_interrupt == gsi)
1038 ioapic = mp_find_ioapic(gsi);
1040 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1044 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1046 if (ioapic_renumber_irq)
1047 gsi = ioapic_renumber_irq(ioapic, gsi);
1050 * Avoid pin reprogramming. PRTs typically include entries
1051 * with redundant pin->gsi mappings (but unique PCI devices);
1052 * we only program the IOAPIC on the first.
1054 bit = ioapic_pin % 32;
1055 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1057 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1058 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1062 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1063 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1064 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1065 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1068 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1071 * For GSI >= 64, use IRQ compression
1073 if ((gsi >= IRQ_COMPRESSION_START)
1074 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1076 * For PCI devices assign IRQs in order, avoiding gaps
1077 * due to unused I/O APIC pins.
1080 if (gsi < MAX_GSI_NUM) {
1082 * Retain the VIA chipset work-around (gsi > 15), but
1083 * avoid a problem where the 8254 timer (IRQ0) is setup
1084 * via an override (so it's not on pin 0 of the ioapic),
1085 * and at the same time, the pin 0 interrupt is a PCI
1086 * type. The gsi > 15 test could cause these two pins
1087 * to be shared as IRQ0, and they are not shareable.
1088 * So test for this condition, and if necessary, avoid
1089 * the pin collision.
1093 * Don't assign IRQ used by ACPI SCI
1095 if (gsi == acpi_gbl_FADT.sci_interrupt)
1097 gsi_to_irq[irq] = gsi;
1099 printk(KERN_ERR "GSI %u is too high\n", gsi);
1104 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1105 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1106 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1110 #endif /* CONFIG_X86_IO_APIC */
1111 #endif /* CONFIG_ACPI */