2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 int apic_version [MAX_APICS];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
48 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58 /* MP IRQ source entries */
64 unsigned long mp_lapic_addr;
66 unsigned int def_to_bigsmp = 0;
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 unsigned int num_processors;
73 unsigned disabled_cpus __cpuinitdata;
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
79 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
83 * Intel MP BIOS table parsing routines:
88 * Checksum an MP configuration block.
91 static int __init mpf_checksum(unsigned char *mp, int len)
102 * Have to match translation table entries to main table entries by counter
103 * hence the mpc_record variable .... can't see a less disgusting way of
107 static int mpc_record;
108 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
110 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
112 int ver, apicid, cpu;
114 physid_mask_t phys_cpu;
116 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
121 #ifdef CONFIG_X86_NUMAQ
122 apicid = mpc_apic_id(m, translation_table[mpc_record]);
124 Dprintk("Processor #%d %u:%u APIC version %d\n",
126 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
127 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
129 apicid = m->mpc_apicid;
132 if (m->mpc_featureflag&(1<<0))
133 Dprintk(" Floating point unit present.\n");
134 if (m->mpc_featureflag&(1<<7))
135 Dprintk(" Machine Exception supported.\n");
136 if (m->mpc_featureflag&(1<<8))
137 Dprintk(" 64 bit compare & exchange supported.\n");
138 if (m->mpc_featureflag&(1<<9))
139 Dprintk(" Internal APIC present.\n");
140 if (m->mpc_featureflag&(1<<11))
141 Dprintk(" SEP present.\n");
142 if (m->mpc_featureflag&(1<<12))
143 Dprintk(" MTRR present.\n");
144 if (m->mpc_featureflag&(1<<13))
145 Dprintk(" PGE present.\n");
146 if (m->mpc_featureflag&(1<<14))
147 Dprintk(" MCA present.\n");
148 if (m->mpc_featureflag&(1<<15))
149 Dprintk(" CMOV present.\n");
150 if (m->mpc_featureflag&(1<<16))
151 Dprintk(" PAT present.\n");
152 if (m->mpc_featureflag&(1<<17))
153 Dprintk(" PSE present.\n");
154 if (m->mpc_featureflag&(1<<18))
155 Dprintk(" PSN present.\n");
156 if (m->mpc_featureflag&(1<<19))
157 Dprintk(" Cache Line Flush Instruction present.\n");
159 if (m->mpc_featureflag&(1<<21))
160 Dprintk(" Debug Trace and EMON Store present.\n");
161 if (m->mpc_featureflag&(1<<22))
162 Dprintk(" ACPI Thermal Throttle Registers present.\n");
163 if (m->mpc_featureflag&(1<<23))
164 Dprintk(" MMX present.\n");
165 if (m->mpc_featureflag&(1<<24))
166 Dprintk(" FXSR present.\n");
167 if (m->mpc_featureflag&(1<<25))
168 Dprintk(" XMM present.\n");
169 if (m->mpc_featureflag&(1<<26))
170 Dprintk(" Willamette New Instructions present.\n");
171 if (m->mpc_featureflag&(1<<27))
172 Dprintk(" Self Snoop present.\n");
173 if (m->mpc_featureflag&(1<<28))
174 Dprintk(" HT present.\n");
175 if (m->mpc_featureflag&(1<<29))
176 Dprintk(" Thermal Monitor present.\n");
177 /* 30, 31 Reserved */
180 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
181 Dprintk(" Bootup CPU\n");
182 boot_cpu_physical_apicid = m->mpc_apicid;
185 ver = m->mpc_apicver;
191 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
192 "fixing up to 0x10. (tell your hw vendor)\n",
196 apic_version[m->mpc_apicid] = ver;
198 phys_cpu = apicid_to_cpu_present(apicid);
199 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
201 if (num_processors >= NR_CPUS) {
202 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
203 " Processor ignored.\n", NR_CPUS);
207 if (num_processors >= maxcpus) {
208 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
209 " Processor ignored.\n", maxcpus);
213 cpu_set(num_processors, cpu_possible_map);
215 cpus_complement(tmp_map, cpu_present_map);
216 cpu = first_cpu(tmp_map);
218 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
220 * x86_bios_cpu_apicid is required to have processors listed
221 * in same order as logical cpu numbers. Hence the first
222 * entry is BSP, and so on.
227 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
228 * but we need to work other dependencies like SMP_SUSPEND etc
229 * before this can be done without some confusion.
230 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
231 * - Ashok Raj <ashok.raj@intel.com>
233 if (num_processors > 8) {
234 switch (boot_cpu_data.x86_vendor) {
235 case X86_VENDOR_INTEL:
236 if (!APIC_XAPIC(ver)) {
240 /* If P4 and above fall through */
246 /* are we being called early in kernel startup? */
247 if (x86_cpu_to_apicid_early_ptr) {
248 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
249 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
251 cpu_to_apicid[cpu] = m->mpc_apicid;
252 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
254 per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
255 per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid;
258 cpu_set(cpu, cpu_present_map);
261 static void __init MP_bus_info (struct mpc_config_bus *m)
265 memcpy(str, m->mpc_bustype, 6);
268 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
270 #if MAX_MP_BUSSES < 256
271 if (m->mpc_busid >= MAX_MP_BUSSES) {
272 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
273 " is too large, max. supported is %d\n",
274 m->mpc_busid, str, MAX_MP_BUSSES - 1);
279 set_bit(m->mpc_busid, mp_bus_not_pci);
280 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
281 mpc_oem_pci_bus(m, translation_table[mpc_record]);
282 clear_bit(m->mpc_busid, mp_bus_not_pci);
283 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
285 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
286 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
287 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
288 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
289 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
290 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
291 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
292 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
294 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
299 static int bad_ioapic(unsigned long address)
301 if (nr_ioapics >= MAX_IO_APICS) {
302 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
303 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
304 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
307 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
308 " found in table, skipping!\n");
314 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
316 if (!(m->mpc_flags & MPC_APIC_USABLE))
319 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
320 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
322 if (bad_ioapic(m->mpc_apicaddr))
325 mp_ioapics[nr_ioapics] = *m;
329 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
331 mp_irqs [mp_irq_entries] = *m;
332 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
333 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
334 m->mpc_irqtype, m->mpc_irqflag & 3,
335 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
336 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
337 if (++mp_irq_entries == MAX_IRQ_SOURCES)
338 panic("Max # of irq sources exceeded!!\n");
341 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
343 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
344 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
345 m->mpc_irqtype, m->mpc_irqflag & 3,
346 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
347 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
350 #ifdef CONFIG_X86_NUMAQ
351 static void __init MP_translation_info (struct mpc_config_translation *m)
353 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
355 if (mpc_record >= MAX_MPC_ENTRY)
356 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
358 translation_table[mpc_record] = m; /* stash this for later */
359 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
360 node_set_online(m->trans_quad);
364 * Read/parse the MPC oem tables
367 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
368 unsigned short oemsize)
370 int count = sizeof (*oemtable); /* the header size */
371 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
374 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
375 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
377 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
378 oemtable->oem_signature[0],
379 oemtable->oem_signature[1],
380 oemtable->oem_signature[2],
381 oemtable->oem_signature[3]);
384 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
386 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
389 while (count < oemtable->oem_length) {
393 struct mpc_config_translation *m=
394 (struct mpc_config_translation *)oemptr;
395 MP_translation_info(m);
396 oemptr += sizeof(*m);
403 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
410 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
413 if (strncmp(oem, "IBM NUMA", 8))
414 printk("Warning! May not be a NUMA-Q system!\n");
416 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
419 #endif /* CONFIG_X86_NUMAQ */
425 static int __init smp_read_mpc(struct mp_config_table *mpc)
429 int count=sizeof(*mpc);
430 unsigned char *mpt=((unsigned char *)mpc)+count;
432 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
433 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
434 *(u32 *)mpc->mpc_signature);
437 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
438 printk(KERN_ERR "SMP mptable: checksum error!\n");
441 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
442 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
446 if (!mpc->mpc_lapic) {
447 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
450 memcpy(oem,mpc->mpc_oem,8);
452 printk(KERN_INFO "OEM ID: %s ",oem);
454 memcpy(str,mpc->mpc_productid,12);
456 printk("Product ID: %s ",str);
458 mps_oem_check(mpc, oem, str);
460 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
463 * Save the local APIC address (it might be non-default) -- but only
464 * if we're not using ACPI.
467 mp_lapic_addr = mpc->mpc_lapic;
470 * Now process the configuration blocks.
473 while (count < mpc->mpc_length) {
477 struct mpc_config_processor *m=
478 (struct mpc_config_processor *)mpt;
479 /* ACPI may have already provided this data */
481 MP_processor_info(m);
488 struct mpc_config_bus *m=
489 (struct mpc_config_bus *)mpt;
497 struct mpc_config_ioapic *m=
498 (struct mpc_config_ioapic *)mpt;
506 struct mpc_config_intsrc *m=
507 (struct mpc_config_intsrc *)mpt;
516 struct mpc_config_lintsrc *m=
517 (struct mpc_config_lintsrc *)mpt;
525 count = mpc->mpc_length;
531 setup_apic_routing();
533 printk(KERN_ERR "SMP mptable: no processors registered!\n");
534 return num_processors;
537 static int __init ELCR_trigger(unsigned int irq)
541 port = 0x4d0 + (irq >> 3);
542 return (inb(port) >> (irq & 7)) & 1;
545 static void __init construct_default_ioirq_mptable(int mpc_default_type)
547 struct mpc_config_intsrc intsrc;
549 int ELCR_fallback = 0;
551 intsrc.mpc_type = MP_INTSRC;
552 intsrc.mpc_irqflag = 0; /* conforming */
553 intsrc.mpc_srcbus = 0;
554 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
556 intsrc.mpc_irqtype = mp_INT;
559 * If true, we have an ISA/PCI system with no IRQ entries
560 * in the MP table. To prevent the PCI interrupts from being set up
561 * incorrectly, we try to use the ELCR. The sanity check to see if
562 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
563 * never be level sensitive, so we simply see if the ELCR agrees.
564 * If it does, we assume it's valid.
566 if (mpc_default_type == 5) {
567 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
569 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
570 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
572 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
577 for (i = 0; i < 16; i++) {
578 switch (mpc_default_type) {
580 if (i == 0 || i == 13)
581 continue; /* IRQ0 & IRQ13 not connected */
585 continue; /* IRQ2 is never connected */
590 * If the ELCR indicates a level-sensitive interrupt, we
591 * copy that information over to the MP table in the
592 * irqflag field (level sensitive, active high polarity).
595 intsrc.mpc_irqflag = 13;
597 intsrc.mpc_irqflag = 0;
600 intsrc.mpc_srcbusirq = i;
601 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
602 MP_intsrc_info(&intsrc);
605 intsrc.mpc_irqtype = mp_ExtINT;
606 intsrc.mpc_srcbusirq = 0;
607 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
608 MP_intsrc_info(&intsrc);
611 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
613 struct mpc_config_processor processor;
614 struct mpc_config_bus bus;
615 struct mpc_config_ioapic ioapic;
616 struct mpc_config_lintsrc lintsrc;
617 int linttypes[2] = { mp_ExtINT, mp_NMI };
621 * local APIC has default address
623 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
626 * 2 CPUs, numbered 0 & 1.
628 processor.mpc_type = MP_PROCESSOR;
629 /* Either an integrated APIC or a discrete 82489DX. */
630 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
631 processor.mpc_cpuflag = CPU_ENABLED;
632 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
633 (boot_cpu_data.x86_model << 4) |
634 boot_cpu_data.x86_mask;
635 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
636 processor.mpc_reserved[0] = 0;
637 processor.mpc_reserved[1] = 0;
638 for (i = 0; i < 2; i++) {
639 processor.mpc_apicid = i;
640 MP_processor_info(&processor);
643 bus.mpc_type = MP_BUS;
645 switch (mpc_default_type) {
648 printk(KERN_ERR "Unknown standard configuration %d\n",
653 memcpy(bus.mpc_bustype, "ISA ", 6);
658 memcpy(bus.mpc_bustype, "EISA ", 6);
662 memcpy(bus.mpc_bustype, "MCA ", 6);
665 if (mpc_default_type > 4) {
667 memcpy(bus.mpc_bustype, "PCI ", 6);
671 ioapic.mpc_type = MP_IOAPIC;
672 ioapic.mpc_apicid = 2;
673 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
674 ioapic.mpc_flags = MPC_APIC_USABLE;
675 ioapic.mpc_apicaddr = 0xFEC00000;
676 MP_ioapic_info(&ioapic);
679 * We set up most of the low 16 IO-APIC pins according to MPS rules.
681 construct_default_ioirq_mptable(mpc_default_type);
683 lintsrc.mpc_type = MP_LINTSRC;
684 lintsrc.mpc_irqflag = 0; /* conforming */
685 lintsrc.mpc_srcbusid = 0;
686 lintsrc.mpc_srcbusirq = 0;
687 lintsrc.mpc_destapic = MP_APIC_ALL;
688 for (i = 0; i < 2; i++) {
689 lintsrc.mpc_irqtype = linttypes[i];
690 lintsrc.mpc_destapiclint = i;
691 MP_lintsrc_info(&lintsrc);
695 static struct intel_mp_floating *mpf_found;
698 * Scan the memory blocks for an SMP configuration block.
700 void __init get_smp_config (void)
702 struct intel_mp_floating *mpf = mpf_found;
705 * ACPI supports both logical (e.g. Hyper-Threading) and physical
706 * processors, where MPS only supports physical.
708 if (acpi_lapic && acpi_ioapic) {
709 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
713 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
715 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
716 if (mpf->mpf_feature2 & (1<<7)) {
717 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
720 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
725 * Now see if we need to read further.
727 if (mpf->mpf_feature1 != 0) {
729 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
730 construct_default_ISA_mptable(mpf->mpf_feature1);
732 } else if (mpf->mpf_physptr) {
735 * Read the physical hardware table. Anything here will
736 * override the defaults.
738 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
739 smp_found_config = 0;
740 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
741 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
745 * If there are no explicit MP IRQ entries, then we are
746 * broken. We set up most of the low 16 IO-APIC pins to
747 * ISA defaults and hope it will work.
749 if (!mp_irq_entries) {
750 struct mpc_config_bus bus;
752 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
754 bus.mpc_type = MP_BUS;
756 memcpy(bus.mpc_bustype, "ISA ", 6);
759 construct_default_ioirq_mptable(0);
765 printk(KERN_INFO "Processors: %d\n", num_processors);
767 * Only use the first configuration found.
771 static int __init smp_scan_config (unsigned long base, unsigned long length)
773 unsigned long *bp = phys_to_virt(base);
774 struct intel_mp_floating *mpf;
776 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
777 if (sizeof(*mpf) != 16)
778 printk("Error: MPF size\n");
781 mpf = (struct intel_mp_floating *)bp;
782 if ((*bp == SMP_MAGIC_IDENT) &&
783 (mpf->mpf_length == 1) &&
784 !mpf_checksum((unsigned char *)bp, 16) &&
785 ((mpf->mpf_specification == 1)
786 || (mpf->mpf_specification == 4)) ) {
788 smp_found_config = 1;
789 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
790 mpf, virt_to_phys(mpf));
791 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
793 if (mpf->mpf_physptr) {
795 * We cannot access to MPC table to compute
796 * table size yet, as only few megabytes from
797 * the bottom is mapped now.
798 * PC-9800's MPC table places on the very last
799 * of physical memory; so that simply reserving
800 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
801 * in reserve_bootmem.
803 unsigned long size = PAGE_SIZE;
804 unsigned long end = max_low_pfn * PAGE_SIZE;
805 if (mpf->mpf_physptr + size > end)
806 size = end - mpf->mpf_physptr;
807 reserve_bootmem(mpf->mpf_physptr, size,
820 void __init find_smp_config (void)
822 unsigned int address;
825 * FIXME: Linux assumes you have 640K of base ram..
826 * this continues the error...
828 * 1) Scan the bottom 1K for a signature
829 * 2) Scan the top 1K of base RAM
830 * 3) Scan the 64K of bios
832 if (smp_scan_config(0x0,0x400) ||
833 smp_scan_config(639*0x400,0x400) ||
834 smp_scan_config(0xF0000,0x10000))
837 * If it is an SMP machine we should know now, unless the
838 * configuration is in an EISA/MCA bus machine with an
839 * extended bios data area.
841 * there is a real-mode segmented pointer pointing to the
842 * 4K EBDA area at 0x40E, calculate and scan it here.
844 * NOTE! There are Linux loaders that will corrupt the EBDA
845 * area, and as such this kind of SMP config may be less
846 * trustworthy, simply because the SMP table may have been
847 * stomped on during early boot. These loaders are buggy and
850 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
853 address = get_bios_ebda();
855 smp_scan_config(address, 0x400);
860 /* --------------------------------------------------------------------------
861 ACPI-based MP Configuration
862 -------------------------------------------------------------------------- */
866 void __init mp_register_lapic_address(u64 address)
868 mp_lapic_addr = (unsigned long) address;
870 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
872 if (boot_cpu_physical_apicid == -1U)
873 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
875 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
878 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
880 struct mpc_config_processor processor;
883 if (MAX_APICS - id <= 0) {
884 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
889 if (id == boot_cpu_physical_apicid)
892 processor.mpc_type = MP_PROCESSOR;
893 processor.mpc_apicid = id;
894 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
895 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
896 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
897 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
898 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
899 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
900 processor.mpc_reserved[0] = 0;
901 processor.mpc_reserved[1] = 0;
903 MP_processor_info(&processor);
906 #ifdef CONFIG_X86_IO_APIC
909 #define MP_MAX_IOAPIC_PIN 127
911 static struct mp_ioapic_routing {
915 u32 pin_programmed[4];
916 } mp_ioapic_routing[MAX_IO_APICS];
918 static int mp_find_ioapic (int gsi)
922 /* Find the IOAPIC that manages this GSI. */
923 for (i = 0; i < nr_ioapics; i++) {
924 if ((gsi >= mp_ioapic_routing[i].gsi_base)
925 && (gsi <= mp_ioapic_routing[i].gsi_end))
929 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
934 static u8 uniq_ioapic_id(u8 id)
936 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
937 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
938 return io_apic_get_unique_id(nr_ioapics, id);
943 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
947 if (bad_ioapic(address))
952 mp_ioapics[idx].mpc_type = MP_IOAPIC;
953 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
954 mp_ioapics[idx].mpc_apicaddr = address;
956 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
957 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
958 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
961 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
962 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
964 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
965 mp_ioapic_routing[idx].gsi_base = gsi_base;
966 mp_ioapic_routing[idx].gsi_end = gsi_base +
967 io_apic_get_redir_entries(idx);
969 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
970 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
971 mp_ioapics[idx].mpc_apicver,
972 mp_ioapics[idx].mpc_apicaddr,
973 mp_ioapic_routing[idx].gsi_base,
974 mp_ioapic_routing[idx].gsi_end);
980 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
982 struct mpc_config_intsrc intsrc;
987 * Convert 'gsi' to 'ioapic.pin'.
989 ioapic = mp_find_ioapic(gsi);
992 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
995 * TBD: This check is for faulty timer entries, where the override
996 * erroneously sets the trigger to level, resulting in a HUGE
997 * increase of timer interrupts!
999 if ((bus_irq == 0) && (trigger == 3))
1002 intsrc.mpc_type = MP_INTSRC;
1003 intsrc.mpc_irqtype = mp_INT;
1004 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1005 intsrc.mpc_srcbus = MP_ISA_BUS;
1006 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1007 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1008 intsrc.mpc_dstirq = pin; /* INTIN# */
1010 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1011 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1012 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1013 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1015 mp_irqs[mp_irq_entries] = intsrc;
1016 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1017 panic("Max # of irq sources exceeded!\n");
1020 void __init mp_config_acpi_legacy_irqs (void)
1022 struct mpc_config_intsrc intsrc;
1026 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1028 * Fabricate the legacy ISA bus (bus #31).
1030 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1032 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1033 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1036 * Older generations of ES7000 have no legacy identity mappings
1038 if (es7000_plat == 1)
1042 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1044 ioapic = mp_find_ioapic(0);
1048 intsrc.mpc_type = MP_INTSRC;
1049 intsrc.mpc_irqflag = 0; /* Conforming */
1050 intsrc.mpc_srcbus = MP_ISA_BUS;
1051 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1054 * Use the default configuration for the IRQs 0-15. Unless
1055 * overridden by (MADT) interrupt source override entries.
1057 for (i = 0; i < 16; i++) {
1060 for (idx = 0; idx < mp_irq_entries; idx++) {
1061 struct mpc_config_intsrc *irq = mp_irqs + idx;
1063 /* Do we already have a mapping for this ISA IRQ? */
1064 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1067 /* Do we already have a mapping for this IOAPIC pin */
1068 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1069 (irq->mpc_dstirq == i))
1073 if (idx != mp_irq_entries) {
1074 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1075 continue; /* IRQ already used */
1078 intsrc.mpc_irqtype = mp_INT;
1079 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1080 intsrc.mpc_dstirq = i;
1082 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1083 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1084 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1085 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1088 mp_irqs[mp_irq_entries] = intsrc;
1089 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1090 panic("Max # of irq sources exceeded!\n");
1094 #define MAX_GSI_NUM 4096
1095 #define IRQ_COMPRESSION_START 64
1097 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1102 static int pci_irq = IRQ_COMPRESSION_START;
1104 * Mapping between Global System Interrupts, which
1105 * represent all possible interrupts, and IRQs
1106 * assigned to actual devices.
1108 static int gsi_to_irq[MAX_GSI_NUM];
1110 /* Don't set up the ACPI SCI because it's already set up */
1111 if (acpi_gbl_FADT.sci_interrupt == gsi)
1114 ioapic = mp_find_ioapic(gsi);
1116 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1120 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1122 if (ioapic_renumber_irq)
1123 gsi = ioapic_renumber_irq(ioapic, gsi);
1126 * Avoid pin reprogramming. PRTs typically include entries
1127 * with redundant pin->gsi mappings (but unique PCI devices);
1128 * we only program the IOAPIC on the first.
1130 bit = ioapic_pin % 32;
1131 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1133 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1134 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1138 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1139 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1140 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1141 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1144 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1147 * For GSI >= 64, use IRQ compression
1149 if ((gsi >= IRQ_COMPRESSION_START)
1150 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1152 * For PCI devices assign IRQs in order, avoiding gaps
1153 * due to unused I/O APIC pins.
1156 if (gsi < MAX_GSI_NUM) {
1158 * Retain the VIA chipset work-around (gsi > 15), but
1159 * avoid a problem where the 8254 timer (IRQ0) is setup
1160 * via an override (so it's not on pin 0 of the ioapic),
1161 * and at the same time, the pin 0 interrupt is a PCI
1162 * type. The gsi > 15 test could cause these two pins
1163 * to be shared as IRQ0, and they are not shareable.
1164 * So test for this condition, and if necessary, avoid
1165 * the pin collision.
1167 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1170 * Don't assign IRQ used by ACPI SCI
1172 if (gsi == acpi_gbl_FADT.sci_interrupt)
1174 gsi_to_irq[irq] = gsi;
1176 printk(KERN_ERR "GSI %u is too high\n", gsi);
1181 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1182 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1183 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1187 #endif /* CONFIG_X86_IO_APIC */
1188 #endif /* CONFIG_ACPI */