2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
61 int timer_through_8259 __initdata;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug = -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers[MAX_IO_APICS];
74 /* I/O APIC entries */
75 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
78 /* MP IRQ source entries */
79 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
81 /* # of MP IRQ source entries */
84 static int disable_timer_pin_1 __initdata;
87 * Rough estimation of how many shared IRQs there are, can
90 #define MAX_PLUS_SHARED_IRQS NR_IRQS
91 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
94 * This is performance-critical, we want to do it O(1)
96 * the indexing order of this array favors 1:1 mappings
97 * between pins and IRQs.
100 static struct irq_pin_list {
102 } irq_2_pin[PIN_MAP_SIZE];
106 unsigned int unused[3];
110 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
112 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
113 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
116 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
118 struct io_apic __iomem *io_apic = io_apic_base(apic);
119 writel(reg, &io_apic->index);
120 return readl(&io_apic->data);
123 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
125 struct io_apic __iomem *io_apic = io_apic_base(apic);
126 writel(reg, &io_apic->index);
127 writel(value, &io_apic->data);
131 * Re-write a value: to be used for read-modify-write
132 * cycles where the read already set up the index register.
134 * Older SiS APIC requires we rewrite the index register
136 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
138 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
140 writel(reg, &io_apic->index);
141 writel(value, &io_apic->data);
145 struct { u32 w1, w2; };
146 struct IO_APIC_route_entry entry;
149 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
151 union entry_union eu;
153 spin_lock_irqsave(&ioapic_lock, flags);
154 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
155 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
156 spin_unlock_irqrestore(&ioapic_lock, flags);
161 * When we write a new IO APIC routing entry, we need to write the high
162 * word first! If the mask bit in the low word is clear, we will enable
163 * the interrupt, and we need to make sure the entry is fully populated
164 * before that happens.
167 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
169 union entry_union eu;
171 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
172 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
175 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
178 spin_lock_irqsave(&ioapic_lock, flags);
179 __ioapic_write_entry(apic, pin, e);
180 spin_unlock_irqrestore(&ioapic_lock, flags);
184 * When we mask an IO APIC routing entry, we need to write the low
185 * word first, in order to set the mask bit before we change the
188 static void ioapic_mask_entry(int apic, int pin)
191 union entry_union eu = { .entry.mask = 1 };
193 spin_lock_irqsave(&ioapic_lock, flags);
194 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
195 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
196 spin_unlock_irqrestore(&ioapic_lock, flags);
200 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
201 * shared ISA-space IRQs, so we have to support them. We are super
202 * fast in the common case, and fast for shared ISA-space IRQs.
204 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
206 static int first_free_entry = NR_IRQS;
207 struct irq_pin_list *entry = irq_2_pin + irq;
210 entry = irq_2_pin + entry->next;
212 if (entry->pin != -1) {
213 entry->next = first_free_entry;
214 entry = irq_2_pin + entry->next;
215 if (++first_free_entry >= PIN_MAP_SIZE)
216 panic("io_apic.c: whoops");
223 * Reroute an IRQ to a different pin.
225 static void __init replace_pin_at_irq(unsigned int irq,
226 int oldapic, int oldpin,
227 int newapic, int newpin)
229 struct irq_pin_list *entry = irq_2_pin + irq;
232 if (entry->apic == oldapic && entry->pin == oldpin) {
233 entry->apic = newapic;
238 entry = irq_2_pin + entry->next;
242 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
244 struct irq_pin_list *entry = irq_2_pin + irq;
245 unsigned int pin, reg;
251 reg = io_apic_read(entry->apic, 0x10 + pin*2);
254 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
257 entry = irq_2_pin + entry->next;
262 static void __mask_IO_APIC_irq (unsigned int irq)
264 __modify_IO_APIC_irq(irq, 0x00010000, 0);
268 static void __unmask_IO_APIC_irq (unsigned int irq)
270 __modify_IO_APIC_irq(irq, 0, 0x00010000);
273 /* mask = 1, trigger = 0 */
274 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
276 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
279 /* mask = 0, trigger = 1 */
280 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
282 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
285 static void mask_IO_APIC_irq (unsigned int irq)
289 spin_lock_irqsave(&ioapic_lock, flags);
290 __mask_IO_APIC_irq(irq);
291 spin_unlock_irqrestore(&ioapic_lock, flags);
294 static void unmask_IO_APIC_irq (unsigned int irq)
298 spin_lock_irqsave(&ioapic_lock, flags);
299 __unmask_IO_APIC_irq(irq);
300 spin_unlock_irqrestore(&ioapic_lock, flags);
303 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
305 struct IO_APIC_route_entry entry;
307 /* Check delivery_mode to be sure we're not clearing an SMI pin */
308 entry = ioapic_read_entry(apic, pin);
309 if (entry.delivery_mode == dest_SMI)
313 * Disable it in the IO-APIC irq-routing table:
315 ioapic_mask_entry(apic, pin);
318 static void clear_IO_APIC (void)
322 for (apic = 0; apic < nr_ioapics; apic++)
323 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
324 clear_IO_APIC_pin(apic, pin);
328 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
332 struct irq_pin_list *entry = irq_2_pin + irq;
333 unsigned int apicid_value;
336 cpus_and(tmp, cpumask, cpu_online_map);
340 cpus_and(cpumask, tmp, CPU_MASK_ALL);
342 apicid_value = cpu_mask_to_apicid(cpumask);
343 /* Prepare to do the io_apic_write */
344 apicid_value = apicid_value << 24;
345 spin_lock_irqsave(&ioapic_lock, flags);
350 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
353 entry = irq_2_pin + entry->next;
355 irq_desc[irq].affinity = cpumask;
356 spin_unlock_irqrestore(&ioapic_lock, flags);
359 #if defined(CONFIG_IRQBALANCE)
360 # include <asm/processor.h> /* kernel_thread() */
361 # include <linux/kernel_stat.h> /* kstat */
362 # include <linux/slab.h> /* kmalloc() */
363 # include <linux/timer.h>
365 #define IRQBALANCE_CHECK_ARCH -999
366 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
367 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
368 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
369 #define BALANCED_IRQ_LESS_DELTA (HZ)
371 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
372 static int physical_balance __read_mostly;
373 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
375 static struct irq_cpu_info {
376 unsigned long * last_irq;
377 unsigned long * irq_delta;
379 } irq_cpu_data[NR_CPUS];
381 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
382 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
383 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
385 #define IDLE_ENOUGH(cpu,now) \
386 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
388 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
390 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
392 static cpumask_t balance_irq_affinity[NR_IRQS] = {
393 [0 ... NR_IRQS-1] = CPU_MASK_ALL
396 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
398 balance_irq_affinity[irq] = mask;
401 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
402 unsigned long now, int direction)
410 if (unlikely(cpu == curr_cpu))
413 if (direction == 1) {
422 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
423 (search_idle && !IDLE_ENOUGH(cpu,now)));
428 static inline void balance_irq(int cpu, int irq)
430 unsigned long now = jiffies;
431 cpumask_t allowed_mask;
432 unsigned int new_cpu;
434 if (irqbalance_disabled)
437 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
438 new_cpu = move(cpu, allowed_mask, now, 1);
439 if (cpu != new_cpu) {
440 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
444 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
448 for_each_online_cpu(i) {
449 for (j = 0; j < NR_IRQS; j++) {
450 if (!irq_desc[j].action)
452 /* Is it a significant load ? */
453 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
454 useful_load_threshold)
459 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
460 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
464 static void do_irq_balance(void)
467 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
468 unsigned long move_this_load = 0;
469 int max_loaded = 0, min_loaded = 0;
471 unsigned long useful_load_threshold = balanced_irq_interval + 10;
473 int tmp_loaded, first_attempt = 1;
474 unsigned long tmp_cpu_irq;
475 unsigned long imbalance = 0;
476 cpumask_t allowed_mask, target_cpu_mask, tmp;
478 for_each_possible_cpu(i) {
483 package_index = CPU_TO_PACKAGEINDEX(i);
484 for (j = 0; j < NR_IRQS; j++) {
485 unsigned long value_now, delta;
486 /* Is this an active IRQ or balancing disabled ? */
487 if (!irq_desc[j].action || irq_balancing_disabled(j))
489 if ( package_index == i )
490 IRQ_DELTA(package_index,j) = 0;
491 /* Determine the total count per processor per IRQ */
492 value_now = (unsigned long) kstat_cpu(i).irqs[j];
494 /* Determine the activity per processor per IRQ */
495 delta = value_now - LAST_CPU_IRQ(i,j);
497 /* Update last_cpu_irq[][] for the next time */
498 LAST_CPU_IRQ(i,j) = value_now;
500 /* Ignore IRQs whose rate is less than the clock */
501 if (delta < useful_load_threshold)
503 /* update the load for the processor or package total */
504 IRQ_DELTA(package_index,j) += delta;
506 /* Keep track of the higher numbered sibling as well */
507 if (i != package_index)
510 * We have sibling A and sibling B in the package
512 * cpu_irq[A] = load for cpu A + load for cpu B
513 * cpu_irq[B] = load for cpu B
515 CPU_IRQ(package_index) += delta;
518 /* Find the least loaded processor package */
519 for_each_online_cpu(i) {
520 if (i != CPU_TO_PACKAGEINDEX(i))
522 if (min_cpu_irq > CPU_IRQ(i)) {
523 min_cpu_irq = CPU_IRQ(i);
527 max_cpu_irq = ULONG_MAX;
530 /* Look for heaviest loaded processor.
531 * We may come back to get the next heaviest loaded processor.
532 * Skip processors with trivial loads.
536 for_each_online_cpu(i) {
537 if (i != CPU_TO_PACKAGEINDEX(i))
539 if (max_cpu_irq <= CPU_IRQ(i))
541 if (tmp_cpu_irq < CPU_IRQ(i)) {
542 tmp_cpu_irq = CPU_IRQ(i);
547 if (tmp_loaded == -1) {
548 /* In the case of small number of heavy interrupt sources,
549 * loading some of the cpus too much. We use Ingo's original
550 * approach to rotate them around.
552 if (!first_attempt && imbalance >= useful_load_threshold) {
553 rotate_irqs_among_cpus(useful_load_threshold);
556 goto not_worth_the_effort;
559 first_attempt = 0; /* heaviest search */
560 max_cpu_irq = tmp_cpu_irq; /* load */
561 max_loaded = tmp_loaded; /* processor */
562 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
564 /* if imbalance is less than approx 10% of max load, then
565 * observe diminishing returns action. - quit
567 if (imbalance < (max_cpu_irq >> 3))
568 goto not_worth_the_effort;
571 /* if we select an IRQ to move that can't go where we want, then
572 * see if there is another one to try.
576 for (j = 0; j < NR_IRQS; j++) {
577 /* Is this an active IRQ? */
578 if (!irq_desc[j].action)
580 if (imbalance <= IRQ_DELTA(max_loaded,j))
582 /* Try to find the IRQ that is closest to the imbalance
583 * without going over.
585 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
586 move_this_load = IRQ_DELTA(max_loaded,j);
590 if (selected_irq == -1) {
594 imbalance = move_this_load;
596 /* For physical_balance case, we accumulated both load
597 * values in the one of the siblings cpu_irq[],
598 * to use the same code for physical and logical processors
599 * as much as possible.
601 * NOTE: the cpu_irq[] array holds the sum of the load for
602 * sibling A and sibling B in the slot for the lowest numbered
603 * sibling (A), _AND_ the load for sibling B in the slot for
604 * the higher numbered sibling.
606 * We seek the least loaded sibling by making the comparison
609 load = CPU_IRQ(min_loaded) >> 1;
610 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
611 if (load > CPU_IRQ(j)) {
612 /* This won't change cpu_sibling_map[min_loaded] */
618 cpus_and(allowed_mask,
620 balance_irq_affinity[selected_irq]);
621 target_cpu_mask = cpumask_of_cpu(min_loaded);
622 cpus_and(tmp, target_cpu_mask, allowed_mask);
624 if (!cpus_empty(tmp)) {
625 /* mark for change destination */
626 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
628 /* Since we made a change, come back sooner to
629 * check for more variation.
631 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
632 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
637 not_worth_the_effort:
639 * if we did not find an IRQ to move, then adjust the time interval
642 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
643 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
647 static int balanced_irq(void *unused)
650 unsigned long prev_balance_time = jiffies;
651 long time_remaining = balanced_irq_interval;
653 /* push everything to CPU 0 to give us a starting point. */
654 for (i = 0 ; i < NR_IRQS ; i++) {
655 irq_desc[i].pending_mask = cpumask_of_cpu(0);
656 set_pending_irq(i, cpumask_of_cpu(0));
661 time_remaining = schedule_timeout_interruptible(time_remaining);
663 if (time_after(jiffies,
664 prev_balance_time+balanced_irq_interval)) {
667 prev_balance_time = jiffies;
668 time_remaining = balanced_irq_interval;
675 static int __init balanced_irq_init(void)
678 struct cpuinfo_x86 *c;
681 cpus_shift_right(tmp, cpu_online_map, 2);
683 /* When not overwritten by the command line ask subarchitecture. */
684 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
685 irqbalance_disabled = NO_BALANCE_IRQ;
686 if (irqbalance_disabled)
689 /* disable irqbalance completely if there is only one processor online */
690 if (num_online_cpus() < 2) {
691 irqbalance_disabled = 1;
695 * Enable physical balance only if more than 1 physical processor
698 if (smp_num_siblings > 1 && !cpus_empty(tmp))
699 physical_balance = 1;
701 for_each_online_cpu(i) {
702 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
703 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
704 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
705 printk(KERN_ERR "balanced_irq_init: out of memory");
708 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
709 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
712 printk(KERN_INFO "Starting balanced_irq\n");
713 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
715 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
717 for_each_possible_cpu(i) {
718 kfree(irq_cpu_data[i].irq_delta);
719 irq_cpu_data[i].irq_delta = NULL;
720 kfree(irq_cpu_data[i].last_irq);
721 irq_cpu_data[i].last_irq = NULL;
726 int __devinit irqbalance_disable(char *str)
728 irqbalance_disabled = 1;
732 __setup("noirqbalance", irqbalance_disable);
734 late_initcall(balanced_irq_init);
735 #endif /* CONFIG_IRQBALANCE */
736 #endif /* CONFIG_SMP */
739 void send_IPI_self(int vector)
746 apic_wait_icr_idle();
747 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
749 * Send the IPI. The write to APIC_ICR fires this off.
751 apic_write_around(APIC_ICR, cfg);
753 #endif /* !CONFIG_SMP */
757 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
758 * specific CPU-side IRQs.
762 static int pirq_entries [MAX_PIRQS];
763 static int pirqs_enabled;
764 int skip_ioapic_setup;
766 static int __init ioapic_pirq_setup(char *str)
769 int ints[MAX_PIRQS+1];
771 get_options(str, ARRAY_SIZE(ints), ints);
773 for (i = 0; i < MAX_PIRQS; i++)
774 pirq_entries[i] = -1;
777 apic_printk(APIC_VERBOSE, KERN_INFO
778 "PIRQ redirection, working around broken MP-BIOS.\n");
780 if (ints[0] < MAX_PIRQS)
783 for (i = 0; i < max; i++) {
784 apic_printk(APIC_VERBOSE, KERN_DEBUG
785 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
787 * PIRQs are mapped upside down, usually.
789 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
794 __setup("pirq=", ioapic_pirq_setup);
797 * Find the IRQ entry number of a certain pin.
799 static int find_irq_entry(int apic, int pin, int type)
803 for (i = 0; i < mp_irq_entries; i++)
804 if (mp_irqs[i].mpc_irqtype == type &&
805 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
806 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
807 mp_irqs[i].mpc_dstirq == pin)
814 * Find the pin to which IRQ[irq] (ISA) is connected
816 static int __init find_isa_irq_pin(int irq, int type)
820 for (i = 0; i < mp_irq_entries; i++) {
821 int lbus = mp_irqs[i].mpc_srcbus;
823 if (test_bit(lbus, mp_bus_not_pci) &&
824 (mp_irqs[i].mpc_irqtype == type) &&
825 (mp_irqs[i].mpc_srcbusirq == irq))
827 return mp_irqs[i].mpc_dstirq;
832 static int __init find_isa_irq_apic(int irq, int type)
836 for (i = 0; i < mp_irq_entries; i++) {
837 int lbus = mp_irqs[i].mpc_srcbus;
839 if (test_bit(lbus, mp_bus_not_pci) &&
840 (mp_irqs[i].mpc_irqtype == type) &&
841 (mp_irqs[i].mpc_srcbusirq == irq))
844 if (i < mp_irq_entries) {
846 for(apic = 0; apic < nr_ioapics; apic++) {
847 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
856 * Find a specific PCI IRQ entry.
857 * Not an __init, possibly needed by modules
859 static int pin_2_irq(int idx, int apic, int pin);
861 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
863 int apic, i, best_guess = -1;
865 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
866 "slot:%d, pin:%d.\n", bus, slot, pin);
867 if (mp_bus_id_to_pci_bus[bus] == -1) {
868 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
871 for (i = 0; i < mp_irq_entries; i++) {
872 int lbus = mp_irqs[i].mpc_srcbus;
874 for (apic = 0; apic < nr_ioapics; apic++)
875 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
876 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
879 if (!test_bit(lbus, mp_bus_not_pci) &&
880 !mp_irqs[i].mpc_irqtype &&
882 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
883 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
885 if (!(apic || IO_APIC_IRQ(irq)))
888 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
891 * Use the first all-but-pin matching entry as a
892 * best-guess fuzzy result for broken mptables.
900 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
903 * This function currently is only a helper for the i386 smp boot process where
904 * we need to reprogram the ioredtbls to cater for the cpus which have come online
905 * so mask in all cases should simply be TARGET_CPUS
908 void __init setup_ioapic_dest(void)
910 int pin, ioapic, irq, irq_entry;
912 if (skip_ioapic_setup == 1)
915 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
916 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
917 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
920 irq = pin_2_irq(irq_entry, ioapic, pin);
921 set_ioapic_affinity_irq(irq, TARGET_CPUS);
928 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
930 * EISA Edge/Level control register, ELCR
932 static int EISA_ELCR(unsigned int irq)
935 unsigned int port = 0x4d0 + (irq >> 3);
936 return (inb(port) >> (irq & 7)) & 1;
938 apic_printk(APIC_VERBOSE, KERN_INFO
939 "Broken MPtable reports ISA irq %d\n", irq);
944 /* ISA interrupts are always polarity zero edge triggered,
945 * when listed as conforming in the MP table. */
947 #define default_ISA_trigger(idx) (0)
948 #define default_ISA_polarity(idx) (0)
950 /* EISA interrupts are always polarity zero and can be edge or level
951 * trigger depending on the ELCR value. If an interrupt is listed as
952 * EISA conforming in the MP table, that means its trigger type must
953 * be read in from the ELCR */
955 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
956 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
958 /* PCI interrupts are always polarity one level triggered,
959 * when listed as conforming in the MP table. */
961 #define default_PCI_trigger(idx) (1)
962 #define default_PCI_polarity(idx) (1)
964 /* MCA interrupts are always polarity zero level triggered,
965 * when listed as conforming in the MP table. */
967 #define default_MCA_trigger(idx) (1)
968 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
970 static int MPBIOS_polarity(int idx)
972 int bus = mp_irqs[idx].mpc_srcbus;
976 * Determine IRQ line polarity (high active or low active):
978 switch (mp_irqs[idx].mpc_irqflag & 3)
980 case 0: /* conforms, ie. bus-type dependent polarity */
982 polarity = test_bit(bus, mp_bus_not_pci)?
983 default_ISA_polarity(idx):
984 default_PCI_polarity(idx);
987 case 1: /* high active */
992 case 2: /* reserved */
994 printk(KERN_WARNING "broken BIOS!!\n");
998 case 3: /* low active */
1003 default: /* invalid */
1005 printk(KERN_WARNING "broken BIOS!!\n");
1013 static int MPBIOS_trigger(int idx)
1015 int bus = mp_irqs[idx].mpc_srcbus;
1019 * Determine IRQ trigger mode (edge or level sensitive):
1021 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1023 case 0: /* conforms, ie. bus-type dependent */
1025 trigger = test_bit(bus, mp_bus_not_pci)?
1026 default_ISA_trigger(idx):
1027 default_PCI_trigger(idx);
1028 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1029 switch (mp_bus_id_to_type[bus])
1031 case MP_BUS_ISA: /* ISA pin */
1033 /* set before the switch */
1036 case MP_BUS_EISA: /* EISA pin */
1038 trigger = default_EISA_trigger(idx);
1041 case MP_BUS_PCI: /* PCI pin */
1043 /* set before the switch */
1046 case MP_BUS_MCA: /* MCA pin */
1048 trigger = default_MCA_trigger(idx);
1053 printk(KERN_WARNING "broken BIOS!!\n");
1066 case 2: /* reserved */
1068 printk(KERN_WARNING "broken BIOS!!\n");
1077 default: /* invalid */
1079 printk(KERN_WARNING "broken BIOS!!\n");
1087 static inline int irq_polarity(int idx)
1089 return MPBIOS_polarity(idx);
1092 static inline int irq_trigger(int idx)
1094 return MPBIOS_trigger(idx);
1097 static int pin_2_irq(int idx, int apic, int pin)
1100 int bus = mp_irqs[idx].mpc_srcbus;
1103 * Debugging check, we are in big trouble if this message pops up!
1105 if (mp_irqs[idx].mpc_dstirq != pin)
1106 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1108 if (test_bit(bus, mp_bus_not_pci))
1109 irq = mp_irqs[idx].mpc_srcbusirq;
1112 * PCI IRQs are mapped in order
1116 irq += nr_ioapic_registers[i++];
1120 * For MPS mode, so far only needed by ES7000 platform
1122 if (ioapic_renumber_irq)
1123 irq = ioapic_renumber_irq(apic, irq);
1127 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1129 if ((pin >= 16) && (pin <= 23)) {
1130 if (pirq_entries[pin-16] != -1) {
1131 if (!pirq_entries[pin-16]) {
1132 apic_printk(APIC_VERBOSE, KERN_DEBUG
1133 "disabling PIRQ%d\n", pin-16);
1135 irq = pirq_entries[pin-16];
1136 apic_printk(APIC_VERBOSE, KERN_DEBUG
1137 "using PIRQ%d -> IRQ %d\n",
1145 static inline int IO_APIC_irq_trigger(int irq)
1149 for (apic = 0; apic < nr_ioapics; apic++) {
1150 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1151 idx = find_irq_entry(apic,pin,mp_INT);
1152 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1153 return irq_trigger(idx);
1157 * nonexistent IRQs are edge default
1162 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1163 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1165 static int __assign_irq_vector(int irq)
1167 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1170 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1172 if (irq_vector[irq] > 0)
1173 return irq_vector[irq];
1175 vector = current_vector;
1176 offset = current_offset;
1179 if (vector >= FIRST_SYSTEM_VECTOR) {
1180 offset = (offset + 1) % 8;
1181 vector = FIRST_DEVICE_VECTOR + offset;
1183 if (vector == current_vector)
1185 if (test_and_set_bit(vector, used_vectors))
1188 current_vector = vector;
1189 current_offset = offset;
1190 irq_vector[irq] = vector;
1195 static int assign_irq_vector(int irq)
1197 unsigned long flags;
1200 spin_lock_irqsave(&vector_lock, flags);
1201 vector = __assign_irq_vector(irq);
1202 spin_unlock_irqrestore(&vector_lock, flags);
1206 static struct irq_chip ioapic_chip;
1208 #define IOAPIC_AUTO -1
1209 #define IOAPIC_EDGE 0
1210 #define IOAPIC_LEVEL 1
1212 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1214 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1215 trigger == IOAPIC_LEVEL) {
1216 irq_desc[irq].status |= IRQ_LEVEL;
1217 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1218 handle_fasteoi_irq, "fasteoi");
1220 irq_desc[irq].status &= ~IRQ_LEVEL;
1221 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1222 handle_edge_irq, "edge");
1224 set_intr_gate(vector, interrupt[irq]);
1227 static void __init setup_IO_APIC_irqs(void)
1229 struct IO_APIC_route_entry entry;
1230 int apic, pin, idx, irq, first_notcon = 1, vector;
1232 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1234 for (apic = 0; apic < nr_ioapics; apic++) {
1235 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1238 * add it to the IO-APIC irq-routing table:
1240 memset(&entry,0,sizeof(entry));
1242 entry.delivery_mode = INT_DELIVERY_MODE;
1243 entry.dest_mode = INT_DEST_MODE;
1244 entry.mask = 0; /* enable IRQ */
1245 entry.dest.logical.logical_dest =
1246 cpu_mask_to_apicid(TARGET_CPUS);
1248 idx = find_irq_entry(apic,pin,mp_INT);
1251 apic_printk(APIC_VERBOSE, KERN_DEBUG
1252 " IO-APIC (apicid-pin) %d-%d",
1253 mp_ioapics[apic].mpc_apicid,
1257 apic_printk(APIC_VERBOSE, ", %d-%d",
1258 mp_ioapics[apic].mpc_apicid, pin);
1262 if (!first_notcon) {
1263 apic_printk(APIC_VERBOSE, " not connected.\n");
1267 entry.trigger = irq_trigger(idx);
1268 entry.polarity = irq_polarity(idx);
1270 if (irq_trigger(idx)) {
1275 irq = pin_2_irq(idx, apic, pin);
1277 * skip adding the timer int on secondary nodes, which causes
1278 * a small but painful rift in the time-space continuum
1280 if (multi_timer_check(apic, irq))
1283 add_pin_to_irq(irq, apic, pin);
1285 if (!apic && !IO_APIC_IRQ(irq))
1288 if (IO_APIC_IRQ(irq)) {
1289 vector = assign_irq_vector(irq);
1290 entry.vector = vector;
1291 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1293 if (!apic && (irq < 16))
1294 disable_8259A_irq(irq);
1296 ioapic_write_entry(apic, pin, entry);
1301 apic_printk(APIC_VERBOSE, " not connected.\n");
1305 * Set up the 8259A-master output pin:
1307 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1309 struct IO_APIC_route_entry entry;
1311 memset(&entry,0,sizeof(entry));
1314 * We use logical delivery to get the timer IRQ
1317 entry.dest_mode = INT_DEST_MODE;
1318 entry.mask = 0; /* unmask IRQ now */
1319 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1320 entry.delivery_mode = INT_DELIVERY_MODE;
1323 entry.vector = vector;
1326 * The timer IRQ doesn't have to know that behind the
1327 * scene we have a 8259A-master in AEOI mode ...
1329 ioapic_register_intr(0, vector, IOAPIC_EDGE);
1332 * Add it to the IO-APIC irq-routing table:
1334 ioapic_write_entry(apic, pin, entry);
1337 void __init print_IO_APIC(void)
1340 union IO_APIC_reg_00 reg_00;
1341 union IO_APIC_reg_01 reg_01;
1342 union IO_APIC_reg_02 reg_02;
1343 union IO_APIC_reg_03 reg_03;
1344 unsigned long flags;
1346 if (apic_verbosity == APIC_QUIET)
1349 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1350 for (i = 0; i < nr_ioapics; i++)
1351 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1352 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1355 * We are a bit conservative about what we expect. We have to
1356 * know about every hardware change ASAP.
1358 printk(KERN_INFO "testing the IO APIC.......................\n");
1360 for (apic = 0; apic < nr_ioapics; apic++) {
1362 spin_lock_irqsave(&ioapic_lock, flags);
1363 reg_00.raw = io_apic_read(apic, 0);
1364 reg_01.raw = io_apic_read(apic, 1);
1365 if (reg_01.bits.version >= 0x10)
1366 reg_02.raw = io_apic_read(apic, 2);
1367 if (reg_01.bits.version >= 0x20)
1368 reg_03.raw = io_apic_read(apic, 3);
1369 spin_unlock_irqrestore(&ioapic_lock, flags);
1371 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1372 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1373 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1374 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1375 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1377 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1378 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1380 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1381 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1384 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1385 * but the value of reg_02 is read as the previous read register
1386 * value, so ignore it if reg_02 == reg_01.
1388 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1389 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1390 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1394 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1395 * or reg_03, but the value of reg_0[23] is read as the previous read
1396 * register value, so ignore it if reg_03 == reg_0[12].
1398 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1399 reg_03.raw != reg_01.raw) {
1400 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1401 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1404 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1406 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1407 " Stat Dest Deli Vect: \n");
1409 for (i = 0; i <= reg_01.bits.entries; i++) {
1410 struct IO_APIC_route_entry entry;
1412 entry = ioapic_read_entry(apic, i);
1414 printk(KERN_DEBUG " %02x %03X %02X ",
1416 entry.dest.logical.logical_dest,
1417 entry.dest.physical.physical_dest
1420 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1425 entry.delivery_status,
1427 entry.delivery_mode,
1432 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1433 for (i = 0; i < NR_IRQS; i++) {
1434 struct irq_pin_list *entry = irq_2_pin + i;
1437 printk(KERN_DEBUG "IRQ%d ", i);
1439 printk("-> %d:%d", entry->apic, entry->pin);
1442 entry = irq_2_pin + entry->next;
1447 printk(KERN_INFO ".................................... done.\n");
1454 static void print_APIC_bitfield (int base)
1459 if (apic_verbosity == APIC_QUIET)
1462 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1463 for (i = 0; i < 8; i++) {
1464 v = apic_read(base + i*0x10);
1465 for (j = 0; j < 32; j++) {
1475 void /*__init*/ print_local_APIC(void * dummy)
1477 unsigned int v, ver, maxlvt;
1479 if (apic_verbosity == APIC_QUIET)
1482 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1483 smp_processor_id(), hard_smp_processor_id());
1484 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1485 GET_APIC_ID(read_apic_id()));
1486 v = apic_read(APIC_LVR);
1487 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1488 ver = GET_APIC_VERSION(v);
1489 maxlvt = lapic_get_maxlvt();
1491 v = apic_read(APIC_TASKPRI);
1492 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1494 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1495 v = apic_read(APIC_ARBPRI);
1496 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1497 v & APIC_ARBPRI_MASK);
1498 v = apic_read(APIC_PROCPRI);
1499 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1502 v = apic_read(APIC_EOI);
1503 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1504 v = apic_read(APIC_RRR);
1505 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1506 v = apic_read(APIC_LDR);
1507 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1508 v = apic_read(APIC_DFR);
1509 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1510 v = apic_read(APIC_SPIV);
1511 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1513 printk(KERN_DEBUG "... APIC ISR field:\n");
1514 print_APIC_bitfield(APIC_ISR);
1515 printk(KERN_DEBUG "... APIC TMR field:\n");
1516 print_APIC_bitfield(APIC_TMR);
1517 printk(KERN_DEBUG "... APIC IRR field:\n");
1518 print_APIC_bitfield(APIC_IRR);
1520 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1521 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1522 apic_write(APIC_ESR, 0);
1523 v = apic_read(APIC_ESR);
1524 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1527 v = apic_read(APIC_ICR);
1528 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1529 v = apic_read(APIC_ICR2);
1530 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1532 v = apic_read(APIC_LVTT);
1533 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1535 if (maxlvt > 3) { /* PC is LVT#4. */
1536 v = apic_read(APIC_LVTPC);
1537 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1539 v = apic_read(APIC_LVT0);
1540 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1541 v = apic_read(APIC_LVT1);
1542 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1544 if (maxlvt > 2) { /* ERR is LVT#3. */
1545 v = apic_read(APIC_LVTERR);
1546 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1549 v = apic_read(APIC_TMICT);
1550 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1551 v = apic_read(APIC_TMCCT);
1552 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1553 v = apic_read(APIC_TDCR);
1554 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1558 void print_all_local_APICs (void)
1560 on_each_cpu(print_local_APIC, NULL, 1, 1);
1563 void /*__init*/ print_PIC(void)
1566 unsigned long flags;
1568 if (apic_verbosity == APIC_QUIET)
1571 printk(KERN_DEBUG "\nprinting PIC contents\n");
1573 spin_lock_irqsave(&i8259A_lock, flags);
1575 v = inb(0xa1) << 8 | inb(0x21);
1576 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1578 v = inb(0xa0) << 8 | inb(0x20);
1579 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1583 v = inb(0xa0) << 8 | inb(0x20);
1587 spin_unlock_irqrestore(&i8259A_lock, flags);
1589 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1591 v = inb(0x4d1) << 8 | inb(0x4d0);
1592 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1597 static void __init enable_IO_APIC(void)
1599 union IO_APIC_reg_01 reg_01;
1600 int i8259_apic, i8259_pin;
1602 unsigned long flags;
1604 for (i = 0; i < PIN_MAP_SIZE; i++) {
1605 irq_2_pin[i].pin = -1;
1606 irq_2_pin[i].next = 0;
1609 for (i = 0; i < MAX_PIRQS; i++)
1610 pirq_entries[i] = -1;
1613 * The number of IO-APIC IRQ registers (== #pins):
1615 for (apic = 0; apic < nr_ioapics; apic++) {
1616 spin_lock_irqsave(&ioapic_lock, flags);
1617 reg_01.raw = io_apic_read(apic, 1);
1618 spin_unlock_irqrestore(&ioapic_lock, flags);
1619 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1621 for(apic = 0; apic < nr_ioapics; apic++) {
1623 /* See if any of the pins is in ExtINT mode */
1624 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1625 struct IO_APIC_route_entry entry;
1626 entry = ioapic_read_entry(apic, pin);
1629 /* If the interrupt line is enabled and in ExtInt mode
1630 * I have found the pin where the i8259 is connected.
1632 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1633 ioapic_i8259.apic = apic;
1634 ioapic_i8259.pin = pin;
1640 /* Look to see what if the MP table has reported the ExtINT */
1641 /* If we could not find the appropriate pin by looking at the ioapic
1642 * the i8259 probably is not connected the ioapic but give the
1643 * mptable a chance anyway.
1645 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1646 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1647 /* Trust the MP table if nothing is setup in the hardware */
1648 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1649 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1650 ioapic_i8259.pin = i8259_pin;
1651 ioapic_i8259.apic = i8259_apic;
1653 /* Complain if the MP table and the hardware disagree */
1654 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1655 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1657 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1661 * Do not trust the IO-APIC being empty at bootup
1667 * Not an __init, needed by the reboot code
1669 void disable_IO_APIC(void)
1672 * Clear the IO-APIC before rebooting:
1677 * If the i8259 is routed through an IOAPIC
1678 * Put that IOAPIC in virtual wire mode
1679 * so legacy interrupts can be delivered.
1681 if (ioapic_i8259.pin != -1) {
1682 struct IO_APIC_route_entry entry;
1684 memset(&entry, 0, sizeof(entry));
1685 entry.mask = 0; /* Enabled */
1686 entry.trigger = 0; /* Edge */
1688 entry.polarity = 0; /* High */
1689 entry.delivery_status = 0;
1690 entry.dest_mode = 0; /* Physical */
1691 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1693 entry.dest.physical.physical_dest =
1694 GET_APIC_ID(read_apic_id());
1697 * Add it to the IO-APIC irq-routing table:
1699 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1701 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1705 * function to set the IO-APIC physical IDs based on the
1706 * values stored in the MPC table.
1708 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1711 #ifndef CONFIG_X86_NUMAQ
1712 static void __init setup_ioapic_ids_from_mpc(void)
1714 union IO_APIC_reg_00 reg_00;
1715 physid_mask_t phys_id_present_map;
1718 unsigned char old_id;
1719 unsigned long flags;
1722 * Don't check I/O APIC IDs for xAPIC systems. They have
1723 * no meaning without the serial APIC bus.
1725 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1726 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1729 * This is broken; anything with a real cpu count has to
1730 * circumvent this idiocy regardless.
1732 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1735 * Set the IOAPIC ID to the value stored in the MPC table.
1737 for (apic = 0; apic < nr_ioapics; apic++) {
1739 /* Read the register 0 value */
1740 spin_lock_irqsave(&ioapic_lock, flags);
1741 reg_00.raw = io_apic_read(apic, 0);
1742 spin_unlock_irqrestore(&ioapic_lock, flags);
1744 old_id = mp_ioapics[apic].mpc_apicid;
1746 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1747 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1748 apic, mp_ioapics[apic].mpc_apicid);
1749 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1751 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1755 * Sanity check, is the ID really free? Every APIC in a
1756 * system must have a unique ID or we get lots of nice
1757 * 'stuck on smp_invalidate_needed IPI wait' messages.
1759 if (check_apicid_used(phys_id_present_map,
1760 mp_ioapics[apic].mpc_apicid)) {
1761 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1762 apic, mp_ioapics[apic].mpc_apicid);
1763 for (i = 0; i < get_physical_broadcast(); i++)
1764 if (!physid_isset(i, phys_id_present_map))
1766 if (i >= get_physical_broadcast())
1767 panic("Max APIC ID exceeded!\n");
1768 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1770 physid_set(i, phys_id_present_map);
1771 mp_ioapics[apic].mpc_apicid = i;
1774 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1775 apic_printk(APIC_VERBOSE, "Setting %d in the "
1776 "phys_id_present_map\n",
1777 mp_ioapics[apic].mpc_apicid);
1778 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1783 * We need to adjust the IRQ routing table
1784 * if the ID changed.
1786 if (old_id != mp_ioapics[apic].mpc_apicid)
1787 for (i = 0; i < mp_irq_entries; i++)
1788 if (mp_irqs[i].mpc_dstapic == old_id)
1789 mp_irqs[i].mpc_dstapic
1790 = mp_ioapics[apic].mpc_apicid;
1793 * Read the right value from the MPC table and
1794 * write it into the ID register.
1796 apic_printk(APIC_VERBOSE, KERN_INFO
1797 "...changing IO-APIC physical APIC ID to %d ...",
1798 mp_ioapics[apic].mpc_apicid);
1800 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1801 spin_lock_irqsave(&ioapic_lock, flags);
1802 io_apic_write(apic, 0, reg_00.raw);
1803 spin_unlock_irqrestore(&ioapic_lock, flags);
1808 spin_lock_irqsave(&ioapic_lock, flags);
1809 reg_00.raw = io_apic_read(apic, 0);
1810 spin_unlock_irqrestore(&ioapic_lock, flags);
1811 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1812 printk("could not set ID!\n");
1814 apic_printk(APIC_VERBOSE, " ok.\n");
1818 static void __init setup_ioapic_ids_from_mpc(void) { }
1821 int no_timer_check __initdata;
1823 static int __init notimercheck(char *s)
1828 __setup("no_timer_check", notimercheck);
1831 * There is a nasty bug in some older SMP boards, their mptable lies
1832 * about the timer IRQ. We do the following to work around the situation:
1834 * - timer IRQ defaults to IO-APIC IRQ
1835 * - if this function detects that timer IRQs are defunct, then we fall
1836 * back to ISA timer IRQs
1838 static int __init timer_irq_works(void)
1840 unsigned long t1 = jiffies;
1841 unsigned long flags;
1846 local_save_flags(flags);
1848 /* Let ten ticks pass... */
1849 mdelay((10 * 1000) / HZ);
1850 local_irq_restore(flags);
1853 * Expect a few ticks at least, to be sure some possible
1854 * glue logic does not lock up after one or two first
1855 * ticks in a non-ExtINT mode. Also the local APIC
1856 * might have cached one ExtINT interrupt. Finally, at
1857 * least one tick may be lost due to delays.
1859 if (time_after(jiffies, t1 + 4))
1866 * In the SMP+IOAPIC case it might happen that there are an unspecified
1867 * number of pending IRQ events unhandled. These cases are very rare,
1868 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1869 * better to do it this way as thus we do not have to be aware of
1870 * 'pending' interrupts in the IRQ path, except at this point.
1873 * Edge triggered needs to resend any interrupt
1874 * that was delayed but this is now handled in the device
1881 * Starting up a edge-triggered IO-APIC interrupt is
1882 * nasty - we need to make sure that we get the edge.
1883 * If it is already asserted for some reason, we need
1884 * return 1 to indicate that is was pending.
1886 * This is not complete - we should be able to fake
1887 * an edge even if it isn't on the 8259A...
1889 * (We do this for level-triggered IRQs too - it cannot hurt.)
1891 static unsigned int startup_ioapic_irq(unsigned int irq)
1893 int was_pending = 0;
1894 unsigned long flags;
1896 spin_lock_irqsave(&ioapic_lock, flags);
1898 disable_8259A_irq(irq);
1899 if (i8259A_irq_pending(irq))
1902 __unmask_IO_APIC_irq(irq);
1903 spin_unlock_irqrestore(&ioapic_lock, flags);
1908 static void ack_ioapic_irq(unsigned int irq)
1910 move_native_irq(irq);
1914 static void ack_ioapic_quirk_irq(unsigned int irq)
1919 move_native_irq(irq);
1921 * It appears there is an erratum which affects at least version 0x11
1922 * of I/O APIC (that's the 82093AA and cores integrated into various
1923 * chipsets). Under certain conditions a level-triggered interrupt is
1924 * erroneously delivered as edge-triggered one but the respective IRR
1925 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1926 * message but it will never arrive and further interrupts are blocked
1927 * from the source. The exact reason is so far unknown, but the
1928 * phenomenon was observed when two consecutive interrupt requests
1929 * from a given source get delivered to the same CPU and the source is
1930 * temporarily disabled in between.
1932 * A workaround is to simulate an EOI message manually. We achieve it
1933 * by setting the trigger mode to edge and then to level when the edge
1934 * trigger mode gets detected in the TMR of a local APIC for a
1935 * level-triggered interrupt. We mask the source for the time of the
1936 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1937 * The idea is from Manfred Spraul. --macro
1939 i = irq_vector[irq];
1941 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1945 if (!(v & (1 << (i & 0x1f)))) {
1946 atomic_inc(&irq_mis_count);
1947 spin_lock(&ioapic_lock);
1948 __mask_and_edge_IO_APIC_irq(irq);
1949 __unmask_and_level_IO_APIC_irq(irq);
1950 spin_unlock(&ioapic_lock);
1954 static int ioapic_retrigger_irq(unsigned int irq)
1956 send_IPI_self(irq_vector[irq]);
1961 static struct irq_chip ioapic_chip __read_mostly = {
1963 .startup = startup_ioapic_irq,
1964 .mask = mask_IO_APIC_irq,
1965 .unmask = unmask_IO_APIC_irq,
1966 .ack = ack_ioapic_irq,
1967 .eoi = ack_ioapic_quirk_irq,
1969 .set_affinity = set_ioapic_affinity_irq,
1971 .retrigger = ioapic_retrigger_irq,
1975 static inline void init_IO_APIC_traps(void)
1980 * NOTE! The local APIC isn't very good at handling
1981 * multiple interrupts at the same interrupt level.
1982 * As the interrupt level is determined by taking the
1983 * vector number and shifting that right by 4, we
1984 * want to spread these out a bit so that they don't
1985 * all fall in the same interrupt level.
1987 * Also, we've got to be careful not to trash gate
1988 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1990 for (irq = 0; irq < NR_IRQS ; irq++) {
1991 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
1993 * Hmm.. We don't have an entry for this,
1994 * so default to an old-fashioned 8259
1995 * interrupt if we can..
1998 make_8259A_irq(irq);
2000 /* Strange. Oh, well.. */
2001 irq_desc[irq].chip = &no_irq_chip;
2007 * The local APIC irq-chip implementation:
2010 static void ack_apic(unsigned int irq)
2015 static void mask_lapic_irq (unsigned int irq)
2019 v = apic_read(APIC_LVT0);
2020 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2023 static void unmask_lapic_irq (unsigned int irq)
2027 v = apic_read(APIC_LVT0);
2028 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2031 static struct irq_chip lapic_chip __read_mostly = {
2032 .name = "local-APIC",
2033 .mask = mask_lapic_irq,
2034 .unmask = unmask_lapic_irq,
2038 static void __init setup_nmi(void)
2041 * Dirty trick to enable the NMI watchdog ...
2042 * We put the 8259A master into AEOI mode and
2043 * unmask on all local APICs LVT0 as NMI.
2045 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2046 * is from Maciej W. Rozycki - so we do not have to EOI from
2047 * the NMI handler or the timer interrupt.
2049 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2051 enable_NMI_through_LVT0();
2053 apic_printk(APIC_VERBOSE, " done.\n");
2057 * This looks a bit hackish but it's about the only one way of sending
2058 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2059 * not support the ExtINT mode, unfortunately. We need to send these
2060 * cycles as some i82489DX-based boards have glue logic that keeps the
2061 * 8259A interrupt line asserted until INTA. --macro
2063 static inline void __init unlock_ExtINT_logic(void)
2066 struct IO_APIC_route_entry entry0, entry1;
2067 unsigned char save_control, save_freq_select;
2069 pin = find_isa_irq_pin(8, mp_INT);
2074 apic = find_isa_irq_apic(8, mp_INT);
2080 entry0 = ioapic_read_entry(apic, pin);
2081 clear_IO_APIC_pin(apic, pin);
2083 memset(&entry1, 0, sizeof(entry1));
2085 entry1.dest_mode = 0; /* physical delivery */
2086 entry1.mask = 0; /* unmask IRQ now */
2087 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2088 entry1.delivery_mode = dest_ExtINT;
2089 entry1.polarity = entry0.polarity;
2093 ioapic_write_entry(apic, pin, entry1);
2095 save_control = CMOS_READ(RTC_CONTROL);
2096 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2097 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2099 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2104 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2108 CMOS_WRITE(save_control, RTC_CONTROL);
2109 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2110 clear_IO_APIC_pin(apic, pin);
2112 ioapic_write_entry(apic, pin, entry0);
2116 * This code may look a bit paranoid, but it's supposed to cooperate with
2117 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2118 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2119 * fanatically on his truly buggy board.
2121 static inline void __init check_timer(void)
2123 int apic1, pin1, apic2, pin2;
2126 unsigned long flags;
2128 local_irq_save(flags);
2130 ver = apic_read(APIC_LVR);
2131 ver = GET_APIC_VERSION(ver);
2134 * get/set the timer IRQ vector:
2136 disable_8259A_irq(0);
2137 vector = assign_irq_vector(0);
2138 set_intr_gate(vector, interrupt[0]);
2141 * As IRQ0 is to be enabled in the 8259A, the virtual
2142 * wire has to be disabled in the local APIC. Also
2143 * timer interrupts need to be acknowledged manually in
2144 * the 8259A for the i82489DX when using the NMI
2145 * watchdog as that APIC treats NMIs as level-triggered.
2146 * The AEOI mode will finish them in the 8259A
2149 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2151 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2153 pin1 = find_isa_irq_pin(0, mp_INT);
2154 apic1 = find_isa_irq_apic(0, mp_INT);
2155 pin2 = ioapic_i8259.pin;
2156 apic2 = ioapic_i8259.apic;
2158 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2159 vector, apic1, pin1, apic2, pin2);
2163 * Ok, does IRQ0 through the IOAPIC work?
2165 unmask_IO_APIC_irq(0);
2166 if (timer_irq_works()) {
2167 if (nmi_watchdog == NMI_IO_APIC) {
2169 enable_8259A_irq(0);
2171 if (disable_timer_pin_1 > 0)
2172 clear_IO_APIC_pin(0, pin1);
2175 clear_IO_APIC_pin(apic1, pin1);
2176 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2180 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2182 printk("\n..... (found pin %d) ...", pin2);
2184 * legacy devices should be connected to IO APIC #0
2186 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2187 enable_8259A_irq(0);
2188 if (timer_irq_works()) {
2190 timer_through_8259 = 1;
2192 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2194 add_pin_to_irq(0, apic2, pin2);
2195 if (nmi_watchdog == NMI_IO_APIC) {
2196 disable_8259A_irq(0);
2198 enable_8259A_irq(0);
2203 * Cleanup, just in case ...
2205 disable_8259A_irq(0);
2206 clear_IO_APIC_pin(apic2, pin2);
2208 printk(" failed.\n");
2210 if (nmi_watchdog == NMI_IO_APIC) {
2211 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2216 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2218 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2220 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2221 enable_8259A_irq(0);
2223 if (timer_irq_works()) {
2224 printk(" works.\n");
2227 disable_8259A_irq(0);
2228 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2229 printk(" failed.\n");
2231 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2235 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2237 unlock_ExtINT_logic();
2239 if (timer_irq_works()) {
2240 printk(" works.\n");
2243 printk(" failed :(.\n");
2244 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2245 "report. Then try booting with the 'noapic' option");
2247 local_irq_restore(flags);
2252 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2253 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2254 * Linux doesn't really care, as it's not actually used
2255 * for any interrupt handling anyway.
2257 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2259 void __init setup_IO_APIC(void)
2263 /* Reserve all the system vectors. */
2264 for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2265 set_bit(i, used_vectors);
2270 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2272 io_apic_irqs = ~PIC_IRQS;
2274 printk("ENABLING IO-APIC IRQs\n");
2277 * Set up IO-APIC IRQ routing.
2280 setup_ioapic_ids_from_mpc();
2282 setup_IO_APIC_irqs();
2283 init_IO_APIC_traps();
2290 * Called after all the initialization is done. If we didnt find any
2291 * APIC bugs then we can allow the modify fast path
2294 static int __init io_apic_bug_finalize(void)
2296 if(sis_apic_bug == -1)
2301 late_initcall(io_apic_bug_finalize);
2303 struct sysfs_ioapic_data {
2304 struct sys_device dev;
2305 struct IO_APIC_route_entry entry[0];
2307 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2309 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2311 struct IO_APIC_route_entry *entry;
2312 struct sysfs_ioapic_data *data;
2315 data = container_of(dev, struct sysfs_ioapic_data, dev);
2316 entry = data->entry;
2317 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2318 entry[i] = ioapic_read_entry(dev->id, i);
2323 static int ioapic_resume(struct sys_device *dev)
2325 struct IO_APIC_route_entry *entry;
2326 struct sysfs_ioapic_data *data;
2327 unsigned long flags;
2328 union IO_APIC_reg_00 reg_00;
2331 data = container_of(dev, struct sysfs_ioapic_data, dev);
2332 entry = data->entry;
2334 spin_lock_irqsave(&ioapic_lock, flags);
2335 reg_00.raw = io_apic_read(dev->id, 0);
2336 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2337 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2338 io_apic_write(dev->id, 0, reg_00.raw);
2340 spin_unlock_irqrestore(&ioapic_lock, flags);
2341 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2342 ioapic_write_entry(dev->id, i, entry[i]);
2347 static struct sysdev_class ioapic_sysdev_class = {
2349 .suspend = ioapic_suspend,
2350 .resume = ioapic_resume,
2353 static int __init ioapic_init_sysfs(void)
2355 struct sys_device * dev;
2356 int i, size, error = 0;
2358 error = sysdev_class_register(&ioapic_sysdev_class);
2362 for (i = 0; i < nr_ioapics; i++ ) {
2363 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2364 * sizeof(struct IO_APIC_route_entry);
2365 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2366 if (!mp_ioapic_data[i]) {
2367 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2370 memset(mp_ioapic_data[i], 0, size);
2371 dev = &mp_ioapic_data[i]->dev;
2373 dev->cls = &ioapic_sysdev_class;
2374 error = sysdev_register(dev);
2376 kfree(mp_ioapic_data[i]);
2377 mp_ioapic_data[i] = NULL;
2378 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2386 device_initcall(ioapic_init_sysfs);
2389 * Dynamic irq allocate and deallocation
2391 int create_irq(void)
2393 /* Allocate an unused irq */
2394 int irq, new, vector = 0;
2395 unsigned long flags;
2398 spin_lock_irqsave(&vector_lock, flags);
2399 for (new = (NR_IRQS - 1); new >= 0; new--) {
2400 if (platform_legacy_irq(new))
2402 if (irq_vector[new] != 0)
2404 vector = __assign_irq_vector(new);
2405 if (likely(vector > 0))
2409 spin_unlock_irqrestore(&vector_lock, flags);
2412 set_intr_gate(vector, interrupt[irq]);
2413 dynamic_irq_init(irq);
2418 void destroy_irq(unsigned int irq)
2420 unsigned long flags;
2422 dynamic_irq_cleanup(irq);
2424 spin_lock_irqsave(&vector_lock, flags);
2425 clear_bit(irq_vector[irq], used_vectors);
2426 irq_vector[irq] = 0;
2427 spin_unlock_irqrestore(&vector_lock, flags);
2431 * MSI message composition
2433 #ifdef CONFIG_PCI_MSI
2434 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2439 vector = assign_irq_vector(irq);
2441 dest = cpu_mask_to_apicid(TARGET_CPUS);
2443 msg->address_hi = MSI_ADDR_BASE_HI;
2446 ((INT_DEST_MODE == 0) ?
2447 MSI_ADDR_DEST_MODE_PHYSICAL:
2448 MSI_ADDR_DEST_MODE_LOGICAL) |
2449 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2450 MSI_ADDR_REDIRECTION_CPU:
2451 MSI_ADDR_REDIRECTION_LOWPRI) |
2452 MSI_ADDR_DEST_ID(dest);
2455 MSI_DATA_TRIGGER_EDGE |
2456 MSI_DATA_LEVEL_ASSERT |
2457 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2458 MSI_DATA_DELIVERY_FIXED:
2459 MSI_DATA_DELIVERY_LOWPRI) |
2460 MSI_DATA_VECTOR(vector);
2466 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2473 cpus_and(tmp, mask, cpu_online_map);
2474 if (cpus_empty(tmp))
2477 vector = assign_irq_vector(irq);
2481 dest = cpu_mask_to_apicid(mask);
2483 read_msi_msg(irq, &msg);
2485 msg.data &= ~MSI_DATA_VECTOR_MASK;
2486 msg.data |= MSI_DATA_VECTOR(vector);
2487 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2488 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2490 write_msi_msg(irq, &msg);
2491 irq_desc[irq].affinity = mask;
2493 #endif /* CONFIG_SMP */
2496 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2497 * which implement the MSI or MSI-X Capability Structure.
2499 static struct irq_chip msi_chip = {
2501 .unmask = unmask_msi_irq,
2502 .mask = mask_msi_irq,
2503 .ack = ack_ioapic_irq,
2505 .set_affinity = set_msi_irq_affinity,
2507 .retrigger = ioapic_retrigger_irq,
2510 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2518 ret = msi_compose_msg(dev, irq, &msg);
2524 set_irq_msi(irq, desc);
2525 write_msi_msg(irq, &msg);
2527 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2533 void arch_teardown_msi_irq(unsigned int irq)
2538 #endif /* CONFIG_PCI_MSI */
2541 * Hypertransport interrupt support
2543 #ifdef CONFIG_HT_IRQ
2547 static void target_ht_irq(unsigned int irq, unsigned int dest)
2549 struct ht_irq_msg msg;
2550 fetch_ht_irq_msg(irq, &msg);
2552 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2553 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2555 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2556 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2558 write_ht_irq_msg(irq, &msg);
2561 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2566 cpus_and(tmp, mask, cpu_online_map);
2567 if (cpus_empty(tmp))
2570 cpus_and(mask, tmp, CPU_MASK_ALL);
2572 dest = cpu_mask_to_apicid(mask);
2574 target_ht_irq(irq, dest);
2575 irq_desc[irq].affinity = mask;
2579 static struct irq_chip ht_irq_chip = {
2581 .mask = mask_ht_irq,
2582 .unmask = unmask_ht_irq,
2583 .ack = ack_ioapic_irq,
2585 .set_affinity = set_ht_irq_affinity,
2587 .retrigger = ioapic_retrigger_irq,
2590 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2594 vector = assign_irq_vector(irq);
2596 struct ht_irq_msg msg;
2601 cpu_set(vector >> 8, tmp);
2602 dest = cpu_mask_to_apicid(tmp);
2604 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2608 HT_IRQ_LOW_DEST_ID(dest) |
2609 HT_IRQ_LOW_VECTOR(vector) |
2610 ((INT_DEST_MODE == 0) ?
2611 HT_IRQ_LOW_DM_PHYSICAL :
2612 HT_IRQ_LOW_DM_LOGICAL) |
2613 HT_IRQ_LOW_RQEOI_EDGE |
2614 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2615 HT_IRQ_LOW_MT_FIXED :
2616 HT_IRQ_LOW_MT_ARBITRATED) |
2617 HT_IRQ_LOW_IRQ_MASKED;
2619 write_ht_irq_msg(irq, &msg);
2621 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2622 handle_edge_irq, "edge");
2626 #endif /* CONFIG_HT_IRQ */
2628 /* --------------------------------------------------------------------------
2629 ACPI-based IOAPIC Configuration
2630 -------------------------------------------------------------------------- */
2634 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2636 union IO_APIC_reg_00 reg_00;
2637 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2639 unsigned long flags;
2643 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2644 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2645 * supports up to 16 on one shared APIC bus.
2647 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2648 * advantage of new APIC bus architecture.
2651 if (physids_empty(apic_id_map))
2652 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2654 spin_lock_irqsave(&ioapic_lock, flags);
2655 reg_00.raw = io_apic_read(ioapic, 0);
2656 spin_unlock_irqrestore(&ioapic_lock, flags);
2658 if (apic_id >= get_physical_broadcast()) {
2659 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2660 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2661 apic_id = reg_00.bits.ID;
2665 * Every APIC in a system must have a unique ID or we get lots of nice
2666 * 'stuck on smp_invalidate_needed IPI wait' messages.
2668 if (check_apicid_used(apic_id_map, apic_id)) {
2670 for (i = 0; i < get_physical_broadcast(); i++) {
2671 if (!check_apicid_used(apic_id_map, i))
2675 if (i == get_physical_broadcast())
2676 panic("Max apic_id exceeded!\n");
2678 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2679 "trying %d\n", ioapic, apic_id, i);
2684 tmp = apicid_to_cpu_present(apic_id);
2685 physids_or(apic_id_map, apic_id_map, tmp);
2687 if (reg_00.bits.ID != apic_id) {
2688 reg_00.bits.ID = apic_id;
2690 spin_lock_irqsave(&ioapic_lock, flags);
2691 io_apic_write(ioapic, 0, reg_00.raw);
2692 reg_00.raw = io_apic_read(ioapic, 0);
2693 spin_unlock_irqrestore(&ioapic_lock, flags);
2696 if (reg_00.bits.ID != apic_id) {
2697 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2702 apic_printk(APIC_VERBOSE, KERN_INFO
2703 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2709 int __init io_apic_get_version (int ioapic)
2711 union IO_APIC_reg_01 reg_01;
2712 unsigned long flags;
2714 spin_lock_irqsave(&ioapic_lock, flags);
2715 reg_01.raw = io_apic_read(ioapic, 1);
2716 spin_unlock_irqrestore(&ioapic_lock, flags);
2718 return reg_01.bits.version;
2722 int __init io_apic_get_redir_entries (int ioapic)
2724 union IO_APIC_reg_01 reg_01;
2725 unsigned long flags;
2727 spin_lock_irqsave(&ioapic_lock, flags);
2728 reg_01.raw = io_apic_read(ioapic, 1);
2729 spin_unlock_irqrestore(&ioapic_lock, flags);
2731 return reg_01.bits.entries;
2735 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2737 struct IO_APIC_route_entry entry;
2739 if (!IO_APIC_IRQ(irq)) {
2740 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2746 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2747 * Note that we mask (disable) IRQs now -- these get enabled when the
2748 * corresponding device driver registers for this IRQ.
2751 memset(&entry,0,sizeof(entry));
2753 entry.delivery_mode = INT_DELIVERY_MODE;
2754 entry.dest_mode = INT_DEST_MODE;
2755 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2756 entry.trigger = edge_level;
2757 entry.polarity = active_high_low;
2761 * IRQs < 16 are already in the irq_2_pin[] map
2764 add_pin_to_irq(irq, ioapic, pin);
2766 entry.vector = assign_irq_vector(irq);
2768 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2769 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2770 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2771 edge_level, active_high_low);
2773 ioapic_register_intr(irq, entry.vector, edge_level);
2775 if (!ioapic && (irq < 16))
2776 disable_8259A_irq(irq);
2778 ioapic_write_entry(ioapic, pin, entry);
2783 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2787 if (skip_ioapic_setup)
2790 for (i = 0; i < mp_irq_entries; i++)
2791 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2792 mp_irqs[i].mpc_srcbusirq == bus_irq)
2794 if (i >= mp_irq_entries)
2797 *trigger = irq_trigger(i);
2798 *polarity = irq_polarity(i);
2802 #endif /* CONFIG_ACPI */
2804 static int __init parse_disable_timer_pin_1(char *arg)
2806 disable_timer_pin_1 = 1;
2809 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2811 static int __init parse_enable_timer_pin_1(char *arg)
2813 disable_timer_pin_1 = -1;
2816 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2818 static int __init parse_noapic(char *arg)
2820 /* disable IO-APIC */
2821 disable_ioapic_setup();
2824 early_param("noapic", parse_noapic);