1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
13 #include <asm/uaccess.h>
14 #include <asm/ptrace.h>
19 #ifdef CONFIG_X86_LOCAL_APIC
20 #include <asm/mpspec.h>
22 #include <mach_apic.h>
25 #ifdef CONFIG_X86_INTEL_USERCOPY
27 * Alignment at which movsl is preferred for bulk memory copies.
29 struct movsl_mask movsl_mask __read_mostly;
32 void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
34 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
35 if (c->x86 == 15 && c->x86_cache_alignment == 64)
36 c->x86_cache_alignment = 128;
37 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
38 (c->x86 == 0x6 && c->x86_model >= 0x0e))
39 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
43 * Early probe support logic for ppro memory erratum #50
45 * This is called before we do cpu ident work
48 int __cpuinit ppro_with_ram_bug(void)
50 /* Uses data from early_cpu_detect now */
51 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
52 boot_cpu_data.x86 == 6 &&
53 boot_cpu_data.x86_model == 1 &&
54 boot_cpu_data.x86_mask < 8) {
55 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
63 * P4 Xeon errata 037 workaround.
64 * Hardware prefetcher may cause stale data to be loaded into the cache.
66 static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
70 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
71 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
72 if ((lo & (1<<9)) == 0) {
73 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
74 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
75 lo |= (1<<9); /* Disable hw prefetching */
76 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
83 * find out the number of processor cores on the die
85 static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
87 unsigned int eax, ebx, ecx, edx;
89 if (c->cpuid_level < 4)
92 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
93 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
95 return ((eax >> 26) + 1);
100 #ifdef CONFIG_X86_F00F_BUG
101 static void __cpuinit trap_init_f00f_bug(void)
103 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
106 * Update the IDT descriptor and reload the IDT so that
107 * it uses the read-only mapped virtual address.
109 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
110 load_idt(&idt_descr);
114 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
121 #ifdef CONFIG_X86_F00F_BUG
123 * All current models of Pentium and Pentium with MMX technology CPUs
124 * have the F0 0F bug, which lets nonprivileged users lock up the system.
125 * Note that the workaround only should be initialized once...
128 if (!paravirt_enabled() && c->x86 == 5) {
129 static int f00f_workaround_enabled = 0;
132 if ( !f00f_workaround_enabled ) {
133 trap_init_f00f_bug();
134 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
135 f00f_workaround_enabled = 1;
140 l2 = init_intel_cacheinfo(c);
141 if (c->cpuid_level > 9 ) {
142 unsigned eax = cpuid_eax(10);
143 /* Check for version and the number of counters */
144 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
145 set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
148 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
149 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
150 clear_bit(X86_FEATURE_SEP, c->x86_capability);
152 /* Names for the Pentium II/Celeron processors
153 detectable only by also checking the cache size.
154 Dixon is NOT a Celeron. */
156 switch (c->x86_model) {
158 if (c->x86_mask == 0) {
160 p = "Celeron (Covington)";
162 p = "Mobile Pentium II (Dixon)";
168 p = "Celeron (Mendocino)";
169 else if (c->x86_mask == 0 || c->x86_mask == 5)
175 p = "Celeron (Coppermine)";
181 strcpy(c->x86_model_id, p);
183 c->x86_max_cores = num_cpu_cores(c);
187 /* Work around errata */
188 Intel_errata_workarounds(c);
190 #ifdef CONFIG_X86_INTEL_USERCOPY
192 * Set up the preferred alignment for movsl bulk memory moves
195 case 4: /* 486: untested */
197 case 5: /* Old Pentia: untested */
199 case 6: /* PII/PIII only like movsl with 8-byte alignment */
202 case 15: /* P4 is OK down to 8-byte alignment */
209 set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability);
211 set_bit(X86_FEATURE_P4, c->x86_capability);
214 set_bit(X86_FEATURE_P3, c->x86_capability);
217 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
219 set_bit(X86_FEATURE_BTS, c->x86_capability);
221 set_bit(X86_FEATURE_PEBS, c->x86_capability);
228 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
230 /* Intel PIII Tualatin. This comes in two flavours.
231 * One has 256kb of cache, the other 512. We have no way
232 * to determine which, so we use a boottime override
233 * for the 512kb model, and assume 256 otherwise.
235 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
240 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
242 .c_ident = { "GenuineIntel" },
244 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
246 [0] = "486 DX-25/33",
257 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
259 [0] = "Pentium 60/66 A-step",
260 [1] = "Pentium 60/66",
261 [2] = "Pentium 75 - 200",
262 [3] = "OverDrive PODP5V83",
264 [7] = "Mobile Pentium 75 - 200",
265 [8] = "Mobile Pentium MMX"
268 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
270 [0] = "Pentium Pro A-step",
272 [3] = "Pentium II (Klamath)",
273 [4] = "Pentium II (Deschutes)",
274 [5] = "Pentium II (Deschutes)",
275 [6] = "Mobile Pentium II",
276 [7] = "Pentium III (Katmai)",
277 [8] = "Pentium III (Coppermine)",
278 [10] = "Pentium III (Cascades)",
279 [11] = "Pentium III (Tualatin)",
282 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
284 [0] = "Pentium 4 (Unknown)",
285 [1] = "Pentium 4 (Willamette)",
286 [2] = "Pentium 4 (Northwood)",
287 [4] = "Pentium 4 (Foster)",
288 [5] = "Pentium 4 (Foster)",
292 .c_init = init_intel,
293 .c_size_cache = intel_size_cache,
296 __init int intel_cpu_init(void)
298 cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
302 #ifndef CONFIG_X86_CMPXCHG
303 unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
308 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
309 local_irq_save(flags);
313 local_irq_restore(flags);
316 EXPORT_SYMBOL(cmpxchg_386_u8);
318 unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
323 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
324 local_irq_save(flags);
328 local_irq_restore(flags);
331 EXPORT_SYMBOL(cmpxchg_386_u16);
333 unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
338 /* Poor man's cmpxchg for 386. Unsuitable for SMP */
339 local_irq_save(flags);
343 local_irq_restore(flags);
346 EXPORT_SYMBOL(cmpxchg_386_u32);
349 #ifndef CONFIG_X86_CMPXCHG64
350 unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
355 /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
356 local_irq_save(flags);
360 local_irq_restore(flags);
363 EXPORT_SYMBOL(cmpxchg_486_u64);
366 // arch_initcall(intel_cpu_init);