1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
24 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
25 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
26 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
27 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
28 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
30 * Segments used for calling PnP BIOS have byte granularity.
31 * They code segments and data segments have fixed 64k limits,
32 * the transfer segment sizes are set at run time.
35 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
37 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
39 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
41 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
43 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
45 * The APM segments have byte granularity and their bases
46 * are set at run time. All have 64k limits.
49 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
51 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
53 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
55 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
56 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
58 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
60 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
62 static int cachesize_override __cpuinitdata = -1;
63 static int disable_x86_serial_nr __cpuinitdata = 1;
65 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
67 static void __cpuinit default_init(struct cpuinfo_x86 *c)
69 /* Not much we can do here... */
70 /* Check if at least it has cpuid */
71 if (c->cpuid_level == -1) {
72 /* No cpuid. It must be an ancient CPU */
74 strcpy(c->x86_model_id, "486");
76 strcpy(c->x86_model_id, "386");
80 static struct cpu_dev __cpuinitdata default_cpu = {
81 .c_init = default_init,
82 .c_vendor = "Unknown",
84 static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
86 static int __init cachesize_setup(char *str)
88 get_option(&str, &cachesize_override);
91 __setup("cachesize=", cachesize_setup);
93 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
98 if (cpuid_eax(0x80000000) < 0x80000004)
101 v = (unsigned int *) c->x86_model_id;
102 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
103 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
104 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
105 c->x86_model_id[48] = 0;
107 /* Intel chips right-justify this string for some dumb reason;
108 undo that brain damage */
109 p = q = &c->x86_model_id[0];
115 while (q <= &c->x86_model_id[48])
116 *q++ = '\0'; /* Zero-pad the rest */
123 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
125 unsigned int n, dummy, ecx, edx, l2size;
127 n = cpuid_eax(0x80000000);
129 if (n >= 0x80000005) {
130 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
131 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
132 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
133 c->x86_cache_size = (ecx>>24)+(edx>>24);
136 if (n < 0x80000006) /* Some chips just has a large L1. */
139 ecx = cpuid_ecx(0x80000006);
142 /* do processor-specific cache resizing */
143 if (this_cpu->c_size_cache)
144 l2size = this_cpu->c_size_cache(c, l2size);
146 /* Allow user to override all this if necessary. */
147 if (cachesize_override != -1)
148 l2size = cachesize_override;
151 return; /* Again, no L2 cache is possible */
153 c->x86_cache_size = l2size;
155 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
160 * Naming convention should be: <Name> [(<Codename>)]
161 * This table only is used unless init_<vendor>() below doesn't set it;
162 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
166 /* Look up CPU names by table lookup. */
167 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
169 struct cpu_model_info *info;
171 if (c->x86_model >= 16)
172 return NULL; /* Range check */
177 info = this_cpu->c_models;
179 while (info && info->family) {
180 if (info->family == c->x86)
181 return info->model_names[c->x86_model];
184 return NULL; /* Not found */
188 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
190 char *v = c->x86_vendor_id;
194 for (i = 0; i < X86_VENDOR_NUM; i++) {
196 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
197 (cpu_devs[i]->c_ident[1] &&
198 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
201 this_cpu = cpu_devs[i];
208 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
209 printk(KERN_ERR "CPU: Your system may be unstable.\n");
211 c->x86_vendor = X86_VENDOR_UNKNOWN;
212 this_cpu = &default_cpu;
216 static int __init x86_fxsr_setup(char *s)
218 setup_clear_cpu_cap(X86_FEATURE_FXSR);
219 setup_clear_cpu_cap(X86_FEATURE_XMM);
222 __setup("nofxsr", x86_fxsr_setup);
225 static int __init x86_sep_setup(char *s)
227 setup_clear_cpu_cap(X86_FEATURE_SEP);
230 __setup("nosep", x86_sep_setup);
233 /* Standard macro to see if a specific flag is changeable */
234 static inline int flag_is_changeable_p(u32 flag)
248 : "=&r" (f1), "=&r" (f2)
251 return ((f1^f2) & flag) != 0;
255 /* Probe for the CPUID instruction */
256 static int __cpuinit have_cpuid_p(void)
258 return flag_is_changeable_p(X86_EFLAGS_ID);
261 void __init cpu_detect(struct cpuinfo_x86 *c)
263 /* Get vendor name */
264 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
265 (unsigned int *)&c->x86_vendor_id[0],
266 (unsigned int *)&c->x86_vendor_id[8],
267 (unsigned int *)&c->x86_vendor_id[4]);
270 if (c->cpuid_level >= 0x00000001) {
271 u32 junk, tfms, cap0, misc;
272 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
273 c->x86 = (tfms >> 8) & 15;
274 c->x86_model = (tfms >> 4) & 15;
276 c->x86 += (tfms >> 20) & 0xff;
278 c->x86_model += ((tfms >> 16) & 0xF) << 4;
279 c->x86_mask = tfms & 15;
280 if (cap0 & (1<<19)) {
281 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
282 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
286 static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
291 memset(&c->x86_capability, 0, sizeof c->x86_capability);
292 if (have_cpuid_p()) {
293 /* Intel-defined flags: level 0x00000001 */
294 if (c->cpuid_level >= 0x00000001) {
295 u32 capability, excap;
296 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
297 c->x86_capability[0] = capability;
298 c->x86_capability[4] = excap;
301 /* AMD-defined flags: level 0x80000001 */
302 xlvl = cpuid_eax(0x80000000);
303 if ((xlvl & 0xffff0000) == 0x80000000) {
304 if (xlvl >= 0x80000001) {
305 c->x86_capability[1] = cpuid_edx(0x80000001);
306 c->x86_capability[6] = cpuid_ecx(0x80000001);
312 clear_cpu_cap(c, X86_FEATURE_PAT);
314 switch (c->x86_vendor) {
316 if (c->x86 >= 0xf && c->x86 <= 0x11)
317 set_cpu_cap(c, X86_FEATURE_PAT);
319 case X86_VENDOR_INTEL:
320 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
321 set_cpu_cap(c, X86_FEATURE_PAT);
328 * Do minimum CPU detection early.
329 * Fields really needed: vendor, cpuid_level, family, model, mask,
331 * The others are not touched to avoid unwanted side effects.
333 * WARNING: this function is only called on the BP. Don't add code here
334 * that is supposed to run on all CPUs.
336 static void __init early_cpu_detect(void)
338 struct cpuinfo_x86 *c = &boot_cpu_data;
340 c->x86_cache_alignment = 32;
341 c->x86_clflush_size = 32;
348 get_cpu_vendor(c, 1);
350 if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
351 cpu_devs[c->x86_vendor]->c_early_init)
352 cpu_devs[c->x86_vendor]->c_early_init(c);
357 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
362 if (have_cpuid_p()) {
363 /* Get vendor name */
364 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
365 (unsigned int *)&c->x86_vendor_id[0],
366 (unsigned int *)&c->x86_vendor_id[8],
367 (unsigned int *)&c->x86_vendor_id[4]);
369 get_cpu_vendor(c, 0);
370 /* Initialize the standard set of capabilities */
371 /* Note that the vendor-specific code below might override */
372 /* Intel-defined flags: level 0x00000001 */
373 if (c->cpuid_level >= 0x00000001) {
374 u32 capability, excap;
375 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
376 c->x86_capability[0] = capability;
377 c->x86_capability[4] = excap;
378 c->x86 = (tfms >> 8) & 15;
379 c->x86_model = (tfms >> 4) & 15;
381 c->x86 += (tfms >> 20) & 0xff;
383 c->x86_model += ((tfms >> 16) & 0xF) << 4;
384 c->x86_mask = tfms & 15;
385 c->initial_apicid = (ebx >> 24) & 0xFF;
387 c->apicid = phys_pkg_id(c->initial_apicid, 0);
388 c->phys_proc_id = c->initial_apicid;
390 c->apicid = c->initial_apicid;
392 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
393 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
395 /* Have CPUID level 0 only - unheard of */
399 /* AMD-defined flags: level 0x80000001 */
400 xlvl = cpuid_eax(0x80000000);
401 if ((xlvl & 0xffff0000) == 0x80000000) {
402 if (xlvl >= 0x80000001) {
403 c->x86_capability[1] = cpuid_edx(0x80000001);
404 c->x86_capability[6] = cpuid_ecx(0x80000001);
406 if (xlvl >= 0x80000004)
407 get_model_name(c); /* Default name */
410 init_scattered_cpuid_features(c);
413 clear_cpu_cap(c, X86_FEATURE_PAT);
415 switch (c->x86_vendor) {
417 if (c->x86 >= 0xf && c->x86 <= 0x11)
418 set_cpu_cap(c, X86_FEATURE_PAT);
420 case X86_VENDOR_INTEL:
421 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
422 set_cpu_cap(c, X86_FEATURE_PAT);
427 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
429 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
430 /* Disable processor serial number */
431 unsigned long lo, hi;
432 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
434 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
435 printk(KERN_NOTICE "CPU serial number disabled.\n");
436 clear_cpu_cap(c, X86_FEATURE_PN);
438 /* Disabling the serial number may affect the cpuid level */
439 c->cpuid_level = cpuid_eax(0);
443 static int __init x86_serial_nr_setup(char *s)
445 disable_x86_serial_nr = 0;
448 __setup("serialnumber", x86_serial_nr_setup);
453 * This does the hard work of actually picking apart the CPU stuff...
455 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
459 c->loops_per_jiffy = loops_per_jiffy;
460 c->x86_cache_size = -1;
461 c->x86_vendor = X86_VENDOR_UNKNOWN;
462 c->cpuid_level = -1; /* CPUID not detected */
463 c->x86_model = c->x86_mask = 0; /* So far unknown... */
464 c->x86_vendor_id[0] = '\0'; /* Unset */
465 c->x86_model_id[0] = '\0'; /* Unset */
466 c->x86_max_cores = 1;
467 c->x86_clflush_size = 32;
468 memset(&c->x86_capability, 0, sizeof c->x86_capability);
470 if (!have_cpuid_p()) {
472 * First of all, decide if this is a 486 or higher
473 * It's a 486 if we can modify the AC flag
475 if (flag_is_changeable_p(X86_EFLAGS_AC))
483 if (this_cpu->c_identify)
484 this_cpu->c_identify(c);
487 * Vendor-specific initialization. In this section we
488 * canonicalize the feature flags, meaning if there are
489 * features a certain CPU supports which CPUID doesn't
490 * tell us, CPUID claiming incorrect flags, or other bugs,
491 * we handle them here.
493 * At the end of this section, c->x86_capability better
494 * indicate the features this CPU genuinely supports!
496 if (this_cpu->c_init)
499 /* Disable the PN if appropriate */
500 squash_the_stupid_serial_number(c);
503 * The vendor-specific functions might have changed features. Now
504 * we do "generic changes."
507 /* If the model name is still unset, do table lookup. */
508 if (!c->x86_model_id[0]) {
510 p = table_lookup_model(c);
512 strcpy(c->x86_model_id, p);
515 sprintf(c->x86_model_id, "%02x/%02x",
516 c->x86, c->x86_model);
520 * On SMP, boot_cpu_data holds the common feature set between
521 * all CPUs; so make sure that we indicate which features are
522 * common between the CPUs. The first time this routine gets
523 * executed, c == &boot_cpu_data.
525 if (c != &boot_cpu_data) {
526 /* AND the already accumulated flags with these */
527 for (i = 0 ; i < NCAPINTS ; i++)
528 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
531 /* Clear all flags overriden by options */
532 for (i = 0; i < NCAPINTS; i++)
533 c->x86_capability[i] &= ~cleared_cpu_caps[i];
535 /* Init Machine Check Exception if available. */
538 select_idle_routine(c);
541 void __init identify_boot_cpu(void)
543 identify_cpu(&boot_cpu_data);
548 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
550 BUG_ON(c == &boot_cpu_data);
557 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
559 u32 eax, ebx, ecx, edx;
560 int index_msb, core_bits;
562 cpuid(1, &eax, &ebx, &ecx, &edx);
564 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
567 smp_num_siblings = (ebx & 0xff0000) >> 16;
569 if (smp_num_siblings == 1) {
570 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
571 } else if (smp_num_siblings > 1) {
573 if (smp_num_siblings > NR_CPUS) {
574 printk(KERN_WARNING "CPU: Unsupported number of the "
575 "siblings %d", smp_num_siblings);
576 smp_num_siblings = 1;
580 index_msb = get_count_order(smp_num_siblings);
581 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
583 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
586 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
588 index_msb = get_count_order(smp_num_siblings) ;
590 core_bits = get_count_order(c->x86_max_cores);
592 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
593 ((1 << core_bits) - 1);
595 if (c->x86_max_cores > 1)
596 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
602 static __init int setup_noclflush(char *arg)
604 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
607 __setup("noclflush", setup_noclflush);
609 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
613 if (c->x86_vendor < X86_VENDOR_NUM)
614 vendor = this_cpu->c_vendor;
615 else if (c->cpuid_level >= 0)
616 vendor = c->x86_vendor_id;
618 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
619 printk("%s ", vendor);
621 if (!c->x86_model_id[0])
622 printk("%d86", c->x86);
624 printk("%s", c->x86_model_id);
626 if (c->x86_mask || c->cpuid_level >= 0)
627 printk(" stepping %02x\n", c->x86_mask);
632 static __init int setup_disablecpuid(char *arg)
635 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
636 setup_clear_cpu_cap(bit);
641 __setup("clearcpuid=", setup_disablecpuid);
643 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
645 void __init early_cpu_init(void)
647 struct cpu_vendor_dev *cvdev;
649 for (cvdev = __x86cpuvendor_start ;
650 cvdev < __x86cpuvendor_end ;
652 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
657 /* Make sure %fs is initialized properly in idle threads */
658 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
660 memset(regs, 0, sizeof(struct pt_regs));
661 regs->fs = __KERNEL_PERCPU;
665 /* Current gdt points %fs at the "master" per-cpu area: after this,
666 * it's on the real one. */
667 void switch_to_new_gdt(void)
669 struct desc_ptr gdt_descr;
671 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
672 gdt_descr.size = GDT_SIZE - 1;
673 load_gdt(&gdt_descr);
674 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
678 * cpu_init() initializes state that is per-CPU. Some data is already
679 * initialized (naturally) in the bootstrap process, such as the GDT
680 * and IDT. We reload them nevertheless, this function acts as a
681 * 'CPU state barrier', nothing should get across.
683 void __cpuinit cpu_init(void)
685 int cpu = smp_processor_id();
686 struct task_struct *curr = current;
687 struct tss_struct *t = &per_cpu(init_tss, cpu);
688 struct thread_struct *thread = &curr->thread;
690 if (cpu_test_and_set(cpu, cpu_initialized)) {
691 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
692 for (;;) local_irq_enable();
695 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
697 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
698 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
700 load_idt(&idt_descr);
704 * Set up and load the per-CPU TSS and LDT
706 atomic_inc(&init_mm.mm_count);
707 curr->active_mm = &init_mm;
710 enter_lazy_tlb(&init_mm, curr);
713 set_tss_desc(cpu, t);
715 load_LDT(&init_mm.context);
717 #ifdef CONFIG_DOUBLEFAULT
718 /* Set up doublefault TSS pointer in the GDT */
719 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
723 asm volatile ("mov %0, %%gs" : : "r" (0));
725 /* Clear all 6 debug registers: */
734 * Force FPU initialization:
736 current_thread_info()->status = 0;
738 mxcsr_feature_mask_init();
741 #ifdef CONFIG_HOTPLUG_CPU
742 void __cpuinit cpu_uninit(void)
744 int cpu = raw_smp_processor_id();
745 cpu_clear(cpu, cpu_initialized);
748 per_cpu(cpu_tlbstate, cpu).state = 0;
749 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;