2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
37 #include <asm/mach_apic.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
44 int disable_apic_timer __cpuinitdata;
45 static int apic_calibrate_pmtmr __initdata;
48 /* Local APIC timer works in C2 */
49 int local_apic_timer_c2_ok;
50 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
53 * Debug level, exported for io_apic.c
57 static struct resource lapic_resource = {
59 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
62 static unsigned int calibration_result;
64 static int lapic_next_event(unsigned long delta,
65 struct clock_event_device *evt);
66 static void lapic_timer_setup(enum clock_event_mode mode,
67 struct clock_event_device *evt);
68 static void lapic_timer_broadcast(cpumask_t mask);
69 static void apic_pm_activate(void);
71 static struct clock_event_device lapic_clockevent = {
73 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
74 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
76 .set_mode = lapic_timer_setup,
77 .set_next_event = lapic_next_event,
78 .broadcast = lapic_timer_broadcast,
82 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
85 * Get the LAPIC version
87 static inline int lapic_get_version(void)
89 return GET_APIC_VERSION(apic_read(APIC_LVR));
93 * Check, if the APIC is integrated or a seperate chip
95 static inline int lapic_is_integrated(void)
101 * Check, whether this is a modern or a first generation APIC
103 static int modern_apic(void)
105 /* AMD systems use old APIC versions, so check the CPU */
106 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
107 boot_cpu_data.x86 >= 0xf)
109 return lapic_get_version() >= 0x14;
112 void apic_wait_icr_idle(void)
114 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
118 u32 safe_apic_wait_icr_idle(void)
125 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
129 } while (timeout++ < 1000);
135 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
137 void __cpuinit enable_NMI_through_LVT0(void)
141 /* unmask and set to NMI */
143 apic_write(APIC_LVT0, v);
147 * lapic_get_maxlvt - get the maximum number of local vector table entries
149 int lapic_get_maxlvt(void)
151 unsigned int v, maxlvt;
153 v = apic_read(APIC_LVR);
154 maxlvt = GET_APIC_MAXLVT(v);
159 * This function sets up the local APIC timer, with a timeout of
160 * 'clocks' APIC bus clock. During calibration we actually call
161 * this function twice on the boot CPU, once with a bogus timeout
162 * value, second time for real. The other (noncalibrating) CPUs
163 * call this function only once, with the real, calibrated value.
165 * We do reads before writes even if unnecessary, to get around the
166 * P5 APIC double write bug.
169 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
171 unsigned int lvtt_value, tmp_value;
173 lvtt_value = LOCAL_TIMER_VECTOR;
175 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
177 lvtt_value |= APIC_LVT_MASKED;
179 apic_write(APIC_LVTT, lvtt_value);
184 tmp_value = apic_read(APIC_TDCR);
185 apic_write(APIC_TDCR, (tmp_value
186 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
190 apic_write(APIC_TMICT, clocks);
194 * Setup extended LVT, AMD specific (K8, family 10h)
196 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
197 * MCE interrupts are supported. Thus MCE offset must be set to 0.
200 #define APIC_EILVT_LVTOFF_MCE 0
201 #define APIC_EILVT_LVTOFF_IBS 1
203 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
205 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
206 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
211 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
213 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
214 return APIC_EILVT_LVTOFF_MCE;
217 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
219 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
220 return APIC_EILVT_LVTOFF_IBS;
224 * Program the next event, relative to now
226 static int lapic_next_event(unsigned long delta,
227 struct clock_event_device *evt)
229 apic_write(APIC_TMICT, delta);
234 * Setup the lapic timer in periodic or oneshot mode
236 static void lapic_timer_setup(enum clock_event_mode mode,
237 struct clock_event_device *evt)
242 /* Lapic used as dummy for broadcast ? */
243 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
246 local_irq_save(flags);
249 case CLOCK_EVT_MODE_PERIODIC:
250 case CLOCK_EVT_MODE_ONESHOT:
251 __setup_APIC_LVTT(calibration_result,
252 mode != CLOCK_EVT_MODE_PERIODIC, 1);
254 case CLOCK_EVT_MODE_UNUSED:
255 case CLOCK_EVT_MODE_SHUTDOWN:
256 v = apic_read(APIC_LVTT);
257 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
258 apic_write(APIC_LVTT, v);
260 case CLOCK_EVT_MODE_RESUME:
261 /* Nothing to do here */
265 local_irq_restore(flags);
269 * Local APIC timer broadcast function
271 static void lapic_timer_broadcast(cpumask_t mask)
274 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
279 * Setup the local APIC timer for this CPU. Copy the initilized values
280 * of the boot CPU and register the clock event in the framework.
282 static void setup_APIC_timer(void)
284 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
286 memcpy(levt, &lapic_clockevent, sizeof(*levt));
287 levt->cpumask = cpumask_of_cpu(smp_processor_id());
289 clockevents_register_device(levt);
293 * In this function we calibrate APIC bus clocks to the external
294 * timer. Unfortunately we cannot use jiffies and the timer irq
295 * to calibrate, since some later bootup code depends on getting
296 * the first irq? Ugh.
298 * We want to do the calibration only once since we
299 * want to have local timer irqs syncron. CPUs connected
300 * by the same APIC bus have the very same bus frequency.
301 * And we want to have irqs off anyways, no accidental
305 #define TICK_COUNT 100000000
307 static void __init calibrate_APIC_clock(void)
309 unsigned apic, apic_start;
310 unsigned long tsc, tsc_start;
316 * Put whatever arbitrary (but long enough) timeout
317 * value into the APIC clock, we just want to get the
318 * counter running for calibration.
320 * No interrupt enable !
322 __setup_APIC_LVTT(250000000, 0, 0);
324 apic_start = apic_read(APIC_TMCCT);
325 #ifdef CONFIG_X86_PM_TIMER
326 if (apic_calibrate_pmtmr && pmtmr_ioport) {
327 pmtimer_wait(5000); /* 5ms wait */
328 apic = apic_read(APIC_TMCCT);
329 result = (apic_start - apic) * 1000L / 5;
336 apic = apic_read(APIC_TMCCT);
338 } while ((tsc - tsc_start) < TICK_COUNT &&
339 (apic_start - apic) < TICK_COUNT);
341 result = (apic_start - apic) * 1000L * tsc_khz /
347 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
349 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
350 result / 1000 / 1000, result / 1000 % 1000);
352 /* Calculate the scaled math multiplication factor */
353 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
354 lapic_clockevent.max_delta_ns =
355 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
356 lapic_clockevent.min_delta_ns =
357 clockevent_delta2ns(0xF, &lapic_clockevent);
359 calibration_result = result / HZ;
363 * Setup the boot APIC
365 * Calibrate and verify the result.
367 void __init setup_boot_APIC_clock(void)
370 * The local apic timer can be disabled via the kernel commandline.
371 * Register the lapic timer as a dummy clock event source on SMP
372 * systems, so the broadcast mechanism is used. On UP systems simply
375 if (disable_apic_timer) {
376 printk(KERN_INFO "Disabling APIC timer\n");
377 /* No broadcast on UP ! */
378 if (num_possible_cpus() > 1)
383 printk(KERN_INFO "Using local APIC timer interrupts.\n");
384 calibrate_APIC_clock();
387 * If nmi_watchdog is set to IO_APIC, we need the
388 * PIT/HPET going. Otherwise register lapic as a dummy
391 if (nmi_watchdog != NMI_IO_APIC)
392 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
394 printk(KERN_WARNING "APIC timer registered as dummy,"
395 " due to nmi_watchdog=1!\n");
401 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
402 * C1E flag only in the secondary CPU, so when we detect the wreckage
403 * we already have enabled the boot CPU local apic timer. Check, if
404 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
405 * set the DUMMY flag again and force the broadcast mode in the
408 void __cpuinit check_boot_apic_timer_broadcast(void)
410 if (!disable_apic_timer ||
411 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
414 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
415 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
418 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id);
422 void __cpuinit setup_secondary_APIC_clock(void)
424 check_boot_apic_timer_broadcast();
429 * The guts of the apic timer interrupt
431 static void local_apic_timer_interrupt(void)
433 int cpu = smp_processor_id();
434 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
437 * Normally we should not be here till LAPIC has been initialized but
438 * in some cases like kdump, its possible that there is a pending LAPIC
439 * timer interrupt from previous kernel's context and is delivered in
440 * new kernel the moment interrupts are enabled.
442 * Interrupts are enabled early and LAPIC is setup much later, hence
443 * its possible that when we get here evt->event_handler is NULL.
444 * Check for event_handler being NULL and discard the interrupt as
447 if (!evt->event_handler) {
449 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
451 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
456 * the NMI deadlock-detector uses this.
458 add_pda(apic_timer_irqs, 1);
460 evt->event_handler(evt);
464 * Local APIC timer interrupt. This is the most natural way for doing
465 * local interrupts, but local timer interrupts can be emulated by
466 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
468 * [ if a single-CPU system runs an SMP kernel then we call the local
469 * interrupt as well. Thus we cannot inline the local irq ... ]
471 void smp_apic_timer_interrupt(struct pt_regs *regs)
473 struct pt_regs *old_regs = set_irq_regs(regs);
476 * NOTE! We'd better ACK the irq immediately,
477 * because timer handling can be slow.
481 * update_process_times() expects us to have done irq_enter().
482 * Besides, if we don't timer interrupts ignore the global
483 * interrupt lock, which is the WrongThing (tm) to do.
487 local_apic_timer_interrupt();
489 set_irq_regs(old_regs);
492 int setup_profiling_timer(unsigned int multiplier)
499 * Local APIC start and shutdown
503 * clear_local_APIC - shutdown the local APIC
505 * This is called, when a CPU is disabled and before rebooting, so the state of
506 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
507 * leftovers during boot.
509 void clear_local_APIC(void)
511 int maxlvt = lapic_get_maxlvt();
515 * Masking an LVT entry can trigger a local APIC error
516 * if the vector is zero. Mask LVTERR first to prevent this.
519 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
520 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
523 * Careful: we have to set masks only first to deassert
524 * any level-triggered sources.
526 v = apic_read(APIC_LVTT);
527 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
528 v = apic_read(APIC_LVT0);
529 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
530 v = apic_read(APIC_LVT1);
531 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
533 v = apic_read(APIC_LVTPC);
534 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
538 * Clean APIC state for other OSs:
540 apic_write(APIC_LVTT, APIC_LVT_MASKED);
541 apic_write(APIC_LVT0, APIC_LVT_MASKED);
542 apic_write(APIC_LVT1, APIC_LVT_MASKED);
544 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
546 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
547 apic_write(APIC_ESR, 0);
552 * disable_local_APIC - clear and disable the local APIC
554 void disable_local_APIC(void)
561 * Disable APIC (implies clearing of registers
564 value = apic_read(APIC_SPIV);
565 value &= ~APIC_SPIV_APIC_ENABLED;
566 apic_write(APIC_SPIV, value);
569 void lapic_shutdown(void)
576 local_irq_save(flags);
578 disable_local_APIC();
580 local_irq_restore(flags);
584 * This is to verify that we're looking at a real local APIC.
585 * Check these against your board if the CPUs aren't getting
586 * started for no apparent reason.
588 int __init verify_local_APIC(void)
590 unsigned int reg0, reg1;
593 * The version register is read-only in a real APIC.
595 reg0 = apic_read(APIC_LVR);
596 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
597 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
598 reg1 = apic_read(APIC_LVR);
599 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
602 * The two version reads above should print the same
603 * numbers. If the second one is different, then we
604 * poke at a non-APIC.
610 * Check if the version looks reasonably.
612 reg1 = GET_APIC_VERSION(reg0);
613 if (reg1 == 0x00 || reg1 == 0xff)
615 reg1 = lapic_get_maxlvt();
616 if (reg1 < 0x02 || reg1 == 0xff)
620 * The ID register is read/write in a real APIC.
622 reg0 = apic_read(APIC_ID);
623 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
624 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
625 reg1 = apic_read(APIC_ID);
626 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
627 apic_write(APIC_ID, reg0);
628 if (reg1 != (reg0 ^ APIC_ID_MASK))
632 * The next two are just to see if we have sane values.
633 * They're only really relevant if we're in Virtual Wire
634 * compatibility mode, but most boxes are anymore.
636 reg0 = apic_read(APIC_LVT0);
637 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
638 reg1 = apic_read(APIC_LVT1);
639 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
645 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
647 void __init sync_Arb_IDs(void)
649 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
656 apic_wait_icr_idle();
658 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
659 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
664 * An initial setup of the virtual wire mode.
666 void __init init_bsp_APIC(void)
671 * Don't do the setup now if we have a SMP BIOS as the
672 * through-I/O-APIC virtual wire mode might be active.
674 if (smp_found_config || !cpu_has_apic)
677 value = apic_read(APIC_LVR);
680 * Do not trust the local APIC being empty at bootup.
687 value = apic_read(APIC_SPIV);
688 value &= ~APIC_VECTOR_MASK;
689 value |= APIC_SPIV_APIC_ENABLED;
690 value |= APIC_SPIV_FOCUS_DISABLED;
691 value |= SPURIOUS_APIC_VECTOR;
692 apic_write(APIC_SPIV, value);
695 * Set up the virtual wire mode.
697 apic_write(APIC_LVT0, APIC_DM_EXTINT);
699 apic_write(APIC_LVT1, value);
703 * setup_local_APIC - setup the local APIC
705 void __cpuinit setup_local_APIC(void)
710 value = apic_read(APIC_LVR);
712 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
715 * Double-check whether this APIC is really registered.
716 * This is meaningless in clustered apic mode, so we skip it.
718 if (!apic_id_registered())
722 * Intel recommends to set DFR, LDR and TPR before enabling
723 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
724 * document number 292116). So here it goes...
729 * Set Task Priority to 'accept all'. We never change this
732 value = apic_read(APIC_TASKPRI);
733 value &= ~APIC_TPRI_MASK;
734 apic_write(APIC_TASKPRI, value);
737 * After a crash, we no longer service the interrupts and a pending
738 * interrupt from previous kernel might still have ISR bit set.
740 * Most probably by now CPU has serviced that pending interrupt and
741 * it might not have done the ack_APIC_irq() because it thought,
742 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
743 * does not clear the ISR bit and cpu thinks it has already serivced
744 * the interrupt. Hence a vector might get locked. It was noticed
745 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
747 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
748 value = apic_read(APIC_ISR + i*0x10);
749 for (j = 31; j >= 0; j--) {
756 * Now that we are all set up, enable the APIC
758 value = apic_read(APIC_SPIV);
759 value &= ~APIC_VECTOR_MASK;
763 value |= APIC_SPIV_APIC_ENABLED;
765 /* We always use processor focus */
768 * Set spurious IRQ vector
770 value |= SPURIOUS_APIC_VECTOR;
771 apic_write(APIC_SPIV, value);
776 * set up through-local-APIC on the BP's LINT0. This is not
777 * strictly necessary in pure symmetric-IO mode, but sometimes
778 * we delegate interrupts to the 8259A.
781 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
783 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
784 if (!smp_processor_id() && !value) {
785 value = APIC_DM_EXTINT;
786 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
789 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
790 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
793 apic_write(APIC_LVT0, value);
796 * only the BP should see the LINT1 NMI signal, obviously.
798 if (!smp_processor_id())
801 value = APIC_DM_NMI | APIC_LVT_MASKED;
802 apic_write(APIC_LVT1, value);
805 void __cpuinit lapic_setup_esr(void)
807 unsigned maxlvt = lapic_get_maxlvt();
809 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
811 * spec says clear errors after enabling vector.
814 apic_write(APIC_ESR, 0);
817 void __cpuinit end_local_APIC_setup(void)
820 nmi_watchdog_default();
821 setup_apic_nmi_watchdog(NULL);
826 * Detect and enable local APICs on non-SMP boards.
827 * Original code written by Keir Fraser.
828 * On AMD64 we trust the BIOS - if it says no APIC it is likely
829 * not correctly set up (usually the APIC timer won't work etc.)
831 static int __init detect_init_APIC(void)
834 printk(KERN_INFO "No local APIC present\n");
838 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
844 * init_apic_mappings - initialize APIC mappings
846 void __init init_apic_mappings(void)
848 unsigned long apic_phys;
851 * If no local APIC can be found then set up a fake all
852 * zeroes page to simulate the local APIC and another
853 * one for the IO-APIC.
855 if (!smp_found_config && detect_init_APIC()) {
856 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
857 apic_phys = __pa(apic_phys);
859 apic_phys = mp_lapic_addr;
861 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
862 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
863 APIC_BASE, apic_phys);
865 /* Put local APIC into the resource map. */
866 lapic_resource.start = apic_phys;
867 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
868 insert_resource(&iomem_resource, &lapic_resource);
871 * Fetch the APIC ID of the BSP in case we have a
872 * default configuration (or the MP table is broken).
874 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
878 * This initializes the IO-APIC and APIC hardware if this is
881 int __init APIC_init_uniprocessor(void)
884 printk(KERN_INFO "Apic disabled\n");
889 printk(KERN_INFO "Apic disabled by BIOS\n");
895 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
896 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
901 * Now enable IO-APICs, actually call clear_IO_APIC
902 * We need clear_IO_APIC before enabling vector on BP
904 if (!skip_ioapic_setup && nr_ioapics)
907 end_local_APIC_setup();
909 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
913 setup_boot_APIC_clock();
914 check_nmi_watchdog();
919 * Local APIC interrupts
923 * This interrupt should _never_ happen with our APIC/SMP architecture
925 asmlinkage void smp_spurious_interrupt(void)
931 * Check if this really is a spurious interrupt and ACK it
932 * if it is a vectored one. Just in case...
933 * Spurious interrupts should not be ACKed.
935 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
936 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
939 add_pda(irq_spurious_count, 1);
944 * This interrupt should never happen with our APIC/SMP architecture
946 asmlinkage void smp_error_interrupt(void)
952 /* First tickle the hardware, only then report what went on. -- REW */
953 v = apic_read(APIC_ESR);
954 apic_write(APIC_ESR, 0);
955 v1 = apic_read(APIC_ESR);
957 atomic_inc(&irq_err_count);
959 /* Here is what the APIC error bits mean:
963 3: Receive accept error
965 5: Send illegal vector
966 6: Received illegal vector
967 7: Illegal register address
969 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
970 smp_processor_id(), v , v1);
974 void disconnect_bsp_APIC(int virt_wire_setup)
976 /* Go back to Virtual Wire compatibility mode */
979 /* For the spurious interrupt use vector F, and enable it */
980 value = apic_read(APIC_SPIV);
981 value &= ~APIC_VECTOR_MASK;
982 value |= APIC_SPIV_APIC_ENABLED;
984 apic_write(APIC_SPIV, value);
986 if (!virt_wire_setup) {
988 * For LVT0 make it edge triggered, active high,
989 * external and enabled
991 value = apic_read(APIC_LVT0);
992 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
993 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
994 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
995 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
996 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
997 apic_write(APIC_LVT0, value);
1000 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1003 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1004 value = apic_read(APIC_LVT1);
1005 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1006 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1007 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1008 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1009 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1010 apic_write(APIC_LVT1, value);
1019 /* 'active' is true if the local APIC was enabled by us and
1020 not the BIOS; this signifies that we are also responsible
1021 for disabling it before entering apm/acpi suspend */
1023 /* r/w apic fields */
1024 unsigned int apic_id;
1025 unsigned int apic_taskpri;
1026 unsigned int apic_ldr;
1027 unsigned int apic_dfr;
1028 unsigned int apic_spiv;
1029 unsigned int apic_lvtt;
1030 unsigned int apic_lvtpc;
1031 unsigned int apic_lvt0;
1032 unsigned int apic_lvt1;
1033 unsigned int apic_lvterr;
1034 unsigned int apic_tmict;
1035 unsigned int apic_tdcr;
1036 unsigned int apic_thmr;
1039 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1041 unsigned long flags;
1044 if (!apic_pm_state.active)
1047 maxlvt = lapic_get_maxlvt();
1049 apic_pm_state.apic_id = apic_read(APIC_ID);
1050 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1051 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1052 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1053 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1054 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1056 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1057 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1058 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1059 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1060 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1061 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1062 #ifdef CONFIG_X86_MCE_INTEL
1064 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1066 local_irq_save(flags);
1067 disable_local_APIC();
1068 local_irq_restore(flags);
1072 static int lapic_resume(struct sys_device *dev)
1075 unsigned long flags;
1078 if (!apic_pm_state.active)
1081 maxlvt = lapic_get_maxlvt();
1083 local_irq_save(flags);
1084 rdmsr(MSR_IA32_APICBASE, l, h);
1085 l &= ~MSR_IA32_APICBASE_BASE;
1086 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1087 wrmsr(MSR_IA32_APICBASE, l, h);
1088 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1089 apic_write(APIC_ID, apic_pm_state.apic_id);
1090 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1091 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1092 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1093 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1094 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1095 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1096 #ifdef CONFIG_X86_MCE_INTEL
1098 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1101 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1102 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1103 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1104 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1105 apic_write(APIC_ESR, 0);
1106 apic_read(APIC_ESR);
1107 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1108 apic_write(APIC_ESR, 0);
1109 apic_read(APIC_ESR);
1110 local_irq_restore(flags);
1114 static struct sysdev_class lapic_sysclass = {
1116 .resume = lapic_resume,
1117 .suspend = lapic_suspend,
1120 static struct sys_device device_lapic = {
1122 .cls = &lapic_sysclass,
1125 static void __cpuinit apic_pm_activate(void)
1127 apic_pm_state.active = 1;
1130 static int __init init_lapic_sysfs(void)
1136 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1138 error = sysdev_class_register(&lapic_sysclass);
1140 error = sysdev_register(&device_lapic);
1143 device_initcall(init_lapic_sysfs);
1145 #else /* CONFIG_PM */
1147 static void apic_pm_activate(void) { }
1149 #endif /* CONFIG_PM */
1152 * apic_is_clustered_box() -- Check if we can expect good TSC
1154 * Thus far, the major user of this is IBM's Summit2 series:
1156 * Clustered boxes may have unsynced TSC problems if they are
1157 * multi-chassis. Use available data to take a good guess.
1158 * If in doubt, go HPET.
1160 __cpuinit int apic_is_clustered_box(void)
1162 int i, clusters, zeros;
1164 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1166 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1168 for (i = 0; i < NR_CPUS; i++) {
1169 id = bios_cpu_apicid[i];
1170 if (id != BAD_APICID)
1171 __set_bit(APIC_CLUSTERID(id), clustermap);
1174 /* Problem: Partially populated chassis may not have CPUs in some of
1175 * the APIC clusters they have been allocated. Only present CPUs have
1176 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1177 * clusters are allocated sequentially, count zeros only if they are
1182 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1183 if (test_bit(i, clustermap)) {
1184 clusters += 1 + zeros;
1191 * If clusters > 2, then should be multi-chassis.
1192 * May have to revisit this when multi-core + hyperthreaded CPUs come
1193 * out, but AFAIK this will work even for them.
1195 return (clusters > 2);
1199 * APIC command line parameters
1201 static int __init apic_set_verbosity(char *str)
1204 skip_ioapic_setup = 0;
1208 if (strcmp("debug", str) == 0)
1209 apic_verbosity = APIC_DEBUG;
1210 else if (strcmp("verbose", str) == 0)
1211 apic_verbosity = APIC_VERBOSE;
1213 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1214 " use apic=verbose or apic=debug\n", str);
1220 early_param("apic", apic_set_verbosity);
1222 static __init int setup_disableapic(char *str)
1225 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1228 early_param("disableapic", setup_disableapic);
1230 /* same as disableapic, for compatibility */
1231 static __init int setup_nolapic(char *str)
1233 return setup_disableapic(str);
1235 early_param("nolapic", setup_nolapic);
1237 static int __init parse_lapic_timer_c2_ok(char *arg)
1239 local_apic_timer_c2_ok = 1;
1242 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1244 static __init int setup_noapictimer(char *str)
1246 if (str[0] != ' ' && str[0] != 0)
1248 disable_apic_timer = 1;
1251 __setup("noapictimer", setup_noapictimer);
1253 static __init int setup_apicpmtimer(char *s)
1255 apic_calibrate_pmtmr = 1;
1259 __setup("apicpmtimer", setup_apicpmtimer);