2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
37 #include <asm/mach_apic.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
44 int disable_apic_timer __cpuinitdata;
45 static int apic_calibrate_pmtmr __initdata;
48 /* Local APIC timer works in C2 */
49 int local_apic_timer_c2_ok;
50 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
53 * Debug level, exported for io_apic.c
57 static struct resource lapic_resource = {
59 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
62 static unsigned int calibration_result;
64 static int lapic_next_event(unsigned long delta,
65 struct clock_event_device *evt);
66 static void lapic_timer_setup(enum clock_event_mode mode,
67 struct clock_event_device *evt);
68 static void lapic_timer_broadcast(cpumask_t mask);
69 static void apic_pm_activate(void);
71 static struct clock_event_device lapic_clockevent = {
73 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
74 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
76 .set_mode = lapic_timer_setup,
77 .set_next_event = lapic_next_event,
78 .broadcast = lapic_timer_broadcast,
82 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
85 * Get the LAPIC version
87 static inline int lapic_get_version(void)
89 return GET_APIC_VERSION(apic_read(APIC_LVR));
93 * Check, if the APIC is integrated or a seperate chip
95 static inline int lapic_is_integrated(void)
101 * Check, whether this is a modern or a first generation APIC
103 static int modern_apic(void)
105 /* AMD systems use old APIC versions, so check the CPU */
106 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
107 boot_cpu_data.x86 >= 0xf)
109 return lapic_get_version() >= 0x14;
112 void apic_wait_icr_idle(void)
114 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
118 u32 safe_apic_wait_icr_idle(void)
125 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
129 } while (timeout++ < 1000);
135 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
137 void __cpuinit enable_NMI_through_LVT0(void)
141 /* unmask and set to NMI */
143 apic_write(APIC_LVT0, v);
147 * lapic_get_maxlvt - get the maximum number of local vector table entries
149 int lapic_get_maxlvt(void)
151 unsigned int v, maxlvt;
153 v = apic_read(APIC_LVR);
154 maxlvt = GET_APIC_MAXLVT(v);
159 * This function sets up the local APIC timer, with a timeout of
160 * 'clocks' APIC bus clock. During calibration we actually call
161 * this function twice on the boot CPU, once with a bogus timeout
162 * value, second time for real. The other (noncalibrating) CPUs
163 * call this function only once, with the real, calibrated value.
165 * We do reads before writes even if unnecessary, to get around the
166 * P5 APIC double write bug.
169 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
171 unsigned int lvtt_value, tmp_value;
173 lvtt_value = LOCAL_TIMER_VECTOR;
175 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
177 lvtt_value |= APIC_LVT_MASKED;
179 apic_write(APIC_LVTT, lvtt_value);
184 tmp_value = apic_read(APIC_TDCR);
185 apic_write(APIC_TDCR, (tmp_value
186 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
190 apic_write(APIC_TMICT, clocks);
194 * Setup extended LVT, AMD specific (K8, family 10h)
196 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
197 * MCE interrupts are supported. Thus MCE offset must be set to 0.
200 #define APIC_EILVT_LVTOFF_MCE 0
201 #define APIC_EILVT_LVTOFF_IBS 1
203 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
205 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
206 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
211 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
213 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
214 return APIC_EILVT_LVTOFF_MCE;
217 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
219 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
220 return APIC_EILVT_LVTOFF_IBS;
224 * Program the next event, relative to now
226 static int lapic_next_event(unsigned long delta,
227 struct clock_event_device *evt)
229 apic_write(APIC_TMICT, delta);
234 * Setup the lapic timer in periodic or oneshot mode
236 static void lapic_timer_setup(enum clock_event_mode mode,
237 struct clock_event_device *evt)
242 /* Lapic used as dummy for broadcast ? */
243 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
246 local_irq_save(flags);
249 case CLOCK_EVT_MODE_PERIODIC:
250 case CLOCK_EVT_MODE_ONESHOT:
251 __setup_APIC_LVTT(calibration_result,
252 mode != CLOCK_EVT_MODE_PERIODIC, 1);
254 case CLOCK_EVT_MODE_UNUSED:
255 case CLOCK_EVT_MODE_SHUTDOWN:
256 v = apic_read(APIC_LVTT);
257 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
258 apic_write(APIC_LVTT, v);
260 case CLOCK_EVT_MODE_RESUME:
261 /* Nothing to do here */
265 local_irq_restore(flags);
269 * Local APIC timer broadcast function
271 static void lapic_timer_broadcast(cpumask_t mask)
274 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
279 * Setup the local APIC timer for this CPU. Copy the initilized values
280 * of the boot CPU and register the clock event in the framework.
282 static void setup_APIC_timer(void)
284 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
286 memcpy(levt, &lapic_clockevent, sizeof(*levt));
287 levt->cpumask = cpumask_of_cpu(smp_processor_id());
289 clockevents_register_device(levt);
293 * In this function we calibrate APIC bus clocks to the external
294 * timer. Unfortunately we cannot use jiffies and the timer irq
295 * to calibrate, since some later bootup code depends on getting
296 * the first irq? Ugh.
298 * We want to do the calibration only once since we
299 * want to have local timer irqs syncron. CPUs connected
300 * by the same APIC bus have the very same bus frequency.
301 * And we want to have irqs off anyways, no accidental
305 #define TICK_COUNT 100000000
307 static void __init calibrate_APIC_clock(void)
309 unsigned apic, apic_start;
310 unsigned long tsc, tsc_start;
316 * Put whatever arbitrary (but long enough) timeout
317 * value into the APIC clock, we just want to get the
318 * counter running for calibration.
320 * No interrupt enable !
322 __setup_APIC_LVTT(250000000, 0, 0);
324 apic_start = apic_read(APIC_TMCCT);
325 #ifdef CONFIG_X86_PM_TIMER
326 if (apic_calibrate_pmtmr && pmtmr_ioport) {
327 pmtimer_wait(5000); /* 5ms wait */
328 apic = apic_read(APIC_TMCCT);
329 result = (apic_start - apic) * 1000L / 5;
336 apic = apic_read(APIC_TMCCT);
338 } while ((tsc - tsc_start) < TICK_COUNT &&
339 (apic_start - apic) < TICK_COUNT);
341 result = (apic_start - apic) * 1000L * tsc_khz /
347 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
349 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
350 result / 1000 / 1000, result / 1000 % 1000);
352 /* Calculate the scaled math multiplication factor */
353 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
354 lapic_clockevent.max_delta_ns =
355 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
356 lapic_clockevent.min_delta_ns =
357 clockevent_delta2ns(0xF, &lapic_clockevent);
359 calibration_result = result / HZ;
363 * Setup the boot APIC
365 * Calibrate and verify the result.
367 void __init setup_boot_APIC_clock(void)
370 * The local apic timer can be disabled via the kernel commandline.
371 * Register the lapic timer as a dummy clock event source on SMP
372 * systems, so the broadcast mechanism is used. On UP systems simply
375 if (disable_apic_timer) {
376 printk(KERN_INFO "Disabling APIC timer\n");
377 /* No broadcast on UP ! */
378 if (num_possible_cpus() > 1)
383 printk(KERN_INFO "Using local APIC timer interrupts.\n");
384 calibrate_APIC_clock();
387 * Do a sanity check on the APIC calibration result
389 if (calibration_result < (1000000 / HZ)) {
391 "APIC frequency too slow, disabling apic timer\n");
392 /* No broadcast on UP ! */
393 if (num_possible_cpus() > 1)
399 * If nmi_watchdog is set to IO_APIC, we need the
400 * PIT/HPET going. Otherwise register lapic as a dummy
403 if (nmi_watchdog != NMI_IO_APIC)
404 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
406 printk(KERN_WARNING "APIC timer registered as dummy,"
407 " due to nmi_watchdog=1!\n");
413 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
414 * C1E flag only in the secondary CPU, so when we detect the wreckage
415 * we already have enabled the boot CPU local apic timer. Check, if
416 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
417 * set the DUMMY flag again and force the broadcast mode in the
420 void __cpuinit check_boot_apic_timer_broadcast(void)
422 if (!disable_apic_timer ||
423 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
426 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
427 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
430 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id);
434 void __cpuinit setup_secondary_APIC_clock(void)
436 check_boot_apic_timer_broadcast();
441 * The guts of the apic timer interrupt
443 static void local_apic_timer_interrupt(void)
445 int cpu = smp_processor_id();
446 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
449 * Normally we should not be here till LAPIC has been initialized but
450 * in some cases like kdump, its possible that there is a pending LAPIC
451 * timer interrupt from previous kernel's context and is delivered in
452 * new kernel the moment interrupts are enabled.
454 * Interrupts are enabled early and LAPIC is setup much later, hence
455 * its possible that when we get here evt->event_handler is NULL.
456 * Check for event_handler being NULL and discard the interrupt as
459 if (!evt->event_handler) {
461 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
463 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
468 * the NMI deadlock-detector uses this.
470 add_pda(apic_timer_irqs, 1);
472 evt->event_handler(evt);
476 * Local APIC timer interrupt. This is the most natural way for doing
477 * local interrupts, but local timer interrupts can be emulated by
478 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
480 * [ if a single-CPU system runs an SMP kernel then we call the local
481 * interrupt as well. Thus we cannot inline the local irq ... ]
483 void smp_apic_timer_interrupt(struct pt_regs *regs)
485 struct pt_regs *old_regs = set_irq_regs(regs);
488 * NOTE! We'd better ACK the irq immediately,
489 * because timer handling can be slow.
493 * update_process_times() expects us to have done irq_enter().
494 * Besides, if we don't timer interrupts ignore the global
495 * interrupt lock, which is the WrongThing (tm) to do.
499 local_apic_timer_interrupt();
501 set_irq_regs(old_regs);
504 int setup_profiling_timer(unsigned int multiplier)
511 * Local APIC start and shutdown
515 * clear_local_APIC - shutdown the local APIC
517 * This is called, when a CPU is disabled and before rebooting, so the state of
518 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
519 * leftovers during boot.
521 void clear_local_APIC(void)
523 int maxlvt = lapic_get_maxlvt();
527 * Masking an LVT entry can trigger a local APIC error
528 * if the vector is zero. Mask LVTERR first to prevent this.
531 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
532 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
535 * Careful: we have to set masks only first to deassert
536 * any level-triggered sources.
538 v = apic_read(APIC_LVTT);
539 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
540 v = apic_read(APIC_LVT0);
541 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
542 v = apic_read(APIC_LVT1);
543 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
545 v = apic_read(APIC_LVTPC);
546 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
550 * Clean APIC state for other OSs:
552 apic_write(APIC_LVTT, APIC_LVT_MASKED);
553 apic_write(APIC_LVT0, APIC_LVT_MASKED);
554 apic_write(APIC_LVT1, APIC_LVT_MASKED);
556 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
558 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
559 apic_write(APIC_ESR, 0);
564 * disable_local_APIC - clear and disable the local APIC
566 void disable_local_APIC(void)
573 * Disable APIC (implies clearing of registers
576 value = apic_read(APIC_SPIV);
577 value &= ~APIC_SPIV_APIC_ENABLED;
578 apic_write(APIC_SPIV, value);
581 void lapic_shutdown(void)
588 local_irq_save(flags);
590 disable_local_APIC();
592 local_irq_restore(flags);
596 * This is to verify that we're looking at a real local APIC.
597 * Check these against your board if the CPUs aren't getting
598 * started for no apparent reason.
600 int __init verify_local_APIC(void)
602 unsigned int reg0, reg1;
605 * The version register is read-only in a real APIC.
607 reg0 = apic_read(APIC_LVR);
608 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
609 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
610 reg1 = apic_read(APIC_LVR);
611 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
614 * The two version reads above should print the same
615 * numbers. If the second one is different, then we
616 * poke at a non-APIC.
622 * Check if the version looks reasonably.
624 reg1 = GET_APIC_VERSION(reg0);
625 if (reg1 == 0x00 || reg1 == 0xff)
627 reg1 = lapic_get_maxlvt();
628 if (reg1 < 0x02 || reg1 == 0xff)
632 * The ID register is read/write in a real APIC.
634 reg0 = apic_read(APIC_ID);
635 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
636 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
637 reg1 = apic_read(APIC_ID);
638 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
639 apic_write(APIC_ID, reg0);
640 if (reg1 != (reg0 ^ APIC_ID_MASK))
644 * The next two are just to see if we have sane values.
645 * They're only really relevant if we're in Virtual Wire
646 * compatibility mode, but most boxes are anymore.
648 reg0 = apic_read(APIC_LVT0);
649 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
650 reg1 = apic_read(APIC_LVT1);
651 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
657 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
659 void __init sync_Arb_IDs(void)
661 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
668 apic_wait_icr_idle();
670 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
671 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
676 * An initial setup of the virtual wire mode.
678 void __init init_bsp_APIC(void)
683 * Don't do the setup now if we have a SMP BIOS as the
684 * through-I/O-APIC virtual wire mode might be active.
686 if (smp_found_config || !cpu_has_apic)
689 value = apic_read(APIC_LVR);
692 * Do not trust the local APIC being empty at bootup.
699 value = apic_read(APIC_SPIV);
700 value &= ~APIC_VECTOR_MASK;
701 value |= APIC_SPIV_APIC_ENABLED;
702 value |= APIC_SPIV_FOCUS_DISABLED;
703 value |= SPURIOUS_APIC_VECTOR;
704 apic_write(APIC_SPIV, value);
707 * Set up the virtual wire mode.
709 apic_write(APIC_LVT0, APIC_DM_EXTINT);
711 apic_write(APIC_LVT1, value);
715 * setup_local_APIC - setup the local APIC
717 void __cpuinit setup_local_APIC(void)
722 value = apic_read(APIC_LVR);
724 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
727 * Double-check whether this APIC is really registered.
728 * This is meaningless in clustered apic mode, so we skip it.
730 if (!apic_id_registered())
734 * Intel recommends to set DFR, LDR and TPR before enabling
735 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
736 * document number 292116). So here it goes...
741 * Set Task Priority to 'accept all'. We never change this
744 value = apic_read(APIC_TASKPRI);
745 value &= ~APIC_TPRI_MASK;
746 apic_write(APIC_TASKPRI, value);
749 * After a crash, we no longer service the interrupts and a pending
750 * interrupt from previous kernel might still have ISR bit set.
752 * Most probably by now CPU has serviced that pending interrupt and
753 * it might not have done the ack_APIC_irq() because it thought,
754 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
755 * does not clear the ISR bit and cpu thinks it has already serivced
756 * the interrupt. Hence a vector might get locked. It was noticed
757 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
759 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
760 value = apic_read(APIC_ISR + i*0x10);
761 for (j = 31; j >= 0; j--) {
768 * Now that we are all set up, enable the APIC
770 value = apic_read(APIC_SPIV);
771 value &= ~APIC_VECTOR_MASK;
775 value |= APIC_SPIV_APIC_ENABLED;
777 /* We always use processor focus */
780 * Set spurious IRQ vector
782 value |= SPURIOUS_APIC_VECTOR;
783 apic_write(APIC_SPIV, value);
788 * set up through-local-APIC on the BP's LINT0. This is not
789 * strictly necessary in pure symmetric-IO mode, but sometimes
790 * we delegate interrupts to the 8259A.
793 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
795 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
796 if (!smp_processor_id() && !value) {
797 value = APIC_DM_EXTINT;
798 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
801 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
802 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
805 apic_write(APIC_LVT0, value);
808 * only the BP should see the LINT1 NMI signal, obviously.
810 if (!smp_processor_id())
813 value = APIC_DM_NMI | APIC_LVT_MASKED;
814 apic_write(APIC_LVT1, value);
817 void __cpuinit lapic_setup_esr(void)
819 unsigned maxlvt = lapic_get_maxlvt();
821 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
823 * spec says clear errors after enabling vector.
826 apic_write(APIC_ESR, 0);
829 void __cpuinit end_local_APIC_setup(void)
832 nmi_watchdog_default();
833 setup_apic_nmi_watchdog(NULL);
838 * Detect and enable local APICs on non-SMP boards.
839 * Original code written by Keir Fraser.
840 * On AMD64 we trust the BIOS - if it says no APIC it is likely
841 * not correctly set up (usually the APIC timer won't work etc.)
843 static int __init detect_init_APIC(void)
846 printk(KERN_INFO "No local APIC present\n");
850 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
856 * init_apic_mappings - initialize APIC mappings
858 void __init init_apic_mappings(void)
860 unsigned long apic_phys;
863 * If no local APIC can be found then set up a fake all
864 * zeroes page to simulate the local APIC and another
865 * one for the IO-APIC.
867 if (!smp_found_config && detect_init_APIC()) {
868 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
869 apic_phys = __pa(apic_phys);
871 apic_phys = mp_lapic_addr;
873 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
874 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
875 APIC_BASE, apic_phys);
877 /* Put local APIC into the resource map. */
878 lapic_resource.start = apic_phys;
879 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
880 insert_resource(&iomem_resource, &lapic_resource);
883 * Fetch the APIC ID of the BSP in case we have a
884 * default configuration (or the MP table is broken).
886 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
890 * This initializes the IO-APIC and APIC hardware if this is
893 int __init APIC_init_uniprocessor(void)
896 printk(KERN_INFO "Apic disabled\n");
901 printk(KERN_INFO "Apic disabled by BIOS\n");
907 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
908 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
913 * Now enable IO-APICs, actually call clear_IO_APIC
914 * We need clear_IO_APIC before enabling vector on BP
916 if (!skip_ioapic_setup && nr_ioapics)
919 end_local_APIC_setup();
921 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
925 setup_boot_APIC_clock();
926 check_nmi_watchdog();
931 * Local APIC interrupts
935 * This interrupt should _never_ happen with our APIC/SMP architecture
937 asmlinkage void smp_spurious_interrupt(void)
943 * Check if this really is a spurious interrupt and ACK it
944 * if it is a vectored one. Just in case...
945 * Spurious interrupts should not be ACKed.
947 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
948 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
951 add_pda(irq_spurious_count, 1);
956 * This interrupt should never happen with our APIC/SMP architecture
958 asmlinkage void smp_error_interrupt(void)
964 /* First tickle the hardware, only then report what went on. -- REW */
965 v = apic_read(APIC_ESR);
966 apic_write(APIC_ESR, 0);
967 v1 = apic_read(APIC_ESR);
969 atomic_inc(&irq_err_count);
971 /* Here is what the APIC error bits mean:
975 3: Receive accept error
977 5: Send illegal vector
978 6: Received illegal vector
979 7: Illegal register address
981 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
982 smp_processor_id(), v , v1);
986 void disconnect_bsp_APIC(int virt_wire_setup)
988 /* Go back to Virtual Wire compatibility mode */
991 /* For the spurious interrupt use vector F, and enable it */
992 value = apic_read(APIC_SPIV);
993 value &= ~APIC_VECTOR_MASK;
994 value |= APIC_SPIV_APIC_ENABLED;
996 apic_write(APIC_SPIV, value);
998 if (!virt_wire_setup) {
1000 * For LVT0 make it edge triggered, active high,
1001 * external and enabled
1003 value = apic_read(APIC_LVT0);
1004 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1005 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1006 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1007 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1008 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1009 apic_write(APIC_LVT0, value);
1012 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1015 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1016 value = apic_read(APIC_LVT1);
1017 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1018 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1019 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1020 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1021 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1022 apic_write(APIC_LVT1, value);
1031 /* 'active' is true if the local APIC was enabled by us and
1032 not the BIOS; this signifies that we are also responsible
1033 for disabling it before entering apm/acpi suspend */
1035 /* r/w apic fields */
1036 unsigned int apic_id;
1037 unsigned int apic_taskpri;
1038 unsigned int apic_ldr;
1039 unsigned int apic_dfr;
1040 unsigned int apic_spiv;
1041 unsigned int apic_lvtt;
1042 unsigned int apic_lvtpc;
1043 unsigned int apic_lvt0;
1044 unsigned int apic_lvt1;
1045 unsigned int apic_lvterr;
1046 unsigned int apic_tmict;
1047 unsigned int apic_tdcr;
1048 unsigned int apic_thmr;
1051 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1053 unsigned long flags;
1056 if (!apic_pm_state.active)
1059 maxlvt = lapic_get_maxlvt();
1061 apic_pm_state.apic_id = apic_read(APIC_ID);
1062 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1063 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1064 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1065 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1066 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1068 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1069 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1070 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1071 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1072 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1073 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1074 #ifdef CONFIG_X86_MCE_INTEL
1076 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1078 local_irq_save(flags);
1079 disable_local_APIC();
1080 local_irq_restore(flags);
1084 static int lapic_resume(struct sys_device *dev)
1087 unsigned long flags;
1090 if (!apic_pm_state.active)
1093 maxlvt = lapic_get_maxlvt();
1095 local_irq_save(flags);
1096 rdmsr(MSR_IA32_APICBASE, l, h);
1097 l &= ~MSR_IA32_APICBASE_BASE;
1098 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1099 wrmsr(MSR_IA32_APICBASE, l, h);
1100 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1101 apic_write(APIC_ID, apic_pm_state.apic_id);
1102 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1103 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1104 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1105 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1106 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1107 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1108 #ifdef CONFIG_X86_MCE_INTEL
1110 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1113 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1114 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1115 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1116 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1117 apic_write(APIC_ESR, 0);
1118 apic_read(APIC_ESR);
1119 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1120 apic_write(APIC_ESR, 0);
1121 apic_read(APIC_ESR);
1122 local_irq_restore(flags);
1126 static struct sysdev_class lapic_sysclass = {
1128 .resume = lapic_resume,
1129 .suspend = lapic_suspend,
1132 static struct sys_device device_lapic = {
1134 .cls = &lapic_sysclass,
1137 static void __cpuinit apic_pm_activate(void)
1139 apic_pm_state.active = 1;
1142 static int __init init_lapic_sysfs(void)
1148 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1150 error = sysdev_class_register(&lapic_sysclass);
1152 error = sysdev_register(&device_lapic);
1155 device_initcall(init_lapic_sysfs);
1157 #else /* CONFIG_PM */
1159 static void apic_pm_activate(void) { }
1161 #endif /* CONFIG_PM */
1164 * apic_is_clustered_box() -- Check if we can expect good TSC
1166 * Thus far, the major user of this is IBM's Summit2 series:
1168 * Clustered boxes may have unsynced TSC problems if they are
1169 * multi-chassis. Use available data to take a good guess.
1170 * If in doubt, go HPET.
1172 __cpuinit int apic_is_clustered_box(void)
1174 int i, clusters, zeros;
1176 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1178 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1180 for (i = 0; i < NR_CPUS; i++) {
1181 id = bios_cpu_apicid[i];
1182 if (id != BAD_APICID)
1183 __set_bit(APIC_CLUSTERID(id), clustermap);
1186 /* Problem: Partially populated chassis may not have CPUs in some of
1187 * the APIC clusters they have been allocated. Only present CPUs have
1188 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1189 * clusters are allocated sequentially, count zeros only if they are
1194 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1195 if (test_bit(i, clustermap)) {
1196 clusters += 1 + zeros;
1203 * If clusters > 2, then should be multi-chassis.
1204 * May have to revisit this when multi-core + hyperthreaded CPUs come
1205 * out, but AFAIK this will work even for them.
1207 return (clusters > 2);
1211 * APIC command line parameters
1213 static int __init apic_set_verbosity(char *str)
1216 skip_ioapic_setup = 0;
1220 if (strcmp("debug", str) == 0)
1221 apic_verbosity = APIC_DEBUG;
1222 else if (strcmp("verbose", str) == 0)
1223 apic_verbosity = APIC_VERBOSE;
1225 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1226 " use apic=verbose or apic=debug\n", str);
1232 early_param("apic", apic_set_verbosity);
1234 static __init int setup_disableapic(char *str)
1237 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1240 early_param("disableapic", setup_disableapic);
1242 /* same as disableapic, for compatibility */
1243 static __init int setup_nolapic(char *str)
1245 return setup_disableapic(str);
1247 early_param("nolapic", setup_nolapic);
1249 static int __init parse_lapic_timer_c2_ok(char *arg)
1251 local_apic_timer_c2_ok = 1;
1254 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1256 static __init int setup_noapictimer(char *str)
1258 if (str[0] != ' ' && str[0] != 0)
1260 disable_apic_timer = 1;
1263 __setup("noapictimer", setup_noapictimer);
1265 static __init int setup_apicpmtimer(char *s)
1267 apic_calibrate_pmtmr = 1;
1271 __setup("apicpmtimer", setup_apicpmtimer);