2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/module.h>
27 #include <linux/ioport.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
35 #include <asm/pgalloc.h>
36 #include <asm/mach_apic.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
45 int disable_apic_timer __cpuinitdata;
46 static int apic_calibrate_pmtmr __initdata;
48 /* Local APIC timer works in C2? */
49 int local_apic_timer_c2_ok;
50 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
52 static struct resource lapic_resource = {
54 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
57 static unsigned int calibration_result;
59 static int lapic_next_event(unsigned long delta,
60 struct clock_event_device *evt);
61 static void lapic_timer_setup(enum clock_event_mode mode,
62 struct clock_event_device *evt);
64 static void lapic_timer_broadcast(cpumask_t mask);
66 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen);
68 static struct clock_event_device lapic_clockevent = {
70 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
71 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
73 .set_mode = lapic_timer_setup,
74 .set_next_event = lapic_next_event,
75 .broadcast = lapic_timer_broadcast,
79 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
81 static int lapic_next_event(unsigned long delta,
82 struct clock_event_device *evt)
84 apic_write(APIC_TMICT, delta);
88 static void lapic_timer_setup(enum clock_event_mode mode,
89 struct clock_event_device *evt)
94 /* Lapic used as dummy for broadcast ? */
95 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
98 local_irq_save(flags);
101 case CLOCK_EVT_MODE_PERIODIC:
102 case CLOCK_EVT_MODE_ONESHOT:
103 __setup_APIC_LVTT(calibration_result,
104 mode != CLOCK_EVT_MODE_PERIODIC, 1);
106 case CLOCK_EVT_MODE_UNUSED:
107 case CLOCK_EVT_MODE_SHUTDOWN:
108 v = apic_read(APIC_LVTT);
109 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
110 apic_write(APIC_LVTT, v);
112 case CLOCK_EVT_MODE_RESUME:
113 /* Nothing to do here */
117 local_irq_restore(flags);
121 * Local APIC timer broadcast function
123 static void lapic_timer_broadcast(cpumask_t mask)
126 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
130 static void apic_pm_activate(void);
132 void apic_wait_icr_idle(void)
134 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
138 u32 safe_apic_wait_icr_idle(void)
145 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
149 } while (timeout++ < 1000);
154 void enable_NMI_through_LVT0 (void * dummy)
158 /* unmask and set to NMI */
160 apic_write(APIC_LVT0, v);
163 int lapic_get_maxlvt(void)
165 unsigned int v, maxlvt;
167 v = apic_read(APIC_LVR);
168 maxlvt = GET_APIC_MAXLVT(v);
172 void clear_local_APIC(void)
177 maxlvt = lapic_get_maxlvt();
180 * Masking an LVT entry can trigger a local APIC error
181 * if the vector is zero. Mask LVTERR first to prevent this.
184 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
185 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
188 * Careful: we have to set masks only first to deassert
189 * any level-triggered sources.
191 v = apic_read(APIC_LVTT);
192 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
193 v = apic_read(APIC_LVT0);
194 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
195 v = apic_read(APIC_LVT1);
196 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
198 v = apic_read(APIC_LVTPC);
199 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
203 * Clean APIC state for other OSs:
205 apic_write(APIC_LVTT, APIC_LVT_MASKED);
206 apic_write(APIC_LVT0, APIC_LVT_MASKED);
207 apic_write(APIC_LVT1, APIC_LVT_MASKED);
209 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
211 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
212 apic_write(APIC_ESR, 0);
216 void disconnect_bsp_APIC(int virt_wire_setup)
218 /* Go back to Virtual Wire compatibility mode */
221 /* For the spurious interrupt use vector F, and enable it */
222 value = apic_read(APIC_SPIV);
223 value &= ~APIC_VECTOR_MASK;
224 value |= APIC_SPIV_APIC_ENABLED;
226 apic_write(APIC_SPIV, value);
228 if (!virt_wire_setup) {
230 * For LVT0 make it edge triggered, active high,
231 * external and enabled
233 value = apic_read(APIC_LVT0);
234 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
235 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
236 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
237 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
238 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
239 apic_write(APIC_LVT0, value);
242 apic_write(APIC_LVT0, APIC_LVT_MASKED);
245 /* For LVT1 make it edge triggered, active high, nmi and enabled */
246 value = apic_read(APIC_LVT1);
247 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
248 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
249 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
250 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
251 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
252 apic_write(APIC_LVT1, value);
255 void disable_local_APIC(void)
262 * Disable APIC (implies clearing of registers
265 value = apic_read(APIC_SPIV);
266 value &= ~APIC_SPIV_APIC_ENABLED;
267 apic_write(APIC_SPIV, value);
270 void lapic_shutdown(void)
277 local_irq_save(flags);
279 disable_local_APIC();
281 local_irq_restore(flags);
285 * This is to verify that we're looking at a real local APIC.
286 * Check these against your board if the CPUs aren't getting
287 * started for no apparent reason.
289 int __init verify_local_APIC(void)
291 unsigned int reg0, reg1;
294 * The version register is read-only in a real APIC.
296 reg0 = apic_read(APIC_LVR);
297 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
298 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
299 reg1 = apic_read(APIC_LVR);
300 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
303 * The two version reads above should print the same
304 * numbers. If the second one is different, then we
305 * poke at a non-APIC.
311 * Check if the version looks reasonably.
313 reg1 = GET_APIC_VERSION(reg0);
314 if (reg1 == 0x00 || reg1 == 0xff)
316 reg1 = lapic_get_maxlvt();
317 if (reg1 < 0x02 || reg1 == 0xff)
321 * The ID register is read/write in a real APIC.
323 reg0 = apic_read(APIC_ID);
324 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
325 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
326 reg1 = apic_read(APIC_ID);
327 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
328 apic_write(APIC_ID, reg0);
329 if (reg1 != (reg0 ^ APIC_ID_MASK))
333 * The next two are just to see if we have sane values.
334 * They're only really relevant if we're in Virtual Wire
335 * compatibility mode, but most boxes are anymore.
337 reg0 = apic_read(APIC_LVT0);
338 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
339 reg1 = apic_read(APIC_LVT1);
340 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
345 void __init sync_Arb_IDs(void)
347 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
348 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
349 if (ver >= 0x14) /* P4 or higher */
355 apic_wait_icr_idle();
357 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
358 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
363 * An initial setup of the virtual wire mode.
365 void __init init_bsp_APIC(void)
370 * Don't do the setup now if we have a SMP BIOS as the
371 * through-I/O-APIC virtual wire mode might be active.
373 if (smp_found_config || !cpu_has_apic)
376 value = apic_read(APIC_LVR);
379 * Do not trust the local APIC being empty at bootup.
386 value = apic_read(APIC_SPIV);
387 value &= ~APIC_VECTOR_MASK;
388 value |= APIC_SPIV_APIC_ENABLED;
389 value |= APIC_SPIV_FOCUS_DISABLED;
390 value |= SPURIOUS_APIC_VECTOR;
391 apic_write(APIC_SPIV, value);
394 * Set up the virtual wire mode.
396 apic_write(APIC_LVT0, APIC_DM_EXTINT);
398 apic_write(APIC_LVT1, value);
401 void __cpuinit setup_local_APIC (void)
403 unsigned int value, maxlvt;
406 value = apic_read(APIC_LVR);
408 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
411 * Double-check whether this APIC is really registered.
412 * This is meaningless in clustered apic mode, so we skip it.
414 if (!apic_id_registered())
418 * Intel recommends to set DFR, LDR and TPR before enabling
419 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
420 * document number 292116). So here it goes...
425 * Set Task Priority to 'accept all'. We never change this
428 value = apic_read(APIC_TASKPRI);
429 value &= ~APIC_TPRI_MASK;
430 apic_write(APIC_TASKPRI, value);
433 * After a crash, we no longer service the interrupts and a pending
434 * interrupt from previous kernel might still have ISR bit set.
436 * Most probably by now CPU has serviced that pending interrupt and
437 * it might not have done the ack_APIC_irq() because it thought,
438 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
439 * does not clear the ISR bit and cpu thinks it has already serivced
440 * the interrupt. Hence a vector might get locked. It was noticed
441 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
443 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
444 value = apic_read(APIC_ISR + i*0x10);
445 for (j = 31; j >= 0; j--) {
452 * Now that we are all set up, enable the APIC
454 value = apic_read(APIC_SPIV);
455 value &= ~APIC_VECTOR_MASK;
459 value |= APIC_SPIV_APIC_ENABLED;
461 /* We always use processor focus */
464 * Set spurious IRQ vector
466 value |= SPURIOUS_APIC_VECTOR;
467 apic_write(APIC_SPIV, value);
472 * set up through-local-APIC on the BP's LINT0. This is not
473 * strictly necessary in pure symmetric-IO mode, but sometimes
474 * we delegate interrupts to the 8259A.
477 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
479 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
480 if (!smp_processor_id() && !value) {
481 value = APIC_DM_EXTINT;
482 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
485 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
486 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
489 apic_write(APIC_LVT0, value);
492 * only the BP should see the LINT1 NMI signal, obviously.
494 if (!smp_processor_id())
497 value = APIC_DM_NMI | APIC_LVT_MASKED;
498 apic_write(APIC_LVT1, value);
502 maxlvt = lapic_get_maxlvt();
503 oldvalue = apic_read(APIC_ESR);
504 value = ERROR_APIC_VECTOR; // enables sending errors
505 apic_write(APIC_LVTERR, value);
507 * spec says clear errors after enabling vector.
510 apic_write(APIC_ESR, 0);
511 value = apic_read(APIC_ESR);
512 if (value != oldvalue)
513 apic_printk(APIC_VERBOSE,
514 "ESR value after enabling vector: %08x, after %08x\n",
518 nmi_watchdog_default();
519 setup_apic_nmi_watchdog(NULL);
526 /* 'active' is true if the local APIC was enabled by us and
527 not the BIOS; this signifies that we are also responsible
528 for disabling it before entering apm/acpi suspend */
530 /* r/w apic fields */
531 unsigned int apic_id;
532 unsigned int apic_taskpri;
533 unsigned int apic_ldr;
534 unsigned int apic_dfr;
535 unsigned int apic_spiv;
536 unsigned int apic_lvtt;
537 unsigned int apic_lvtpc;
538 unsigned int apic_lvt0;
539 unsigned int apic_lvt1;
540 unsigned int apic_lvterr;
541 unsigned int apic_tmict;
542 unsigned int apic_tdcr;
543 unsigned int apic_thmr;
546 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
551 if (!apic_pm_state.active)
554 maxlvt = lapic_get_maxlvt();
556 apic_pm_state.apic_id = apic_read(APIC_ID);
557 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
558 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
559 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
560 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
561 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
563 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
564 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
565 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
566 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
567 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
568 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
569 #ifdef CONFIG_X86_MCE_INTEL
571 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
573 local_irq_save(flags);
574 disable_local_APIC();
575 local_irq_restore(flags);
579 static int lapic_resume(struct sys_device *dev)
585 if (!apic_pm_state.active)
588 maxlvt = lapic_get_maxlvt();
590 local_irq_save(flags);
591 rdmsr(MSR_IA32_APICBASE, l, h);
592 l &= ~MSR_IA32_APICBASE_BASE;
593 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
594 wrmsr(MSR_IA32_APICBASE, l, h);
595 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
596 apic_write(APIC_ID, apic_pm_state.apic_id);
597 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
598 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
599 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
600 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
601 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
602 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
603 #ifdef CONFIG_X86_MCE_INTEL
605 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
608 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
609 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
610 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
611 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
612 apic_write(APIC_ESR, 0);
614 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
615 apic_write(APIC_ESR, 0);
617 local_irq_restore(flags);
621 static struct sysdev_class lapic_sysclass = {
623 .resume = lapic_resume,
624 .suspend = lapic_suspend,
627 static struct sys_device device_lapic = {
629 .cls = &lapic_sysclass,
632 static void __cpuinit apic_pm_activate(void)
634 apic_pm_state.active = 1;
637 static int __init init_lapic_sysfs(void)
642 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
643 error = sysdev_class_register(&lapic_sysclass);
645 error = sysdev_register(&device_lapic);
648 device_initcall(init_lapic_sysfs);
650 #else /* CONFIG_PM */
652 static void apic_pm_activate(void) { }
654 #endif /* CONFIG_PM */
656 static int __init apic_set_verbosity(char *str)
659 skip_ioapic_setup = 0;
663 if (strcmp("debug", str) == 0)
664 apic_verbosity = APIC_DEBUG;
665 else if (strcmp("verbose", str) == 0)
666 apic_verbosity = APIC_VERBOSE;
668 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
669 " use apic=verbose or apic=debug\n", str);
675 early_param("apic", apic_set_verbosity);
678 * Detect and enable local APICs on non-SMP boards.
679 * Original code written by Keir Fraser.
680 * On AMD64 we trust the BIOS - if it says no APIC it is likely
681 * not correctly set up (usually the APIC timer won't work etc.)
684 static int __init detect_init_APIC (void)
687 printk(KERN_INFO "No local APIC present\n");
691 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
696 void __init init_apic_mappings(void)
698 unsigned long apic_phys;
701 * If no local APIC can be found then set up a fake all
702 * zeroes page to simulate the local APIC and another
703 * one for the IO-APIC.
705 if (!smp_found_config && detect_init_APIC()) {
706 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
707 apic_phys = __pa(apic_phys);
709 apic_phys = mp_lapic_addr;
711 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
712 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
713 APIC_BASE, apic_phys);
715 /* Put local APIC into the resource map. */
716 lapic_resource.start = apic_phys;
717 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
718 insert_resource(&iomem_resource, &lapic_resource);
721 * Fetch the APIC ID of the BSP in case we have a
722 * default configuration (or the MP table is broken).
724 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
728 * This function sets up the local APIC timer, with a timeout of
729 * 'clocks' APIC bus clock. During calibration we actually call
730 * this function twice on the boot CPU, once with a bogus timeout
731 * value, second time for real. The other (noncalibrating) CPUs
732 * call this function only once, with the real, calibrated value.
734 * We do reads before writes even if unnecessary, to get around the
735 * P5 APIC double write bug.
738 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
740 unsigned int lvtt_value, tmp_value;
742 lvtt_value = LOCAL_TIMER_VECTOR;
744 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
746 lvtt_value |= APIC_LVT_MASKED;
748 apic_write(APIC_LVTT, lvtt_value);
753 tmp_value = apic_read(APIC_TDCR);
754 apic_write(APIC_TDCR, (tmp_value
755 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
759 apic_write(APIC_TMICT, clocks);
762 static void setup_APIC_timer(void)
764 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
766 memcpy(levt, &lapic_clockevent, sizeof(*levt));
767 levt->cpumask = cpumask_of_cpu(smp_processor_id());
769 clockevents_register_device(levt);
773 * In this function we calibrate APIC bus clocks to the external
774 * timer. Unfortunately we cannot use jiffies and the timer irq
775 * to calibrate, since some later bootup code depends on getting
776 * the first irq? Ugh.
778 * We want to do the calibration only once since we
779 * want to have local timer irqs syncron. CPUs connected
780 * by the same APIC bus have the very same bus frequency.
781 * And we want to have irqs off anyways, no accidental
785 #define TICK_COUNT 100000000
787 static void __init calibrate_APIC_clock(void)
789 unsigned apic, apic_start;
790 unsigned long tsc, tsc_start;
796 * Put whatever arbitrary (but long enough) timeout
797 * value into the APIC clock, we just want to get the
798 * counter running for calibration.
800 * No interrupt enable !
802 __setup_APIC_LVTT(250000000, 0, 0);
804 apic_start = apic_read(APIC_TMCCT);
805 #ifdef CONFIG_X86_PM_TIMER
806 if (apic_calibrate_pmtmr && pmtmr_ioport) {
807 pmtimer_wait(5000); /* 5ms wait */
808 apic = apic_read(APIC_TMCCT);
809 result = (apic_start - apic) * 1000L / 5;
816 apic = apic_read(APIC_TMCCT);
818 } while ((tsc - tsc_start) < TICK_COUNT &&
819 (apic_start - apic) < TICK_COUNT);
821 result = (apic_start - apic) * 1000L * tsc_khz /
827 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
829 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
830 result / 1000 / 1000, result / 1000 % 1000);
832 /* Calculate the scaled math multiplication factor */
833 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
834 lapic_clockevent.max_delta_ns =
835 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
836 lapic_clockevent.min_delta_ns =
837 clockevent_delta2ns(0xF, &lapic_clockevent);
839 calibration_result = result / HZ;
842 void __init setup_boot_APIC_clock (void)
845 * The local apic timer can be disabled via the kernel commandline.
846 * Register the lapic timer as a dummy clock event source on SMP
847 * systems, so the broadcast mechanism is used. On UP systems simply
850 if (disable_apic_timer) {
851 printk(KERN_INFO "Disabling APIC timer\n");
852 /* No broadcast on UP ! */
853 if (num_possible_cpus() > 1)
858 printk(KERN_INFO "Using local APIC timer interrupts.\n");
859 calibrate_APIC_clock();
862 * If nmi_watchdog is set to IO_APIC, we need the
863 * PIT/HPET going. Otherwise register lapic as a dummy
866 if (nmi_watchdog != NMI_IO_APIC)
867 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
869 printk(KERN_WARNING "APIC timer registered as dummy,"
870 " due to nmi_watchdog=1!\n");
876 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
877 * C1E flag only in the secondary CPU, so when we detect the wreckage
878 * we already have enabled the boot CPU local apic timer. Check, if
879 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
880 * set the DUMMY flag again and force the broadcast mode in the
883 void __cpuinit check_boot_apic_timer_broadcast(void)
885 if (!disable_apic_timer ||
886 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
889 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
890 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
893 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id);
897 void __cpuinit setup_secondary_APIC_clock(void)
899 check_boot_apic_timer_broadcast();
903 int setup_profiling_timer(unsigned int multiplier)
908 void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector,
909 unsigned char msg_type, unsigned char mask)
911 unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE;
912 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
917 * Local timer interrupt handler. It does both profiling and
918 * process statistics/rescheduling.
920 * We do profiling in every local tick, statistics/rescheduling
921 * happen only every 'profiling multiplier' ticks. The default
922 * multiplier is 1 and it can be changed by writing the new multiplier
923 * value into /proc/profile.
926 void smp_local_timer_interrupt(void)
928 int cpu = smp_processor_id();
929 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
932 * Normally we should not be here till LAPIC has been initialized but
933 * in some cases like kdump, its possible that there is a pending LAPIC
934 * timer interrupt from previous kernel's context and is delivered in
935 * new kernel the moment interrupts are enabled.
937 * Interrupts are enabled early and LAPIC is setup much later, hence
938 * its possible that when we get here evt->event_handler is NULL.
939 * Check for event_handler being NULL and discard the interrupt as
942 if (!evt->event_handler) {
944 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
946 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
951 * the NMI deadlock-detector uses this.
953 add_pda(apic_timer_irqs, 1);
955 evt->event_handler(evt);
959 * Local APIC timer interrupt. This is the most natural way for doing
960 * local interrupts, but local timer interrupts can be emulated by
961 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
963 * [ if a single-CPU system runs an SMP kernel then we call the local
964 * interrupt as well. Thus we cannot inline the local irq ... ]
966 void smp_apic_timer_interrupt(struct pt_regs *regs)
968 struct pt_regs *old_regs = set_irq_regs(regs);
971 * NOTE! We'd better ACK the irq immediately,
972 * because timer handling can be slow.
976 * update_process_times() expects us to have done irq_enter().
977 * Besides, if we don't timer interrupts ignore the global
978 * interrupt lock, which is the WrongThing (tm) to do.
982 smp_local_timer_interrupt();
984 set_irq_regs(old_regs);
988 * apic_is_clustered_box() -- Check if we can expect good TSC
990 * Thus far, the major user of this is IBM's Summit2 series:
992 * Clustered boxes may have unsynced TSC problems if they are
993 * multi-chassis. Use available data to take a good guess.
994 * If in doubt, go HPET.
996 __cpuinit int apic_is_clustered_box(void)
998 int i, clusters, zeros;
1000 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1002 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1004 for (i = 0; i < NR_CPUS; i++) {
1005 id = bios_cpu_apicid[i];
1006 if (id != BAD_APICID)
1007 __set_bit(APIC_CLUSTERID(id), clustermap);
1010 /* Problem: Partially populated chassis may not have CPUs in some of
1011 * the APIC clusters they have been allocated. Only present CPUs have
1012 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1013 * clusters are allocated sequentially, count zeros only if they are
1018 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1019 if (test_bit(i, clustermap)) {
1020 clusters += 1 + zeros;
1027 * If clusters > 2, then should be multi-chassis.
1028 * May have to revisit this when multi-core + hyperthreaded CPUs come
1029 * out, but AFAIK this will work even for them.
1031 return (clusters > 2);
1035 * This interrupt should _never_ happen with our APIC/SMP architecture
1037 asmlinkage void smp_spurious_interrupt(void)
1043 * Check if this really is a spurious interrupt and ACK it
1044 * if it is a vectored one. Just in case...
1045 * Spurious interrupts should not be ACKed.
1047 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1048 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1051 add_pda(irq_spurious_count, 1);
1056 * This interrupt should never happen with our APIC/SMP architecture
1059 asmlinkage void smp_error_interrupt(void)
1065 /* First tickle the hardware, only then report what went on. -- REW */
1066 v = apic_read(APIC_ESR);
1067 apic_write(APIC_ESR, 0);
1068 v1 = apic_read(APIC_ESR);
1070 atomic_inc(&irq_err_count);
1072 /* Here is what the APIC error bits mean:
1075 2: Send accept error
1076 3: Receive accept error
1078 5: Send illegal vector
1079 6: Received illegal vector
1080 7: Illegal register address
1082 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1083 smp_processor_id(), v , v1);
1090 * This initializes the IO-APIC and APIC hardware if this is
1093 int __init APIC_init_uniprocessor (void)
1096 printk(KERN_INFO "Apic disabled\n");
1099 if (!cpu_has_apic) {
1101 printk(KERN_INFO "Apic disabled by BIOS\n");
1105 verify_local_APIC();
1107 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
1108 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
1112 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1116 setup_boot_APIC_clock();
1117 check_nmi_watchdog();
1121 static __init int setup_disableapic(char *str)
1124 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1127 early_param("disableapic", setup_disableapic);
1129 /* same as disableapic, for compatibility */
1130 static __init int setup_nolapic(char *str)
1132 return setup_disableapic(str);
1134 early_param("nolapic", setup_nolapic);
1136 static int __init parse_lapic_timer_c2_ok(char *arg)
1138 local_apic_timer_c2_ok = 1;
1141 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1143 static __init int setup_noapictimer(char *str)
1145 if (str[0] != ' ' && str[0] != 0)
1147 disable_apic_timer = 1;
1150 __setup("noapictimer", setup_noapictimer);
1152 static __init int setup_apicpmtimer(char *s)
1154 apic_calibrate_pmtmr = 1;
1158 __setup("apicpmtimer", setup_apicpmtimer);