2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
44 #include <mach_apic.h>
46 static int disable_apic_timer __cpuinitdata;
47 static int apic_calibrate_pmtmr __initdata;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
55 * Debug level, exported for io_apic.c
59 /* Have we found an MP table */
62 static struct resource lapic_resource = {
64 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
67 static unsigned int calibration_result;
69 static int lapic_next_event(unsigned long delta,
70 struct clock_event_device *evt);
71 static void lapic_timer_setup(enum clock_event_mode mode,
72 struct clock_event_device *evt);
73 static void lapic_timer_broadcast(cpumask_t mask);
74 static void apic_pm_activate(void);
76 static struct clock_event_device lapic_clockevent = {
78 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
79 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
81 .set_mode = lapic_timer_setup,
82 .set_next_event = lapic_next_event,
83 .broadcast = lapic_timer_broadcast,
87 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
89 static unsigned long apic_phys;
91 unsigned long mp_lapic_addr;
93 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
94 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
96 unsigned int __cpuinitdata maxcpus = NR_CPUS;
98 * Get the LAPIC version
100 static inline int lapic_get_version(void)
102 return GET_APIC_VERSION(apic_read(APIC_LVR));
106 * Check, if the APIC is integrated or a seperate chip
108 static inline int lapic_is_integrated(void)
114 * Check, whether this is a modern or a first generation APIC
116 static int modern_apic(void)
118 /* AMD systems use old APIC versions, so check the CPU */
119 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
120 boot_cpu_data.x86 >= 0xf)
122 return lapic_get_version() >= 0x14;
125 void apic_wait_icr_idle(void)
127 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
131 u32 safe_apic_wait_icr_idle(void)
138 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
142 } while (timeout++ < 1000);
148 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
150 void __cpuinit enable_NMI_through_LVT0(void)
154 /* unmask and set to NMI */
156 apic_write(APIC_LVT0, v);
160 * lapic_get_maxlvt - get the maximum number of local vector table entries
162 int lapic_get_maxlvt(void)
164 unsigned int v, maxlvt;
166 v = apic_read(APIC_LVR);
167 maxlvt = GET_APIC_MAXLVT(v);
172 * This function sets up the local APIC timer, with a timeout of
173 * 'clocks' APIC bus clock. During calibration we actually call
174 * this function twice on the boot CPU, once with a bogus timeout
175 * value, second time for real. The other (noncalibrating) CPUs
176 * call this function only once, with the real, calibrated value.
178 * We do reads before writes even if unnecessary, to get around the
179 * P5 APIC double write bug.
182 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
184 unsigned int lvtt_value, tmp_value;
186 lvtt_value = LOCAL_TIMER_VECTOR;
188 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
190 lvtt_value |= APIC_LVT_MASKED;
192 apic_write(APIC_LVTT, lvtt_value);
197 tmp_value = apic_read(APIC_TDCR);
198 apic_write(APIC_TDCR, (tmp_value
199 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
203 apic_write(APIC_TMICT, clocks);
207 * Setup extended LVT, AMD specific (K8, family 10h)
209 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
210 * MCE interrupts are supported. Thus MCE offset must be set to 0.
213 #define APIC_EILVT_LVTOFF_MCE 0
214 #define APIC_EILVT_LVTOFF_IBS 1
216 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
218 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
219 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
224 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
226 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
227 return APIC_EILVT_LVTOFF_MCE;
230 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
232 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
233 return APIC_EILVT_LVTOFF_IBS;
237 * Program the next event, relative to now
239 static int lapic_next_event(unsigned long delta,
240 struct clock_event_device *evt)
242 apic_write(APIC_TMICT, delta);
247 * Setup the lapic timer in periodic or oneshot mode
249 static void lapic_timer_setup(enum clock_event_mode mode,
250 struct clock_event_device *evt)
255 /* Lapic used as dummy for broadcast ? */
256 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
259 local_irq_save(flags);
262 case CLOCK_EVT_MODE_PERIODIC:
263 case CLOCK_EVT_MODE_ONESHOT:
264 __setup_APIC_LVTT(calibration_result,
265 mode != CLOCK_EVT_MODE_PERIODIC, 1);
267 case CLOCK_EVT_MODE_UNUSED:
268 case CLOCK_EVT_MODE_SHUTDOWN:
269 v = apic_read(APIC_LVTT);
270 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
271 apic_write(APIC_LVTT, v);
273 case CLOCK_EVT_MODE_RESUME:
274 /* Nothing to do here */
278 local_irq_restore(flags);
282 * Local APIC timer broadcast function
284 static void lapic_timer_broadcast(cpumask_t mask)
287 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
292 * Setup the local APIC timer for this CPU. Copy the initilized values
293 * of the boot CPU and register the clock event in the framework.
295 static void setup_APIC_timer(void)
297 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
299 memcpy(levt, &lapic_clockevent, sizeof(*levt));
300 levt->cpumask = cpumask_of_cpu(smp_processor_id());
302 clockevents_register_device(levt);
306 * In this function we calibrate APIC bus clocks to the external
307 * timer. Unfortunately we cannot use jiffies and the timer irq
308 * to calibrate, since some later bootup code depends on getting
309 * the first irq? Ugh.
311 * We want to do the calibration only once since we
312 * want to have local timer irqs syncron. CPUs connected
313 * by the same APIC bus have the very same bus frequency.
314 * And we want to have irqs off anyways, no accidental
318 #define TICK_COUNT 100000000
320 static void __init calibrate_APIC_clock(void)
322 unsigned apic, apic_start;
323 unsigned long tsc, tsc_start;
329 * Put whatever arbitrary (but long enough) timeout
330 * value into the APIC clock, we just want to get the
331 * counter running for calibration.
333 * No interrupt enable !
335 __setup_APIC_LVTT(250000000, 0, 0);
337 apic_start = apic_read(APIC_TMCCT);
338 #ifdef CONFIG_X86_PM_TIMER
339 if (apic_calibrate_pmtmr && pmtmr_ioport) {
340 pmtimer_wait(5000); /* 5ms wait */
341 apic = apic_read(APIC_TMCCT);
342 result = (apic_start - apic) * 1000L / 5;
349 apic = apic_read(APIC_TMCCT);
351 } while ((tsc - tsc_start) < TICK_COUNT &&
352 (apic_start - apic) < TICK_COUNT);
354 result = (apic_start - apic) * 1000L * tsc_khz /
360 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
362 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
363 result / 1000 / 1000, result / 1000 % 1000);
365 /* Calculate the scaled math multiplication factor */
366 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
367 lapic_clockevent.shift);
368 lapic_clockevent.max_delta_ns =
369 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
370 lapic_clockevent.min_delta_ns =
371 clockevent_delta2ns(0xF, &lapic_clockevent);
373 calibration_result = result / HZ;
377 * Setup the boot APIC
379 * Calibrate and verify the result.
381 void __init setup_boot_APIC_clock(void)
384 * The local apic timer can be disabled via the kernel commandline.
385 * Register the lapic timer as a dummy clock event source on SMP
386 * systems, so the broadcast mechanism is used. On UP systems simply
389 if (disable_apic_timer) {
390 printk(KERN_INFO "Disabling APIC timer\n");
391 /* No broadcast on UP ! */
392 if (num_possible_cpus() > 1) {
393 lapic_clockevent.mult = 1;
399 printk(KERN_INFO "Using local APIC timer interrupts.\n");
400 calibrate_APIC_clock();
403 * Do a sanity check on the APIC calibration result
405 if (calibration_result < (1000000 / HZ)) {
407 "APIC frequency too slow, disabling apic timer\n");
408 /* No broadcast on UP ! */
409 if (num_possible_cpus() > 1)
415 * If nmi_watchdog is set to IO_APIC, we need the
416 * PIT/HPET going. Otherwise register lapic as a dummy
419 if (nmi_watchdog != NMI_IO_APIC)
420 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
422 printk(KERN_WARNING "APIC timer registered as dummy,"
423 " due to nmi_watchdog=1!\n");
428 void __cpuinit setup_secondary_APIC_clock(void)
434 * The guts of the apic timer interrupt
436 static void local_apic_timer_interrupt(void)
438 int cpu = smp_processor_id();
439 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
442 * Normally we should not be here till LAPIC has been initialized but
443 * in some cases like kdump, its possible that there is a pending LAPIC
444 * timer interrupt from previous kernel's context and is delivered in
445 * new kernel the moment interrupts are enabled.
447 * Interrupts are enabled early and LAPIC is setup much later, hence
448 * its possible that when we get here evt->event_handler is NULL.
449 * Check for event_handler being NULL and discard the interrupt as
452 if (!evt->event_handler) {
454 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
456 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
461 * the NMI deadlock-detector uses this.
463 add_pda(apic_timer_irqs, 1);
465 evt->event_handler(evt);
469 * Local APIC timer interrupt. This is the most natural way for doing
470 * local interrupts, but local timer interrupts can be emulated by
471 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
473 * [ if a single-CPU system runs an SMP kernel then we call the local
474 * interrupt as well. Thus we cannot inline the local irq ... ]
476 void smp_apic_timer_interrupt(struct pt_regs *regs)
478 struct pt_regs *old_regs = set_irq_regs(regs);
481 * NOTE! We'd better ACK the irq immediately,
482 * because timer handling can be slow.
486 * update_process_times() expects us to have done irq_enter().
487 * Besides, if we don't timer interrupts ignore the global
488 * interrupt lock, which is the WrongThing (tm) to do.
492 local_apic_timer_interrupt();
494 set_irq_regs(old_regs);
497 int setup_profiling_timer(unsigned int multiplier)
504 * Local APIC start and shutdown
508 * clear_local_APIC - shutdown the local APIC
510 * This is called, when a CPU is disabled and before rebooting, so the state of
511 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
512 * leftovers during boot.
514 void clear_local_APIC(void)
519 /* APIC hasn't been mapped yet */
523 maxlvt = lapic_get_maxlvt();
525 * Masking an LVT entry can trigger a local APIC error
526 * if the vector is zero. Mask LVTERR first to prevent this.
529 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
530 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
533 * Careful: we have to set masks only first to deassert
534 * any level-triggered sources.
536 v = apic_read(APIC_LVTT);
537 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
538 v = apic_read(APIC_LVT0);
539 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
540 v = apic_read(APIC_LVT1);
541 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
543 v = apic_read(APIC_LVTPC);
544 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
548 * Clean APIC state for other OSs:
550 apic_write(APIC_LVTT, APIC_LVT_MASKED);
551 apic_write(APIC_LVT0, APIC_LVT_MASKED);
552 apic_write(APIC_LVT1, APIC_LVT_MASKED);
554 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
556 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
557 apic_write(APIC_ESR, 0);
562 * disable_local_APIC - clear and disable the local APIC
564 void disable_local_APIC(void)
571 * Disable APIC (implies clearing of registers
574 value = apic_read(APIC_SPIV);
575 value &= ~APIC_SPIV_APIC_ENABLED;
576 apic_write(APIC_SPIV, value);
579 void lapic_shutdown(void)
586 local_irq_save(flags);
588 disable_local_APIC();
590 local_irq_restore(flags);
594 * This is to verify that we're looking at a real local APIC.
595 * Check these against your board if the CPUs aren't getting
596 * started for no apparent reason.
598 int __init verify_local_APIC(void)
600 unsigned int reg0, reg1;
603 * The version register is read-only in a real APIC.
605 reg0 = apic_read(APIC_LVR);
606 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
607 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
608 reg1 = apic_read(APIC_LVR);
609 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
612 * The two version reads above should print the same
613 * numbers. If the second one is different, then we
614 * poke at a non-APIC.
620 * Check if the version looks reasonably.
622 reg1 = GET_APIC_VERSION(reg0);
623 if (reg1 == 0x00 || reg1 == 0xff)
625 reg1 = lapic_get_maxlvt();
626 if (reg1 < 0x02 || reg1 == 0xff)
630 * The ID register is read/write in a real APIC.
632 reg0 = read_apic_id();
633 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
634 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
635 reg1 = read_apic_id();
636 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
637 apic_write(APIC_ID, reg0);
638 if (reg1 != (reg0 ^ APIC_ID_MASK))
642 * The next two are just to see if we have sane values.
643 * They're only really relevant if we're in Virtual Wire
644 * compatibility mode, but most boxes are anymore.
646 reg0 = apic_read(APIC_LVT0);
647 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
648 reg1 = apic_read(APIC_LVT1);
649 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
655 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
657 void __init sync_Arb_IDs(void)
659 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
666 apic_wait_icr_idle();
668 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
669 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
674 * An initial setup of the virtual wire mode.
676 void __init init_bsp_APIC(void)
681 * Don't do the setup now if we have a SMP BIOS as the
682 * through-I/O-APIC virtual wire mode might be active.
684 if (smp_found_config || !cpu_has_apic)
687 value = apic_read(APIC_LVR);
690 * Do not trust the local APIC being empty at bootup.
697 value = apic_read(APIC_SPIV);
698 value &= ~APIC_VECTOR_MASK;
699 value |= APIC_SPIV_APIC_ENABLED;
700 value |= APIC_SPIV_FOCUS_DISABLED;
701 value |= SPURIOUS_APIC_VECTOR;
702 apic_write(APIC_SPIV, value);
705 * Set up the virtual wire mode.
707 apic_write(APIC_LVT0, APIC_DM_EXTINT);
709 apic_write(APIC_LVT1, value);
713 * setup_local_APIC - setup the local APIC
715 void __cpuinit setup_local_APIC(void)
721 value = apic_read(APIC_LVR);
723 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
726 * Double-check whether this APIC is really registered.
727 * This is meaningless in clustered apic mode, so we skip it.
729 if (!apic_id_registered())
733 * Intel recommends to set DFR, LDR and TPR before enabling
734 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
735 * document number 292116). So here it goes...
740 * Set Task Priority to 'accept all'. We never change this
743 value = apic_read(APIC_TASKPRI);
744 value &= ~APIC_TPRI_MASK;
745 apic_write(APIC_TASKPRI, value);
748 * After a crash, we no longer service the interrupts and a pending
749 * interrupt from previous kernel might still have ISR bit set.
751 * Most probably by now CPU has serviced that pending interrupt and
752 * it might not have done the ack_APIC_irq() because it thought,
753 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
754 * does not clear the ISR bit and cpu thinks it has already serivced
755 * the interrupt. Hence a vector might get locked. It was noticed
756 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
758 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
759 value = apic_read(APIC_ISR + i*0x10);
760 for (j = 31; j >= 0; j--) {
767 * Now that we are all set up, enable the APIC
769 value = apic_read(APIC_SPIV);
770 value &= ~APIC_VECTOR_MASK;
774 value |= APIC_SPIV_APIC_ENABLED;
776 /* We always use processor focus */
779 * Set spurious IRQ vector
781 value |= SPURIOUS_APIC_VECTOR;
782 apic_write(APIC_SPIV, value);
787 * set up through-local-APIC on the BP's LINT0. This is not
788 * strictly necessary in pure symmetric-IO mode, but sometimes
789 * we delegate interrupts to the 8259A.
792 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
794 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
795 if (!smp_processor_id() && !value) {
796 value = APIC_DM_EXTINT;
797 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
800 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
801 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
804 apic_write(APIC_LVT0, value);
807 * only the BP should see the LINT1 NMI signal, obviously.
809 if (!smp_processor_id())
812 value = APIC_DM_NMI | APIC_LVT_MASKED;
813 apic_write(APIC_LVT1, value);
817 static void __cpuinit lapic_setup_esr(void)
819 unsigned maxlvt = lapic_get_maxlvt();
821 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
823 * spec says clear errors after enabling vector.
826 apic_write(APIC_ESR, 0);
829 void __cpuinit end_local_APIC_setup(void)
832 nmi_watchdog_default();
833 setup_apic_nmi_watchdog(NULL);
838 * Detect and enable local APICs on non-SMP boards.
839 * Original code written by Keir Fraser.
840 * On AMD64 we trust the BIOS - if it says no APIC it is likely
841 * not correctly set up (usually the APIC timer won't work etc.)
843 static int __init detect_init_APIC(void)
846 printk(KERN_INFO "No local APIC present\n");
850 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
851 boot_cpu_physical_apicid = 0;
855 void __init early_init_lapic_mapping(void)
857 unsigned long phys_addr;
860 * If no local APIC can be found then go out
861 * : it means there is no mpatable and MADT
863 if (!smp_found_config)
866 phys_addr = mp_lapic_addr;
868 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
869 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
870 APIC_BASE, phys_addr);
873 * Fetch the APIC ID of the BSP in case we have a
874 * default configuration (or the MP table is broken).
876 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
880 * init_apic_mappings - initialize APIC mappings
882 void __init init_apic_mappings(void)
885 * If no local APIC can be found then set up a fake all
886 * zeroes page to simulate the local APIC and another
887 * one for the IO-APIC.
889 if (!smp_found_config && detect_init_APIC()) {
890 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
891 apic_phys = __pa(apic_phys);
893 apic_phys = mp_lapic_addr;
895 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
896 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
897 APIC_BASE, apic_phys);
900 * Fetch the APIC ID of the BSP in case we have a
901 * default configuration (or the MP table is broken).
903 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
907 * This initializes the IO-APIC and APIC hardware if this is
910 int __init APIC_init_uniprocessor(void)
913 printk(KERN_INFO "Apic disabled\n");
918 printk(KERN_INFO "Apic disabled by BIOS\n");
924 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
925 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
930 * Now enable IO-APICs, actually call clear_IO_APIC
931 * We need clear_IO_APIC before enabling vector on BP
933 if (!skip_ioapic_setup && nr_ioapics)
936 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
937 localise_nmi_watchdog();
938 end_local_APIC_setup();
940 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
944 setup_boot_APIC_clock();
945 check_nmi_watchdog();
950 * Local APIC interrupts
954 * This interrupt should _never_ happen with our APIC/SMP architecture
956 asmlinkage void smp_spurious_interrupt(void)
962 * Check if this really is a spurious interrupt and ACK it
963 * if it is a vectored one. Just in case...
964 * Spurious interrupts should not be ACKed.
966 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
967 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
970 add_pda(irq_spurious_count, 1);
975 * This interrupt should never happen with our APIC/SMP architecture
977 asmlinkage void smp_error_interrupt(void)
983 /* First tickle the hardware, only then report what went on. -- REW */
984 v = apic_read(APIC_ESR);
985 apic_write(APIC_ESR, 0);
986 v1 = apic_read(APIC_ESR);
988 atomic_inc(&irq_err_count);
990 /* Here is what the APIC error bits mean:
994 3: Receive accept error
996 5: Send illegal vector
997 6: Received illegal vector
998 7: Illegal register address
1000 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1001 smp_processor_id(), v , v1);
1005 void disconnect_bsp_APIC(int virt_wire_setup)
1007 /* Go back to Virtual Wire compatibility mode */
1008 unsigned long value;
1010 /* For the spurious interrupt use vector F, and enable it */
1011 value = apic_read(APIC_SPIV);
1012 value &= ~APIC_VECTOR_MASK;
1013 value |= APIC_SPIV_APIC_ENABLED;
1015 apic_write(APIC_SPIV, value);
1017 if (!virt_wire_setup) {
1019 * For LVT0 make it edge triggered, active high,
1020 * external and enabled
1022 value = apic_read(APIC_LVT0);
1023 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1024 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1025 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1026 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1027 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1028 apic_write(APIC_LVT0, value);
1031 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1034 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1035 value = apic_read(APIC_LVT1);
1036 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1037 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1038 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1039 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1040 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1041 apic_write(APIC_LVT1, value);
1044 void __cpuinit generic_processor_info(int apicid, int version)
1049 if (num_processors >= NR_CPUS) {
1050 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1051 " Processor ignored.\n", NR_CPUS);
1055 if (num_processors >= maxcpus) {
1056 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1057 " Processor ignored.\n", maxcpus);
1062 cpus_complement(tmp_map, cpu_present_map);
1063 cpu = first_cpu(tmp_map);
1065 physid_set(apicid, phys_cpu_present_map);
1066 if (apicid == boot_cpu_physical_apicid) {
1068 * x86_bios_cpu_apicid is required to have processors listed
1069 * in same order as logical cpu numbers. Hence the first
1070 * entry is BSP, and so on.
1074 if (apicid > max_physical_apicid)
1075 max_physical_apicid = apicid;
1077 /* are we being called early in kernel startup? */
1078 if (x86_cpu_to_apicid_early_ptr) {
1079 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
1080 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
1082 cpu_to_apicid[cpu] = apicid;
1083 bios_cpu_apicid[cpu] = apicid;
1085 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1086 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1089 cpu_set(cpu, cpu_possible_map);
1090 cpu_set(cpu, cpu_present_map);
1099 /* 'active' is true if the local APIC was enabled by us and
1100 not the BIOS; this signifies that we are also responsible
1101 for disabling it before entering apm/acpi suspend */
1103 /* r/w apic fields */
1104 unsigned int apic_id;
1105 unsigned int apic_taskpri;
1106 unsigned int apic_ldr;
1107 unsigned int apic_dfr;
1108 unsigned int apic_spiv;
1109 unsigned int apic_lvtt;
1110 unsigned int apic_lvtpc;
1111 unsigned int apic_lvt0;
1112 unsigned int apic_lvt1;
1113 unsigned int apic_lvterr;
1114 unsigned int apic_tmict;
1115 unsigned int apic_tdcr;
1116 unsigned int apic_thmr;
1119 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1121 unsigned long flags;
1124 if (!apic_pm_state.active)
1127 maxlvt = lapic_get_maxlvt();
1129 apic_pm_state.apic_id = read_apic_id();
1130 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1131 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1132 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1133 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1134 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1136 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1137 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1138 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1139 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1140 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1141 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1142 #ifdef CONFIG_X86_MCE_INTEL
1144 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1146 local_irq_save(flags);
1147 disable_local_APIC();
1148 local_irq_restore(flags);
1152 static int lapic_resume(struct sys_device *dev)
1155 unsigned long flags;
1158 if (!apic_pm_state.active)
1161 maxlvt = lapic_get_maxlvt();
1163 local_irq_save(flags);
1164 rdmsr(MSR_IA32_APICBASE, l, h);
1165 l &= ~MSR_IA32_APICBASE_BASE;
1166 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1167 wrmsr(MSR_IA32_APICBASE, l, h);
1168 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1169 apic_write(APIC_ID, apic_pm_state.apic_id);
1170 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1171 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1172 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1173 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1174 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1175 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1176 #ifdef CONFIG_X86_MCE_INTEL
1178 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1181 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1182 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1183 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1184 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1185 apic_write(APIC_ESR, 0);
1186 apic_read(APIC_ESR);
1187 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1188 apic_write(APIC_ESR, 0);
1189 apic_read(APIC_ESR);
1190 local_irq_restore(flags);
1194 static struct sysdev_class lapic_sysclass = {
1196 .resume = lapic_resume,
1197 .suspend = lapic_suspend,
1200 static struct sys_device device_lapic = {
1202 .cls = &lapic_sysclass,
1205 static void __cpuinit apic_pm_activate(void)
1207 apic_pm_state.active = 1;
1210 static int __init init_lapic_sysfs(void)
1216 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1218 error = sysdev_class_register(&lapic_sysclass);
1220 error = sysdev_register(&device_lapic);
1223 device_initcall(init_lapic_sysfs);
1225 #else /* CONFIG_PM */
1227 static void apic_pm_activate(void) { }
1229 #endif /* CONFIG_PM */
1232 * apic_is_clustered_box() -- Check if we can expect good TSC
1234 * Thus far, the major user of this is IBM's Summit2 series:
1236 * Clustered boxes may have unsynced TSC problems if they are
1237 * multi-chassis. Use available data to take a good guess.
1238 * If in doubt, go HPET.
1240 __cpuinit int apic_is_clustered_box(void)
1242 int i, clusters, zeros;
1244 u16 *bios_cpu_apicid;
1245 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1248 * there is not this kind of box with AMD CPU yet.
1249 * Some AMD box with quadcore cpu and 8 sockets apicid
1250 * will be [4, 0x23] or [8, 0x27] could be thought to
1251 * vsmp box still need checking...
1253 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1256 bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
1257 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1259 for (i = 0; i < NR_CPUS; i++) {
1260 /* are we being called early in kernel startup? */
1261 if (bios_cpu_apicid) {
1262 id = bios_cpu_apicid[i];
1264 else if (i < nr_cpu_ids) {
1266 id = per_cpu(x86_bios_cpu_apicid, i);
1273 if (id != BAD_APICID)
1274 __set_bit(APIC_CLUSTERID(id), clustermap);
1277 /* Problem: Partially populated chassis may not have CPUs in some of
1278 * the APIC clusters they have been allocated. Only present CPUs have
1279 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1280 * Since clusters are allocated sequentially, count zeros only if
1281 * they are bounded by ones.
1285 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1286 if (test_bit(i, clustermap)) {
1287 clusters += 1 + zeros;
1293 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1294 * not guaranteed to be synced between boards
1296 if (is_vsmp_box() && clusters > 1)
1300 * If clusters > 2, then should be multi-chassis.
1301 * May have to revisit this when multi-core + hyperthreaded CPUs come
1302 * out, but AFAIK this will work even for them.
1304 return (clusters > 2);
1308 * APIC command line parameters
1310 static int __init apic_set_verbosity(char *str)
1313 skip_ioapic_setup = 0;
1317 if (strcmp("debug", str) == 0)
1318 apic_verbosity = APIC_DEBUG;
1319 else if (strcmp("verbose", str) == 0)
1320 apic_verbosity = APIC_VERBOSE;
1322 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1323 " use apic=verbose or apic=debug\n", str);
1329 early_param("apic", apic_set_verbosity);
1331 static __init int setup_disableapic(char *str)
1334 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1337 early_param("disableapic", setup_disableapic);
1339 /* same as disableapic, for compatibility */
1340 static __init int setup_nolapic(char *str)
1342 return setup_disableapic(str);
1344 early_param("nolapic", setup_nolapic);
1346 static int __init parse_lapic_timer_c2_ok(char *arg)
1348 local_apic_timer_c2_ok = 1;
1351 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1353 static __init int setup_noapictimer(char *str)
1355 if (str[0] != ' ' && str[0] != 0)
1357 disable_apic_timer = 1;
1360 __setup("noapictimer", setup_noapictimer);
1362 static __init int setup_apicpmtimer(char *s)
1364 apic_calibrate_pmtmr = 1;
1368 __setup("apicpmtimer", setup_apicpmtimer);
1370 static int __init lapic_insert_resource(void)
1375 /* Put local APIC into the resource map. */
1376 lapic_resource.start = apic_phys;
1377 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1378 insert_resource(&iomem_resource, &lapic_resource);
1384 * need call insert after e820_reserve_resources()
1385 * that is using request_resource
1387 late_initcall(lapic_insert_resource);