2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
44 #include <mach_apic.h>
46 int disable_apic_timer __cpuinitdata;
47 static int apic_calibrate_pmtmr __initdata;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
55 * Debug level, exported for io_apic.c
59 static struct resource lapic_resource = {
61 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
64 static unsigned int calibration_result;
66 static int lapic_next_event(unsigned long delta,
67 struct clock_event_device *evt);
68 static void lapic_timer_setup(enum clock_event_mode mode,
69 struct clock_event_device *evt);
70 static void lapic_timer_broadcast(cpumask_t mask);
71 static void apic_pm_activate(void);
73 static struct clock_event_device lapic_clockevent = {
75 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
76 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
78 .set_mode = lapic_timer_setup,
79 .set_next_event = lapic_next_event,
80 .broadcast = lapic_timer_broadcast,
84 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
86 static unsigned long apic_phys;
88 unsigned long mp_lapic_addr;
90 /* Processor that is doing the boot up */
91 unsigned int boot_cpu_physical_apicid = -1U;
92 EXPORT_SYMBOL(boot_cpu_physical_apicid);
94 unsigned int __cpuinitdata maxcpus = NR_CPUS;
96 * Get the LAPIC version
98 static inline int lapic_get_version(void)
100 return GET_APIC_VERSION(apic_read(APIC_LVR));
104 * Check, if the APIC is integrated or a seperate chip
106 static inline int lapic_is_integrated(void)
112 * Check, whether this is a modern or a first generation APIC
114 static int modern_apic(void)
116 /* AMD systems use old APIC versions, so check the CPU */
117 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
118 boot_cpu_data.x86 >= 0xf)
120 return lapic_get_version() >= 0x14;
123 void apic_wait_icr_idle(void)
125 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
129 u32 safe_apic_wait_icr_idle(void)
136 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
140 } while (timeout++ < 1000);
146 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
148 void __cpuinit enable_NMI_through_LVT0(void)
152 /* unmask and set to NMI */
154 apic_write(APIC_LVT0, v);
158 * lapic_get_maxlvt - get the maximum number of local vector table entries
160 int lapic_get_maxlvt(void)
162 unsigned int v, maxlvt;
164 v = apic_read(APIC_LVR);
165 maxlvt = GET_APIC_MAXLVT(v);
170 * This function sets up the local APIC timer, with a timeout of
171 * 'clocks' APIC bus clock. During calibration we actually call
172 * this function twice on the boot CPU, once with a bogus timeout
173 * value, second time for real. The other (noncalibrating) CPUs
174 * call this function only once, with the real, calibrated value.
176 * We do reads before writes even if unnecessary, to get around the
177 * P5 APIC double write bug.
180 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
182 unsigned int lvtt_value, tmp_value;
184 lvtt_value = LOCAL_TIMER_VECTOR;
186 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
188 lvtt_value |= APIC_LVT_MASKED;
190 apic_write(APIC_LVTT, lvtt_value);
195 tmp_value = apic_read(APIC_TDCR);
196 apic_write(APIC_TDCR, (tmp_value
197 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
201 apic_write(APIC_TMICT, clocks);
205 * Setup extended LVT, AMD specific (K8, family 10h)
207 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
208 * MCE interrupts are supported. Thus MCE offset must be set to 0.
211 #define APIC_EILVT_LVTOFF_MCE 0
212 #define APIC_EILVT_LVTOFF_IBS 1
214 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
216 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
217 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
222 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
224 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
225 return APIC_EILVT_LVTOFF_MCE;
228 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
230 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
231 return APIC_EILVT_LVTOFF_IBS;
235 * Program the next event, relative to now
237 static int lapic_next_event(unsigned long delta,
238 struct clock_event_device *evt)
240 apic_write(APIC_TMICT, delta);
245 * Setup the lapic timer in periodic or oneshot mode
247 static void lapic_timer_setup(enum clock_event_mode mode,
248 struct clock_event_device *evt)
253 /* Lapic used as dummy for broadcast ? */
254 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
257 local_irq_save(flags);
260 case CLOCK_EVT_MODE_PERIODIC:
261 case CLOCK_EVT_MODE_ONESHOT:
262 __setup_APIC_LVTT(calibration_result,
263 mode != CLOCK_EVT_MODE_PERIODIC, 1);
265 case CLOCK_EVT_MODE_UNUSED:
266 case CLOCK_EVT_MODE_SHUTDOWN:
267 v = apic_read(APIC_LVTT);
268 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
269 apic_write(APIC_LVTT, v);
271 case CLOCK_EVT_MODE_RESUME:
272 /* Nothing to do here */
276 local_irq_restore(flags);
280 * Local APIC timer broadcast function
282 static void lapic_timer_broadcast(cpumask_t mask)
285 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
290 * Setup the local APIC timer for this CPU. Copy the initilized values
291 * of the boot CPU and register the clock event in the framework.
293 static void setup_APIC_timer(void)
295 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
297 memcpy(levt, &lapic_clockevent, sizeof(*levt));
298 levt->cpumask = cpumask_of_cpu(smp_processor_id());
300 clockevents_register_device(levt);
304 * In this function we calibrate APIC bus clocks to the external
305 * timer. Unfortunately we cannot use jiffies and the timer irq
306 * to calibrate, since some later bootup code depends on getting
307 * the first irq? Ugh.
309 * We want to do the calibration only once since we
310 * want to have local timer irqs syncron. CPUs connected
311 * by the same APIC bus have the very same bus frequency.
312 * And we want to have irqs off anyways, no accidental
316 #define TICK_COUNT 100000000
318 static void __init calibrate_APIC_clock(void)
320 unsigned apic, apic_start;
321 unsigned long tsc, tsc_start;
327 * Put whatever arbitrary (but long enough) timeout
328 * value into the APIC clock, we just want to get the
329 * counter running for calibration.
331 * No interrupt enable !
333 __setup_APIC_LVTT(250000000, 0, 0);
335 apic_start = apic_read(APIC_TMCCT);
336 #ifdef CONFIG_X86_PM_TIMER
337 if (apic_calibrate_pmtmr && pmtmr_ioport) {
338 pmtimer_wait(5000); /* 5ms wait */
339 apic = apic_read(APIC_TMCCT);
340 result = (apic_start - apic) * 1000L / 5;
347 apic = apic_read(APIC_TMCCT);
349 } while ((tsc - tsc_start) < TICK_COUNT &&
350 (apic_start - apic) < TICK_COUNT);
352 result = (apic_start - apic) * 1000L * tsc_khz /
358 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
360 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
361 result / 1000 / 1000, result / 1000 % 1000);
363 /* Calculate the scaled math multiplication factor */
364 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
365 lapic_clockevent.max_delta_ns =
366 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
367 lapic_clockevent.min_delta_ns =
368 clockevent_delta2ns(0xF, &lapic_clockevent);
370 calibration_result = result / HZ;
374 * Setup the boot APIC
376 * Calibrate and verify the result.
378 void __init setup_boot_APIC_clock(void)
381 * The local apic timer can be disabled via the kernel commandline.
382 * Register the lapic timer as a dummy clock event source on SMP
383 * systems, so the broadcast mechanism is used. On UP systems simply
386 if (disable_apic_timer) {
387 printk(KERN_INFO "Disabling APIC timer\n");
388 /* No broadcast on UP ! */
389 if (num_possible_cpus() > 1) {
390 lapic_clockevent.mult = 1;
396 printk(KERN_INFO "Using local APIC timer interrupts.\n");
397 calibrate_APIC_clock();
400 * Do a sanity check on the APIC calibration result
402 if (calibration_result < (1000000 / HZ)) {
404 "APIC frequency too slow, disabling apic timer\n");
405 /* No broadcast on UP ! */
406 if (num_possible_cpus() > 1)
412 * If nmi_watchdog is set to IO_APIC, we need the
413 * PIT/HPET going. Otherwise register lapic as a dummy
416 if (nmi_watchdog != NMI_IO_APIC)
417 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
419 printk(KERN_WARNING "APIC timer registered as dummy,"
420 " due to nmi_watchdog=1!\n");
426 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
427 * C1E flag only in the secondary CPU, so when we detect the wreckage
428 * we already have enabled the boot CPU local apic timer. Check, if
429 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
430 * set the DUMMY flag again and force the broadcast mode in the
433 void __cpuinit check_boot_apic_timer_broadcast(void)
435 if (!disable_apic_timer ||
436 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
439 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
440 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
443 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
444 &boot_cpu_physical_apicid);
448 void __cpuinit setup_secondary_APIC_clock(void)
450 check_boot_apic_timer_broadcast();
455 * The guts of the apic timer interrupt
457 static void local_apic_timer_interrupt(void)
459 int cpu = smp_processor_id();
460 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
463 * Normally we should not be here till LAPIC has been initialized but
464 * in some cases like kdump, its possible that there is a pending LAPIC
465 * timer interrupt from previous kernel's context and is delivered in
466 * new kernel the moment interrupts are enabled.
468 * Interrupts are enabled early and LAPIC is setup much later, hence
469 * its possible that when we get here evt->event_handler is NULL.
470 * Check for event_handler being NULL and discard the interrupt as
473 if (!evt->event_handler) {
475 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
477 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
482 * the NMI deadlock-detector uses this.
484 add_pda(apic_timer_irqs, 1);
486 evt->event_handler(evt);
490 * Local APIC timer interrupt. This is the most natural way for doing
491 * local interrupts, but local timer interrupts can be emulated by
492 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
494 * [ if a single-CPU system runs an SMP kernel then we call the local
495 * interrupt as well. Thus we cannot inline the local irq ... ]
497 void smp_apic_timer_interrupt(struct pt_regs *regs)
499 struct pt_regs *old_regs = set_irq_regs(regs);
502 * NOTE! We'd better ACK the irq immediately,
503 * because timer handling can be slow.
507 * update_process_times() expects us to have done irq_enter().
508 * Besides, if we don't timer interrupts ignore the global
509 * interrupt lock, which is the WrongThing (tm) to do.
513 local_apic_timer_interrupt();
515 set_irq_regs(old_regs);
518 int setup_profiling_timer(unsigned int multiplier)
525 * Local APIC start and shutdown
529 * clear_local_APIC - shutdown the local APIC
531 * This is called, when a CPU is disabled and before rebooting, so the state of
532 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
533 * leftovers during boot.
535 void clear_local_APIC(void)
537 int maxlvt = lapic_get_maxlvt();
540 /* APIC hasn't been mapped yet */
544 maxlvt = lapic_get_maxlvt();
546 * Masking an LVT entry can trigger a local APIC error
547 * if the vector is zero. Mask LVTERR first to prevent this.
550 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
551 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
554 * Careful: we have to set masks only first to deassert
555 * any level-triggered sources.
557 v = apic_read(APIC_LVTT);
558 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
559 v = apic_read(APIC_LVT0);
560 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
561 v = apic_read(APIC_LVT1);
562 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
564 v = apic_read(APIC_LVTPC);
565 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
569 * Clean APIC state for other OSs:
571 apic_write(APIC_LVTT, APIC_LVT_MASKED);
572 apic_write(APIC_LVT0, APIC_LVT_MASKED);
573 apic_write(APIC_LVT1, APIC_LVT_MASKED);
575 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
577 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
578 apic_write(APIC_ESR, 0);
583 * disable_local_APIC - clear and disable the local APIC
585 void disable_local_APIC(void)
592 * Disable APIC (implies clearing of registers
595 value = apic_read(APIC_SPIV);
596 value &= ~APIC_SPIV_APIC_ENABLED;
597 apic_write(APIC_SPIV, value);
600 void lapic_shutdown(void)
607 local_irq_save(flags);
609 disable_local_APIC();
611 local_irq_restore(flags);
615 * This is to verify that we're looking at a real local APIC.
616 * Check these against your board if the CPUs aren't getting
617 * started for no apparent reason.
619 int __init verify_local_APIC(void)
621 unsigned int reg0, reg1;
624 * The version register is read-only in a real APIC.
626 reg0 = apic_read(APIC_LVR);
627 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
628 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
629 reg1 = apic_read(APIC_LVR);
630 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
633 * The two version reads above should print the same
634 * numbers. If the second one is different, then we
635 * poke at a non-APIC.
641 * Check if the version looks reasonably.
643 reg1 = GET_APIC_VERSION(reg0);
644 if (reg1 == 0x00 || reg1 == 0xff)
646 reg1 = lapic_get_maxlvt();
647 if (reg1 < 0x02 || reg1 == 0xff)
651 * The ID register is read/write in a real APIC.
653 reg0 = read_apic_id();
654 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
655 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
656 reg1 = read_apic_id();
657 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
658 apic_write(APIC_ID, reg0);
659 if (reg1 != (reg0 ^ APIC_ID_MASK))
663 * The next two are just to see if we have sane values.
664 * They're only really relevant if we're in Virtual Wire
665 * compatibility mode, but most boxes are anymore.
667 reg0 = apic_read(APIC_LVT0);
668 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
669 reg1 = apic_read(APIC_LVT1);
670 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
676 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
678 void __init sync_Arb_IDs(void)
680 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
687 apic_wait_icr_idle();
689 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
690 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
695 * An initial setup of the virtual wire mode.
697 void __init init_bsp_APIC(void)
702 * Don't do the setup now if we have a SMP BIOS as the
703 * through-I/O-APIC virtual wire mode might be active.
705 if (smp_found_config || !cpu_has_apic)
708 value = apic_read(APIC_LVR);
711 * Do not trust the local APIC being empty at bootup.
718 value = apic_read(APIC_SPIV);
719 value &= ~APIC_VECTOR_MASK;
720 value |= APIC_SPIV_APIC_ENABLED;
721 value |= APIC_SPIV_FOCUS_DISABLED;
722 value |= SPURIOUS_APIC_VECTOR;
723 apic_write(APIC_SPIV, value);
726 * Set up the virtual wire mode.
728 apic_write(APIC_LVT0, APIC_DM_EXTINT);
730 apic_write(APIC_LVT1, value);
734 * setup_local_APIC - setup the local APIC
736 void __cpuinit setup_local_APIC(void)
741 value = apic_read(APIC_LVR);
743 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
746 * Double-check whether this APIC is really registered.
747 * This is meaningless in clustered apic mode, so we skip it.
749 if (!apic_id_registered())
753 * Intel recommends to set DFR, LDR and TPR before enabling
754 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
755 * document number 292116). So here it goes...
760 * Set Task Priority to 'accept all'. We never change this
763 value = apic_read(APIC_TASKPRI);
764 value &= ~APIC_TPRI_MASK;
765 apic_write(APIC_TASKPRI, value);
768 * After a crash, we no longer service the interrupts and a pending
769 * interrupt from previous kernel might still have ISR bit set.
771 * Most probably by now CPU has serviced that pending interrupt and
772 * it might not have done the ack_APIC_irq() because it thought,
773 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
774 * does not clear the ISR bit and cpu thinks it has already serivced
775 * the interrupt. Hence a vector might get locked. It was noticed
776 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
778 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
779 value = apic_read(APIC_ISR + i*0x10);
780 for (j = 31; j >= 0; j--) {
787 * Now that we are all set up, enable the APIC
789 value = apic_read(APIC_SPIV);
790 value &= ~APIC_VECTOR_MASK;
794 value |= APIC_SPIV_APIC_ENABLED;
796 /* We always use processor focus */
799 * Set spurious IRQ vector
801 value |= SPURIOUS_APIC_VECTOR;
802 apic_write(APIC_SPIV, value);
807 * set up through-local-APIC on the BP's LINT0. This is not
808 * strictly necessary in pure symmetric-IO mode, but sometimes
809 * we delegate interrupts to the 8259A.
812 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
814 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
815 if (!smp_processor_id() && !value) {
816 value = APIC_DM_EXTINT;
817 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
820 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
821 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
824 apic_write(APIC_LVT0, value);
827 * only the BP should see the LINT1 NMI signal, obviously.
829 if (!smp_processor_id())
832 value = APIC_DM_NMI | APIC_LVT_MASKED;
833 apic_write(APIC_LVT1, value);
836 void __cpuinit lapic_setup_esr(void)
838 unsigned maxlvt = lapic_get_maxlvt();
840 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
842 * spec says clear errors after enabling vector.
845 apic_write(APIC_ESR, 0);
848 void __cpuinit end_local_APIC_setup(void)
851 nmi_watchdog_default();
852 setup_apic_nmi_watchdog(NULL);
857 * Detect and enable local APICs on non-SMP boards.
858 * Original code written by Keir Fraser.
859 * On AMD64 we trust the BIOS - if it says no APIC it is likely
860 * not correctly set up (usually the APIC timer won't work etc.)
862 static int __init detect_init_APIC(void)
865 printk(KERN_INFO "No local APIC present\n");
869 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
870 boot_cpu_physical_apicid = 0;
874 void __init early_init_lapic_mapping(void)
876 unsigned long apic_phys;
879 * If no local APIC can be found then go out
880 * : it means there is no mpatable and MADT
882 if (!smp_found_config)
885 apic_phys = mp_lapic_addr;
887 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
888 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
889 APIC_BASE, apic_phys);
892 * Fetch the APIC ID of the BSP in case we have a
893 * default configuration (or the MP table is broken).
895 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
899 * init_apic_mappings - initialize APIC mappings
901 void __init init_apic_mappings(void)
904 * If no local APIC can be found then set up a fake all
905 * zeroes page to simulate the local APIC and another
906 * one for the IO-APIC.
908 if (!smp_found_config && detect_init_APIC()) {
909 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
910 apic_phys = __pa(apic_phys);
912 apic_phys = mp_lapic_addr;
914 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
915 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
916 APIC_BASE, apic_phys);
919 * Fetch the APIC ID of the BSP in case we have a
920 * default configuration (or the MP table is broken).
922 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
926 * This initializes the IO-APIC and APIC hardware if this is
929 int __init APIC_init_uniprocessor(void)
932 printk(KERN_INFO "Apic disabled\n");
937 printk(KERN_INFO "Apic disabled by BIOS\n");
943 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
944 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
949 * Now enable IO-APICs, actually call clear_IO_APIC
950 * We need clear_IO_APIC before enabling vector on BP
952 if (!skip_ioapic_setup && nr_ioapics)
955 end_local_APIC_setup();
957 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
961 setup_boot_APIC_clock();
962 check_nmi_watchdog();
967 * Local APIC interrupts
971 * This interrupt should _never_ happen with our APIC/SMP architecture
973 asmlinkage void smp_spurious_interrupt(void)
979 * Check if this really is a spurious interrupt and ACK it
980 * if it is a vectored one. Just in case...
981 * Spurious interrupts should not be ACKed.
983 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
984 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
987 add_pda(irq_spurious_count, 1);
992 * This interrupt should never happen with our APIC/SMP architecture
994 asmlinkage void smp_error_interrupt(void)
1000 /* First tickle the hardware, only then report what went on. -- REW */
1001 v = apic_read(APIC_ESR);
1002 apic_write(APIC_ESR, 0);
1003 v1 = apic_read(APIC_ESR);
1005 atomic_inc(&irq_err_count);
1007 /* Here is what the APIC error bits mean:
1010 2: Send accept error
1011 3: Receive accept error
1013 5: Send illegal vector
1014 6: Received illegal vector
1015 7: Illegal register address
1017 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1018 smp_processor_id(), v , v1);
1022 void disconnect_bsp_APIC(int virt_wire_setup)
1024 /* Go back to Virtual Wire compatibility mode */
1025 unsigned long value;
1027 /* For the spurious interrupt use vector F, and enable it */
1028 value = apic_read(APIC_SPIV);
1029 value &= ~APIC_VECTOR_MASK;
1030 value |= APIC_SPIV_APIC_ENABLED;
1032 apic_write(APIC_SPIV, value);
1034 if (!virt_wire_setup) {
1036 * For LVT0 make it edge triggered, active high,
1037 * external and enabled
1039 value = apic_read(APIC_LVT0);
1040 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1041 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1042 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1043 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1044 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1045 apic_write(APIC_LVT0, value);
1048 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1051 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1052 value = apic_read(APIC_LVT1);
1053 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1054 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1055 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1056 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1057 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1058 apic_write(APIC_LVT1, value);
1061 void __cpuinit generic_processor_info(int apicid, int version)
1066 if (num_processors >= NR_CPUS) {
1067 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1068 " Processor ignored.\n", NR_CPUS);
1072 if (num_processors >= maxcpus) {
1073 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1074 " Processor ignored.\n", maxcpus);
1079 cpus_complement(tmp_map, cpu_present_map);
1080 cpu = first_cpu(tmp_map);
1082 physid_set(apicid, phys_cpu_present_map);
1083 if (apicid == boot_cpu_physical_apicid) {
1085 * x86_bios_cpu_apicid is required to have processors listed
1086 * in same order as logical cpu numbers. Hence the first
1087 * entry is BSP, and so on.
1091 /* are we being called early in kernel startup? */
1092 if (x86_cpu_to_apicid_early_ptr) {
1093 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
1094 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
1096 cpu_to_apicid[cpu] = apicid;
1097 bios_cpu_apicid[cpu] = apicid;
1099 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1100 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1103 cpu_set(cpu, cpu_possible_map);
1104 cpu_set(cpu, cpu_present_map);
1113 /* 'active' is true if the local APIC was enabled by us and
1114 not the BIOS; this signifies that we are also responsible
1115 for disabling it before entering apm/acpi suspend */
1117 /* r/w apic fields */
1118 unsigned int apic_id;
1119 unsigned int apic_taskpri;
1120 unsigned int apic_ldr;
1121 unsigned int apic_dfr;
1122 unsigned int apic_spiv;
1123 unsigned int apic_lvtt;
1124 unsigned int apic_lvtpc;
1125 unsigned int apic_lvt0;
1126 unsigned int apic_lvt1;
1127 unsigned int apic_lvterr;
1128 unsigned int apic_tmict;
1129 unsigned int apic_tdcr;
1130 unsigned int apic_thmr;
1133 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1135 unsigned long flags;
1138 if (!apic_pm_state.active)
1141 maxlvt = lapic_get_maxlvt();
1143 apic_pm_state.apic_id = read_apic_id();
1144 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1145 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1146 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1147 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1148 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1150 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1151 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1152 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1153 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1154 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1155 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1156 #ifdef CONFIG_X86_MCE_INTEL
1158 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1160 local_irq_save(flags);
1161 disable_local_APIC();
1162 local_irq_restore(flags);
1166 static int lapic_resume(struct sys_device *dev)
1169 unsigned long flags;
1172 if (!apic_pm_state.active)
1175 maxlvt = lapic_get_maxlvt();
1177 local_irq_save(flags);
1178 rdmsr(MSR_IA32_APICBASE, l, h);
1179 l &= ~MSR_IA32_APICBASE_BASE;
1180 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1181 wrmsr(MSR_IA32_APICBASE, l, h);
1182 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1183 apic_write(APIC_ID, apic_pm_state.apic_id);
1184 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1185 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1186 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1187 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1188 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1189 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1190 #ifdef CONFIG_X86_MCE_INTEL
1192 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1195 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1196 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1197 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1198 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1199 apic_write(APIC_ESR, 0);
1200 apic_read(APIC_ESR);
1201 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1202 apic_write(APIC_ESR, 0);
1203 apic_read(APIC_ESR);
1204 local_irq_restore(flags);
1208 static struct sysdev_class lapic_sysclass = {
1210 .resume = lapic_resume,
1211 .suspend = lapic_suspend,
1214 static struct sys_device device_lapic = {
1216 .cls = &lapic_sysclass,
1219 static void __cpuinit apic_pm_activate(void)
1221 apic_pm_state.active = 1;
1224 static int __init init_lapic_sysfs(void)
1230 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1232 error = sysdev_class_register(&lapic_sysclass);
1234 error = sysdev_register(&device_lapic);
1237 device_initcall(init_lapic_sysfs);
1239 #else /* CONFIG_PM */
1241 static void apic_pm_activate(void) { }
1243 #endif /* CONFIG_PM */
1246 * apic_is_clustered_box() -- Check if we can expect good TSC
1248 * Thus far, the major user of this is IBM's Summit2 series:
1250 * Clustered boxes may have unsynced TSC problems if they are
1251 * multi-chassis. Use available data to take a good guess.
1252 * If in doubt, go HPET.
1254 __cpuinit int apic_is_clustered_box(void)
1256 int i, clusters, zeros;
1258 u16 *bios_cpu_apicid;
1259 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1262 * there is not this kind of box with AMD CPU yet.
1263 * Some AMD box with quadcore cpu and 8 sockets apicid
1264 * will be [4, 0x23] or [8, 0x27] could be thought to
1265 * vsmp box still need checking...
1267 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1270 bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
1271 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1273 for (i = 0; i < NR_CPUS; i++) {
1274 /* are we being called early in kernel startup? */
1275 if (bios_cpu_apicid) {
1276 id = bios_cpu_apicid[i];
1278 else if (i < nr_cpu_ids) {
1280 id = per_cpu(x86_bios_cpu_apicid, i);
1287 if (id != BAD_APICID)
1288 __set_bit(APIC_CLUSTERID(id), clustermap);
1291 /* Problem: Partially populated chassis may not have CPUs in some of
1292 * the APIC clusters they have been allocated. Only present CPUs have
1293 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1294 * Since clusters are allocated sequentially, count zeros only if
1295 * they are bounded by ones.
1299 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1300 if (test_bit(i, clustermap)) {
1301 clusters += 1 + zeros;
1307 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1308 * not guaranteed to be synced between boards
1310 if (is_vsmp_box() && clusters > 1)
1314 * If clusters > 2, then should be multi-chassis.
1315 * May have to revisit this when multi-core + hyperthreaded CPUs come
1316 * out, but AFAIK this will work even for them.
1318 return (clusters > 2);
1322 * APIC command line parameters
1324 static int __init apic_set_verbosity(char *str)
1327 skip_ioapic_setup = 0;
1331 if (strcmp("debug", str) == 0)
1332 apic_verbosity = APIC_DEBUG;
1333 else if (strcmp("verbose", str) == 0)
1334 apic_verbosity = APIC_VERBOSE;
1336 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1337 " use apic=verbose or apic=debug\n", str);
1343 early_param("apic", apic_set_verbosity);
1345 static __init int setup_disableapic(char *str)
1348 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1351 early_param("disableapic", setup_disableapic);
1353 /* same as disableapic, for compatibility */
1354 static __init int setup_nolapic(char *str)
1356 return setup_disableapic(str);
1358 early_param("nolapic", setup_nolapic);
1360 static int __init parse_lapic_timer_c2_ok(char *arg)
1362 local_apic_timer_c2_ok = 1;
1365 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1367 static __init int setup_noapictimer(char *str)
1369 if (str[0] != ' ' && str[0] != 0)
1371 disable_apic_timer = 1;
1374 __setup("noapictimer", setup_noapictimer);
1376 static __init int setup_apicpmtimer(char *s)
1378 apic_calibrate_pmtmr = 1;
1382 __setup("apicpmtimer", setup_apicpmtimer);
1384 static int __init lapic_insert_resource(void)
1389 /* Put local APIC into the resource map. */
1390 lapic_resource.start = apic_phys;
1391 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1392 insert_resource(&iomem_resource, &lapic_resource);
1398 * need call insert after e820_reserve_resources()
1399 * that is using request_resource
1401 late_initcall(lapic_insert_resource);