1 /* tsb.S: Sparc64 TSB table handling.
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
7 #include <asm/hypervisor.h>
12 /* Invoked from TLB miss handler, we are in the
13 * MMU global registers and they are setup like
16 * %g1: TSB entry pointer
17 * %g2: available temporary
18 * %g3: FAULT_CODE_{D,I}TLB
19 * %g4: available temporary
20 * %g5: available temporary
22 * %g7: available temporary, will be loaded by us with
23 * the physical address base of the linux page
24 * tables for the current address space
27 mov TLB_TAG_ACCESS, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
29 ldxa [%g4] ASI_DMMU, %g4
32 mov TLB_TAG_ACCESS, %g4
33 ba,pt %xcc, tsb_miss_page_table_walk
34 ldxa [%g4] ASI_IMMU, %g4
36 /* At this point we have:
37 * %g4 -- missing virtual address
38 * %g1 -- TSB entry address
39 * %g6 -- TAG TARGET (vaddr >> 22)
41 tsb_miss_page_table_walk:
42 TRAP_LOAD_PGD_PHYS(%g7, %g5)
44 /* And now we have the PGD base physical address in %g7. */
45 tsb_miss_page_table_walk_sun4v_fastpath:
46 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
49 TSB_LOCK_TAG(%g1, %g2, %g7)
51 /* Load and check PTE. */
52 ldxa [%g5] ASI_PHYS_USE_EC, %g5
54 sllx %g7, TSB_TAG_INVALID_BIT, %g7
55 brgez,a,pn %g5, tsb_do_fault
58 /* If it is larger than the base page size, don't
59 * bother putting it into the TSB.
61 sethi %hi(_PAGE_ALL_SZ_BITS), %g7
62 ldx [%g7 + %lo(_PAGE_ALL_SZ_BITS)], %g7
64 sethi %hi(_PAGE_SZBITS), %g7
65 ldx [%g7 + %lo(_PAGE_SZBITS)], %g7
68 sllx %g7, TSB_TAG_INVALID_BIT, %g7
69 bne,a,pn %xcc, tsb_tlb_reload
72 TSB_WRITE(%g1, %g5, %g6)
74 /* Finally, load TLB and return from trap. */
76 cmp %g3, FAULT_CODE_DTLB
77 bne,pn %xcc, tsb_itlb_load
82 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
84 .section .sun4v_2insn_patch, "ax"
90 /* For sun4v the ASI_DTLB_DATA_IN store and the retry
91 * instruction get nop'd out and we get here to branch
92 * to the sun4v tlb load code. The registers are setup
99 * The sun4v TLB load wants the PTE in %g3 so we fix that
102 ba,pt %xcc, sun4v_dtlb_load
106 /* Executable bit must be set. */
107 661: andcc %g5, _PAGE_EXEC_4U, %g0
108 .section .sun4v_1insn_patch, "ax"
110 andcc %g5, _PAGE_EXEC_4V, %g0
113 be,pn %xcc, tsb_do_fault
116 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
118 .section .sun4v_2insn_patch, "ax"
124 /* For sun4v the ASI_ITLB_DATA_IN store and the retry
125 * instruction get nop'd out and we get here to branch
126 * to the sun4v tlb load code. The registers are setup
133 * The sun4v TLB load wants the PTE in %g3 so we fix that
136 ba,pt %xcc, sun4v_itlb_load
139 /* No valid entry in the page tables, do full fault
145 cmp %g3, FAULT_CODE_DTLB
147 661: rdpr %pstate, %g5
148 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
149 .section .sun4v_2insn_patch, "ax"
152 ldxa [%g0] ASI_SCRATCHPAD, %g4
155 bne,pn %xcc, tsb_do_itlb_fault
162 661: mov TLB_TAG_ACCESS, %g4
163 ldxa [%g4] ASI_DMMU, %g5
164 .section .sun4v_2insn_patch, "ax"
166 ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
170 be,pt %xcc, sparc64_realfault_common
171 mov FAULT_CODE_DTLB, %g4
172 ba,pt %xcc, winfix_trampoline
177 ba,pt %xcc, sparc64_realfault_common
178 mov FAULT_CODE_ITLB, %g4
180 .globl sparc64_realfault_common
181 sparc64_realfault_common:
182 /* fault code in %g4, fault address in %g5, etrap will
183 * preserve these two values in %l4 and %l5 respectively
185 ba,pt %xcc, etrap ! Save trap state
187 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
188 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
189 call do_sparc64_fault ! Call fault handler
190 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
191 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
192 nop ! Delay slot (fill me)
195 rdpr %tpc, %g3 ! Prepare winfixup TNPC
196 or %g3, 0x7c, %g3 ! Compute branch offset
197 wrpr %g3, %tnpc ! Write it into TNPC
200 /* Insert an entry into the TSB.
202 * %o0: TSB entry pointer (virt or phys address)
210 wrpr %o5, PSTATE_IE, %pstate
211 TSB_LOCK_TAG(%o0, %g2, %g3)
212 TSB_WRITE(%o0, %o2, %o1)
217 /* Flush the given TSB entry if it has the matching
220 * %o0: TSB entry pointer (virt or phys address)
226 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
227 1: TSB_LOAD_TAG(%o0, %g1)
235 sllx %o3, TSB_TAG_INVALID_BIT, %o3
236 TSB_CAS_TAG(%o0, %g1, %o3)
243 /* Reload MMU related context switch state at
246 * %o0: page table physical address
247 * %o1: TSB register value
248 * %o2: TSB virtual address
249 * %o3: TSB mapping locked PTE
250 * %o4: Hypervisor TSB descriptor physical address
252 * We have to run this whole thing with interrupts
253 * disabled so that the current cpu doesn't change
257 .globl __tsb_context_switch
258 __tsb_context_switch:
260 wrpr %o5, PSTATE_IE, %pstate
262 ldub [%g6 + TI_CPU], %g1
263 sethi %hi(trap_block), %g2
264 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
265 or %g2, %lo(trap_block), %g2
267 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
269 sethi %hi(tlb_type), %g1
270 lduw [%g1 + %lo(tlb_type)], %g1
275 /* Hypervisor TSB switch. */
276 mov SCRATCHPAD_UTSBREG1, %g1
277 stxa %o1, [%g1] ASI_SCRATCHPAD
279 mov SCRATCHPAD_UTSBREG2, %g1
280 stxa %g2, [%g1] ASI_SCRATCHPAD
282 /* Save away %o5's %pstate, we have to use %o5 for
283 * the hypervisor call.
287 mov HV_FAST_MMU_TSB_CTXNON0, %o5
292 /* Finish up and restore %o5. */
296 /* SUN4U TSB switch. */
298 stxa %o1, [%g1] ASI_DMMU
300 stxa %o1, [%g1] ASI_IMMU
306 sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
307 mov TLB_TAG_ACCESS, %g1
308 lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
309 stxa %o2, [%g1] ASI_DMMU
312 stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS