1 /* tsb.S: Sparc64 TSB table handling.
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
11 /* Invoked from TLB miss handler, we are in the
12 * MMU global registers and they are setup like
15 * %g1: TSB entry pointer
16 * %g2: available temporary
17 * %g3: FAULT_CODE_{D,I}TLB
18 * %g4: available temporary
19 * %g5: available temporary
21 * %g7: available temporary, will be loaded by us with
22 * the physical address base of the linux page
23 * tables for the current address space
26 mov TLB_TAG_ACCESS, %g4
27 ldxa [%g4] ASI_DMMU, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
32 mov TLB_TAG_ACCESS, %g4
33 ldxa [%g4] ASI_IMMU, %g4
34 ba,pt %xcc, tsb_miss_page_table_walk
37 /* The sun4v TLB miss handlers jump directly here instead
38 * of tsb_miss_{d,i}tlb with the missing virtual address
39 * already loaded into %g4.
41 tsb_miss_page_table_walk:
42 TRAP_LOAD_PGD_PHYS(%g7, %g5)
44 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
47 TSB_LOCK_TAG(%g1, %g2, %g7)
49 /* Load and check PTE. */
50 ldxa [%g5] ASI_PHYS_USE_EC, %g5
51 brgez,a,pn %g5, tsb_do_fault
54 /* If it is larger than the base page size, don't
55 * bother putting it into the TSB.
58 sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g7
60 sethi %hi(_PAGE_SZBITS >> 32), %g7
62 bne,a,pn %xcc, tsb_tlb_reload
65 TSB_WRITE(%g1, %g5, %g6)
67 /* Finally, load TLB and return from trap. */
69 cmp %g3, FAULT_CODE_DTLB
70 bne,pn %xcc, tsb_itlb_load
75 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
77 .section .sun4v_2insn_patch, "ax"
83 /* For sun4v the ASI_DTLB_DATA_IN store and the retry
84 * instruction get nop'd out and we get here to branch
85 * to the sun4v tlb load code. The registers are setup
92 * The sun4v TLB load wants the PTE in %g3 so we fix that
95 ba,pt %xcc, sun4v_dtlb_load
100 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
102 .section .sun4v_2insn_patch, "ax"
108 /* For sun4v the ASI_ITLB_DATA_IN store and the retry
109 * instruction get nop'd out and we get here to branch
110 * to the sun4v tlb load code. The registers are setup
117 * The sun4v TLB load wants the PTE in %g3 so we fix that
120 ba,pt %xcc, sun4v_itlb_load
123 /* No valid entry in the page tables, do full fault
129 cmp %g3, FAULT_CODE_DTLB
131 661: rdpr %pstate, %g5
132 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
133 .section .sun4v_2insn_patch, "ax"
139 bne,pn %xcc, tsb_do_itlb_fault
146 661: mov TLB_TAG_ACCESS, %g4
147 ldxa [%g4] ASI_DMMU, %g5
148 .section .sun4v_2insn_patch, "ax"
154 be,pt %xcc, sparc64_realfault_common
155 mov FAULT_CODE_DTLB, %g4
156 ba,pt %xcc, winfix_trampoline
161 ba,pt %xcc, sparc64_realfault_common
162 mov FAULT_CODE_ITLB, %g4
164 .globl sparc64_realfault_common
165 sparc64_realfault_common:
166 /* fault code in %g4, fault address in %g5, etrap will
167 * preserve these two values in %l4 and %l5 respectively
169 ba,pt %xcc, etrap ! Save trap state
171 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
172 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
173 call do_sparc64_fault ! Call fault handler
174 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
175 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
176 nop ! Delay slot (fill me)
179 rdpr %tpc, %g3 ! Prepare winfixup TNPC
180 or %g3, 0x7c, %g3 ! Compute branch offset
181 wrpr %g3, %tnpc ! Write it into TNPC
184 /* Insert an entry into the TSB.
186 * %o0: TSB entry pointer (virt or phys address)
194 wrpr %o5, PSTATE_IE, %pstate
195 TSB_LOCK_TAG(%o0, %g2, %g3)
196 TSB_WRITE(%o0, %o2, %o1)
201 /* Flush the given TSB entry if it has the matching
204 * %o0: TSB entry pointer (virt or phys address)
210 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
211 1: TSB_LOAD_TAG(%o0, %g1)
219 TSB_CAS_TAG(%o0, %g1, %o3)
226 /* Reload MMU related context switch state at
229 * %o0: page table physical address
230 * %o1: TSB register value
231 * %o2: TSB virtual address
232 * %o3: TSB mapping locked PTE
234 * We have to run this whole thing with interrupts
235 * disabled so that the current cpu doesn't change
239 .globl __tsb_context_switch
240 __tsb_context_switch:
242 wrpr %o5, PSTATE_IE, %pstate
244 ldub [%g6 + TI_CPU], %g1
245 sethi %hi(trap_block), %g2
246 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
247 or %g2, %lo(trap_block), %g2
249 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
251 661: mov TSB_REG, %g1
252 stxa %o1, [%g1] ASI_DMMU
253 .section .sun4v_2insn_patch, "ax"
255 mov SCRATCHPAD_UTSBREG1, %g1
256 stxa %o1, [%g1] ASI_SCRATCHPAD
261 661: stxa %o1, [%g1] ASI_IMMU
263 .section .sun4v_2insn_patch, "ax"
272 sethi %hi(sparc64_highest_unlocked_tlb_ent), %o4
273 mov TLB_TAG_ACCESS, %g1
274 lduw [%o4 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
275 stxa %o2, [%g1] ASI_DMMU
278 stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS