1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/lmb.h>
26 #include <asm/ptrace.h>
27 #include <asm/atomic.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/cpudata.h>
31 #include <asm/hvtramp.h>
33 #include <asm/timer.h>
36 #include <asm/irq_regs.h>
38 #include <asm/pgtable.h>
39 #include <asm/oplib.h>
40 #include <asm/uaccess.h>
41 #include <asm/starfire.h>
43 #include <asm/sections.h>
45 #include <asm/mdesc.h>
47 #include <asm/hypervisor.h>
49 int sparc64_multi_core __read_mostly;
51 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
52 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
53 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
54 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
55 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
57 EXPORT_SYMBOL(cpu_possible_map);
58 EXPORT_SYMBOL(cpu_online_map);
59 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
60 EXPORT_SYMBOL(cpu_core_map);
62 static cpumask_t smp_commenced_mask;
64 void smp_info(struct seq_file *m)
68 seq_printf(m, "State:\n");
69 for_each_online_cpu(i)
70 seq_printf(m, "CPU%d:\t\tonline\n", i);
73 void smp_bogo(struct seq_file *m)
77 for_each_online_cpu(i)
79 "Cpu%dClkTck\t: %016lx\n",
80 i, cpu_data(i).clock_tick);
83 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
85 extern void setup_sparc64_timer(void);
87 static volatile unsigned long callin_flag = 0;
89 void __cpuinit smp_callin(void)
91 int cpuid = hard_smp_processor_id();
93 __local_per_cpu_offset = __per_cpu_offset(cpuid);
95 if (tlb_type == hypervisor)
96 sun4v_ktsb_register();
100 setup_sparc64_timer();
102 if (cheetah_pcache_forced_on)
103 cheetah_enable_pcache();
108 __asm__ __volatile__("membar #Sync\n\t"
109 "flush %%g6" : : : "memory");
111 /* Clear this or we will die instantly when we
112 * schedule back to this idler...
114 current_thread_info()->new_child = 0;
116 /* Attach to the address space of init_task. */
117 atomic_inc(&init_mm.mm_count);
118 current->active_mm = &init_mm;
120 while (!cpu_isset(cpuid, smp_commenced_mask))
123 spin_lock(&call_lock);
124 cpu_set(cpuid, cpu_online_map);
125 spin_unlock(&call_lock);
127 /* idle thread is expected to have preempt disabled */
133 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
134 panic("SMP bolixed\n");
137 /* This tick register synchronization scheme is taken entirely from
138 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
140 * The only change I've made is to rework it so that the master
141 * initiates the synchonization instead of the slave. -DaveM
145 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
147 #define NUM_ROUNDS 64 /* magic value */
148 #define NUM_ITERS 5 /* likewise */
150 static DEFINE_SPINLOCK(itc_sync_lock);
151 static unsigned long go[SLAVE + 1];
153 #define DEBUG_TICK_SYNC 0
155 static inline long get_delta (long *rt, long *master)
157 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
158 unsigned long tcenter, t0, t1, tm;
161 for (i = 0; i < NUM_ITERS; i++) {
162 t0 = tick_ops->get_tick();
165 while (!(tm = go[SLAVE]))
169 t1 = tick_ops->get_tick();
171 if (t1 - t0 < best_t1 - best_t0)
172 best_t0 = t0, best_t1 = t1, best_tm = tm;
175 *rt = best_t1 - best_t0;
176 *master = best_tm - best_t0;
178 /* average best_t0 and best_t1 without overflow: */
179 tcenter = (best_t0/2 + best_t1/2);
180 if (best_t0 % 2 + best_t1 % 2 == 2)
182 return tcenter - best_tm;
185 void smp_synchronize_tick_client(void)
187 long i, delta, adj, adjust_latency = 0, done = 0;
188 unsigned long flags, rt, master_time_stamp, bound;
191 long rt; /* roundtrip time */
192 long master; /* master's timestamp */
193 long diff; /* difference between midpoint and master's timestamp */
194 long lat; /* estimate of itc adjustment latency */
203 local_irq_save(flags);
205 for (i = 0; i < NUM_ROUNDS; i++) {
206 delta = get_delta(&rt, &master_time_stamp);
208 done = 1; /* let's lock on to this... */
214 adjust_latency += -delta;
215 adj = -delta + adjust_latency/4;
219 tick_ops->add_tick(adj);
223 t[i].master = master_time_stamp;
225 t[i].lat = adjust_latency/4;
229 local_irq_restore(flags);
232 for (i = 0; i < NUM_ROUNDS; i++)
233 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
234 t[i].rt, t[i].master, t[i].diff, t[i].lat);
237 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
238 "(last diff %ld cycles, maxerr %lu cycles)\n",
239 smp_processor_id(), delta, rt);
242 static void smp_start_sync_tick_client(int cpu);
244 static void smp_synchronize_one_tick(int cpu)
246 unsigned long flags, i;
250 smp_start_sync_tick_client(cpu);
252 /* wait for client to be ready */
256 /* now let the client proceed into his loop */
260 spin_lock_irqsave(&itc_sync_lock, flags);
262 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
267 go[SLAVE] = tick_ops->get_tick();
271 spin_unlock_irqrestore(&itc_sync_lock, flags);
274 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
275 /* XXX Put this in some common place. XXX */
276 static unsigned long kimage_addr_to_ra(void *p)
278 unsigned long val = (unsigned long) p;
280 return kern_base + (val - KERNBASE);
283 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
285 extern unsigned long sparc64_ttable_tl0;
286 extern unsigned long kern_locked_tte_data;
287 struct hvtramp_descr *hdesc;
288 unsigned long trampoline_ra;
289 struct trap_per_cpu *tb;
290 u64 tte_vaddr, tte_data;
291 unsigned long hv_err;
294 hdesc = kzalloc(sizeof(*hdesc) +
295 (sizeof(struct hvtramp_mapping) *
296 num_kernel_image_mappings - 1),
299 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
305 hdesc->num_mappings = num_kernel_image_mappings;
307 tb = &trap_block[cpu];
310 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
311 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
313 hdesc->thread_reg = thread_reg;
315 tte_vaddr = (unsigned long) KERNBASE;
316 tte_data = kern_locked_tte_data;
318 for (i = 0; i < hdesc->num_mappings; i++) {
319 hdesc->maps[i].vaddr = tte_vaddr;
320 hdesc->maps[i].tte = tte_data;
321 tte_vaddr += 0x400000;
322 tte_data += 0x400000;
325 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
327 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
328 kimage_addr_to_ra(&sparc64_ttable_tl0),
331 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
332 "gives error %lu\n", hv_err);
336 extern unsigned long sparc64_cpu_startup;
338 /* The OBP cpu startup callback truncates the 3rd arg cookie to
339 * 32-bits (I think) so to be safe we have it read the pointer
340 * contained here so we work on >4GB machines. -DaveM
342 static struct thread_info *cpu_new_thread = NULL;
344 static int __devinit smp_boot_one_cpu(unsigned int cpu)
346 struct trap_per_cpu *tb = &trap_block[cpu];
347 unsigned long entry =
348 (unsigned long)(&sparc64_cpu_startup);
349 unsigned long cookie =
350 (unsigned long)(&cpu_new_thread);
351 struct task_struct *p;
358 cpu_new_thread = task_thread_info(p);
360 if (tlb_type == hypervisor) {
361 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
362 if (ldom_domaining_enabled)
363 ldom_startcpu_cpuid(cpu,
364 (unsigned long) cpu_new_thread);
367 prom_startcpu_cpuid(cpu, entry, cookie);
369 struct device_node *dp = of_find_node_by_cpuid(cpu);
371 prom_startcpu(dp->node, entry, cookie);
374 for (timeout = 0; timeout < 50000; timeout++) {
383 printk("Processor %d is stuck.\n", cpu);
386 cpu_new_thread = NULL;
396 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
401 if (this_is_starfire) {
402 /* map to real upaid */
403 cpu = (((cpu & 0x3c) << 1) |
404 ((cpu & 0x40) >> 4) |
408 target = (cpu << 14) | 0x70;
410 /* Ok, this is the real Spitfire Errata #54.
411 * One must read back from a UDB internal register
412 * after writes to the UDB interrupt dispatch, but
413 * before the membar Sync for that write.
414 * So we use the high UDB control register (ASI 0x7f,
415 * ADDR 0x20) for the dummy read. -DaveM
418 __asm__ __volatile__(
419 "wrpr %1, %2, %%pstate\n\t"
420 "stxa %4, [%0] %3\n\t"
421 "stxa %5, [%0+%8] %3\n\t"
423 "stxa %6, [%0+%8] %3\n\t"
425 "stxa %%g0, [%7] %3\n\t"
428 "ldxa [%%g1] 0x7f, %%g0\n\t"
431 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
432 "r" (data0), "r" (data1), "r" (data2), "r" (target),
433 "r" (0x10), "0" (tmp)
436 /* NOTE: PSTATE_IE is still clear. */
439 __asm__ __volatile__("ldxa [%%g0] %1, %0"
441 : "i" (ASI_INTR_DISPATCH_STAT));
443 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
450 } while (result & 0x1);
451 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
454 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
455 smp_processor_id(), result);
462 static inline void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
467 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
468 for_each_cpu_mask_nr(i, *mask)
469 spitfire_xcall_helper(data0, data1, data2, pstate, i);
472 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
473 * packet, but we have no use for that. However we do take advantage of
474 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
476 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask_p)
478 u64 pstate, ver, busy_mask;
479 int nack_busy_id, is_jbus, need_more;
482 if (cpus_empty(*mask_p))
487 /* Unfortunately, someone at Sun had the brilliant idea to make the
488 * busy/nack fields hard-coded by ITID number for this Ultra-III
489 * derivative processor.
491 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
492 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
493 (ver >> 32) == __SERRANO_ID);
495 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
499 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
500 : : "r" (pstate), "i" (PSTATE_IE));
502 /* Setup the dispatch data registers. */
503 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
504 "stxa %1, [%4] %6\n\t"
505 "stxa %2, [%5] %6\n\t"
508 : "r" (data0), "r" (data1), "r" (data2),
509 "r" (0x40), "r" (0x50), "r" (0x60),
517 for_each_cpu_mask_nr(i, mask) {
518 u64 target = (i << 14) | 0x70;
521 busy_mask |= (0x1UL << (i * 2));
523 target |= (nack_busy_id << 24);
524 busy_mask |= (0x1UL <<
527 __asm__ __volatile__(
528 "stxa %%g0, [%0] %1\n\t"
531 : "r" (target), "i" (ASI_INTR_W));
533 if (nack_busy_id == 32) {
540 /* Now, poll for completion. */
542 u64 dispatch_stat, nack_mask;
545 stuck = 100000 * nack_busy_id;
546 nack_mask = busy_mask << 1;
548 __asm__ __volatile__("ldxa [%%g0] %1, %0"
549 : "=r" (dispatch_stat)
550 : "i" (ASI_INTR_DISPATCH_STAT));
551 if (!(dispatch_stat & (busy_mask | nack_mask))) {
552 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
554 if (unlikely(need_more)) {
556 for_each_cpu_mask_nr(i, mask) {
568 } while (dispatch_stat & busy_mask);
570 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
573 if (dispatch_stat & busy_mask) {
574 /* Busy bits will not clear, continue instead
575 * of freezing up on this cpu.
577 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
578 smp_processor_id(), dispatch_stat);
580 int i, this_busy_nack = 0;
582 /* Delay some random time with interrupts enabled
583 * to prevent deadlock.
585 udelay(2 * nack_busy_id);
587 /* Clear out the mask bits for cpus which did not
590 for_each_cpu_mask_nr(i, mask) {
594 check_mask = (0x2UL << (2*i));
596 check_mask = (0x2UL <<
598 if ((dispatch_stat & check_mask) == 0)
601 if (this_busy_nack == 64)
610 /* Multi-cpu list version. */
611 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
613 int cnt, retries, this_cpu, prev_sent, i;
614 unsigned long status;
615 cpumask_t error_mask;
616 struct trap_per_cpu *tb;
620 if (cpus_empty(*mask))
623 this_cpu = smp_processor_id();
624 tb = &trap_block[this_cpu];
626 mondo = __va(tb->cpu_mondo_block_pa);
632 cpu_list = __va(tb->cpu_list_pa);
634 /* Setup the initial cpu list. */
636 for_each_cpu_mask_nr(i, *mask)
639 cpus_clear(error_mask);
643 int forward_progress, n_sent;
645 status = sun4v_cpu_mondo_send(cnt,
647 tb->cpu_mondo_block_pa);
649 /* HV_EOK means all cpus received the xcall, we're done. */
650 if (likely(status == HV_EOK))
653 /* First, see if we made any forward progress.
655 * The hypervisor indicates successful sends by setting
656 * cpu list entries to the value 0xffff.
659 for (i = 0; i < cnt; i++) {
660 if (likely(cpu_list[i] == 0xffff))
664 forward_progress = 0;
665 if (n_sent > prev_sent)
666 forward_progress = 1;
670 /* If we get a HV_ECPUERROR, then one or more of the cpus
671 * in the list are in error state. Use the cpu_state()
672 * hypervisor call to find out which cpus are in error state.
674 if (unlikely(status == HV_ECPUERROR)) {
675 for (i = 0; i < cnt; i++) {
683 err = sun4v_cpu_state(cpu);
685 err == HV_CPU_STATE_ERROR) {
686 cpu_list[i] = 0xffff;
687 cpu_set(cpu, error_mask);
690 } else if (unlikely(status != HV_EWOULDBLOCK))
691 goto fatal_mondo_error;
693 /* Don't bother rewriting the CPU list, just leave the
694 * 0xffff and non-0xffff entries in there and the
695 * hypervisor will do the right thing.
697 * Only advance timeout state if we didn't make any
700 if (unlikely(!forward_progress)) {
701 if (unlikely(++retries > 10000))
702 goto fatal_mondo_timeout;
704 /* Delay a little bit to let other cpus catch up
705 * on their cpu mondo queue work.
711 if (unlikely(!cpus_empty(error_mask)))
712 goto fatal_mondo_cpu_error;
716 fatal_mondo_cpu_error:
717 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
718 "were in error state\n",
720 printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
721 for_each_cpu_mask_nr(i, error_mask)
727 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
728 " progress after %d retries.\n",
730 goto dump_cpu_list_and_out;
733 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
735 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
736 "mondo_block_pa(%lx)\n",
737 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
739 dump_cpu_list_and_out:
740 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
741 for (i = 0; i < cnt; i++)
742 printk("%u ", cpu_list[i]);
746 static void (*xcall_deliver_impl)(u64, u64, u64, const cpumask_t *);
748 static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
752 /* We have to do this whole thing with interrupts fully disabled.
753 * Otherwise if we send an xcall from interrupt context it will
754 * corrupt both our mondo block and cpu list state.
756 * One consequence of this is that we cannot use timeout mechanisms
757 * that depend upon interrupts being delivered locally. So, for
758 * example, we cannot sample jiffies and expect it to advance.
760 * Fortunately, udelay() uses %stick/%tick so we can use that.
762 local_irq_save(flags);
763 xcall_deliver_impl(data0, data1, data2, mask);
764 local_irq_restore(flags);
767 /* Send cross call to all processors mentioned in MASK_P
768 * except self. Really, there are only two cases currently,
769 * "&cpu_online_map" and "&mm->cpu_vm_mask".
771 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask_p)
773 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
774 int this_cpu = get_cpu();
778 if (mask_p != &cpu_online_map)
779 cpus_and(mask, mask, cpu_online_map);
780 cpu_clear(this_cpu, mask);
782 xcall_deliver(data0, data1, data2, &mask);
783 /* NOTE: Caller runs local copy on master. */
788 extern unsigned long xcall_sync_tick;
790 static void smp_start_sync_tick_client(int cpu)
792 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
793 &cpumask_of_cpu(cpu));
796 extern unsigned long xcall_call_function;
798 void arch_send_call_function_ipi(cpumask_t mask)
800 xcall_deliver((u64) &xcall_call_function, 0, 0, &mask);
803 extern unsigned long xcall_call_function_single;
805 void arch_send_call_function_single_ipi(int cpu)
807 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
808 &cpumask_of_cpu(cpu));
811 /* Send cross call to all processors except self. */
812 #define smp_cross_call(func, ctx, data1, data2) \
813 smp_cross_call_masked(func, ctx, data1, data2, &cpu_online_map)
815 void smp_call_function_client(int irq, struct pt_regs *regs)
817 clear_softint(1 << irq);
818 generic_smp_call_function_interrupt();
821 void smp_call_function_single_client(int irq, struct pt_regs *regs)
823 clear_softint(1 << irq);
824 generic_smp_call_function_single_interrupt();
827 static void tsb_sync(void *info)
829 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
830 struct mm_struct *mm = info;
832 /* It is not valid to test "currrent->active_mm == mm" here.
834 * The value of "current" is not changed atomically with
835 * switch_mm(). But that's OK, we just need to check the
836 * current cpu's trap block PGD physical address.
838 if (tp->pgd_paddr == __pa(mm->pgd))
839 tsb_context_switch(mm);
842 void smp_tsb_sync(struct mm_struct *mm)
844 smp_call_function_mask(mm->cpu_vm_mask, tsb_sync, mm, 1);
847 extern unsigned long xcall_flush_tlb_mm;
848 extern unsigned long xcall_flush_tlb_pending;
849 extern unsigned long xcall_flush_tlb_kernel_range;
850 #ifdef CONFIG_MAGIC_SYSRQ
851 extern unsigned long xcall_fetch_glob_regs;
853 extern unsigned long xcall_receive_signal;
854 extern unsigned long xcall_new_mmu_context_version;
856 extern unsigned long xcall_kgdb_capture;
859 #ifdef DCACHE_ALIASING_POSSIBLE
860 extern unsigned long xcall_flush_dcache_page_cheetah;
862 extern unsigned long xcall_flush_dcache_page_spitfire;
864 #ifdef CONFIG_DEBUG_DCFLUSH
865 extern atomic_t dcpage_flushes;
866 extern atomic_t dcpage_flushes_xcall;
869 static inline void __local_flush_dcache_page(struct page *page)
871 #ifdef DCACHE_ALIASING_POSSIBLE
872 __flush_dcache_page(page_address(page),
873 ((tlb_type == spitfire) &&
874 page_mapping(page) != NULL));
876 if (page_mapping(page) != NULL &&
877 tlb_type == spitfire)
878 __flush_icache_page(__pa(page_address(page)));
882 void smp_flush_dcache_page_impl(struct page *page, int cpu)
884 cpumask_t mask = cpumask_of_cpu(cpu);
887 if (tlb_type == hypervisor)
890 #ifdef CONFIG_DEBUG_DCFLUSH
891 atomic_inc(&dcpage_flushes);
894 this_cpu = get_cpu();
896 if (cpu == this_cpu) {
897 __local_flush_dcache_page(page);
898 } else if (cpu_online(cpu)) {
899 void *pg_addr = page_address(page);
902 if (tlb_type == spitfire) {
903 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
904 if (page_mapping(page) != NULL)
905 data0 |= ((u64)1 << 32);
906 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
907 #ifdef DCACHE_ALIASING_POSSIBLE
908 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
912 xcall_deliver(data0, __pa(pg_addr),
913 (u64) pg_addr, &mask);
914 #ifdef CONFIG_DEBUG_DCFLUSH
915 atomic_inc(&dcpage_flushes_xcall);
923 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
925 cpumask_t mask = cpu_online_map;
930 if (tlb_type == hypervisor)
933 this_cpu = get_cpu();
935 cpu_clear(this_cpu, mask);
937 #ifdef CONFIG_DEBUG_DCFLUSH
938 atomic_inc(&dcpage_flushes);
940 if (cpus_empty(mask))
943 pg_addr = page_address(page);
944 if (tlb_type == spitfire) {
945 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
946 if (page_mapping(page) != NULL)
947 data0 |= ((u64)1 << 32);
948 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
949 #ifdef DCACHE_ALIASING_POSSIBLE
950 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
954 xcall_deliver(data0, __pa(pg_addr),
955 (u64) pg_addr, &mask);
956 #ifdef CONFIG_DEBUG_DCFLUSH
957 atomic_inc(&dcpage_flushes_xcall);
961 __local_flush_dcache_page(page);
966 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
968 struct mm_struct *mm;
971 clear_softint(1 << irq);
973 /* See if we need to allocate a new TLB context because
974 * the version of the one we are using is now out of date.
976 mm = current->active_mm;
977 if (unlikely(!mm || (mm == &init_mm)))
980 spin_lock_irqsave(&mm->context.lock, flags);
982 if (unlikely(!CTX_VALID(mm->context)))
983 get_new_mmu_context(mm);
985 spin_unlock_irqrestore(&mm->context.lock, flags);
987 load_secondary_context(mm);
988 __flush_tlb_mm(CTX_HWBITS(mm->context),
992 void smp_new_mmu_context_version(void)
994 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
998 void kgdb_roundup_cpus(unsigned long flags)
1000 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1004 #ifdef CONFIG_MAGIC_SYSRQ
1005 void smp_fetch_global_regs(void)
1007 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1011 /* We know that the window frames of the user have been flushed
1012 * to the stack before we get here because all callers of us
1013 * are flush_tlb_*() routines, and these run after flush_cache_*()
1014 * which performs the flushw.
1016 * The SMP TLB coherency scheme we use works as follows:
1018 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1019 * space has (potentially) executed on, this is the heuristic
1020 * we use to avoid doing cross calls.
1022 * Also, for flushing from kswapd and also for clones, we
1023 * use cpu_vm_mask as the list of cpus to make run the TLB.
1025 * 2) TLB context numbers are shared globally across all processors
1026 * in the system, this allows us to play several games to avoid
1029 * One invariant is that when a cpu switches to a process, and
1030 * that processes tsk->active_mm->cpu_vm_mask does not have the
1031 * current cpu's bit set, that tlb context is flushed locally.
1033 * If the address space is non-shared (ie. mm->count == 1) we avoid
1034 * cross calls when we want to flush the currently running process's
1035 * tlb state. This is done by clearing all cpu bits except the current
1036 * processor's in current->active_mm->cpu_vm_mask and performing the
1037 * flush locally only. This will force any subsequent cpus which run
1038 * this task to flush the context from the local tlb if the process
1039 * migrates to another cpu (again).
1041 * 3) For shared address spaces (threads) and swapping we bite the
1042 * bullet for most cases and perform the cross call (but only to
1043 * the cpus listed in cpu_vm_mask).
1045 * The performance gain from "optimizing" away the cross call for threads is
1046 * questionable (in theory the big win for threads is the massive sharing of
1047 * address space state across processors).
1050 /* This currently is only used by the hugetlb arch pre-fault
1051 * hook on UltraSPARC-III+ and later when changing the pagesize
1052 * bits of the context register for an address space.
1054 void smp_flush_tlb_mm(struct mm_struct *mm)
1056 u32 ctx = CTX_HWBITS(mm->context);
1057 int cpu = get_cpu();
1059 if (atomic_read(&mm->mm_users) == 1) {
1060 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1061 goto local_flush_and_out;
1064 smp_cross_call_masked(&xcall_flush_tlb_mm,
1068 local_flush_and_out:
1069 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1074 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1076 u32 ctx = CTX_HWBITS(mm->context);
1077 int cpu = get_cpu();
1079 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1080 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1082 smp_cross_call_masked(&xcall_flush_tlb_pending,
1083 ctx, nr, (unsigned long) vaddrs,
1086 __flush_tlb_pending(ctx, nr, vaddrs);
1091 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1094 end = PAGE_ALIGN(end);
1096 smp_cross_call(&xcall_flush_tlb_kernel_range,
1099 __flush_tlb_kernel_range(start, end);
1104 /* #define CAPTURE_DEBUG */
1105 extern unsigned long xcall_capture;
1107 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1108 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1109 static unsigned long penguins_are_doing_time;
1111 void smp_capture(void)
1113 int result = atomic_add_ret(1, &smp_capture_depth);
1116 int ncpus = num_online_cpus();
1118 #ifdef CAPTURE_DEBUG
1119 printk("CPU[%d]: Sending penguins to jail...",
1120 smp_processor_id());
1122 penguins_are_doing_time = 1;
1123 membar_storestore_loadstore();
1124 atomic_inc(&smp_capture_registry);
1125 smp_cross_call(&xcall_capture, 0, 0, 0);
1126 while (atomic_read(&smp_capture_registry) != ncpus)
1128 #ifdef CAPTURE_DEBUG
1134 void smp_release(void)
1136 if (atomic_dec_and_test(&smp_capture_depth)) {
1137 #ifdef CAPTURE_DEBUG
1138 printk("CPU[%d]: Giving pardon to "
1139 "imprisoned penguins\n",
1140 smp_processor_id());
1142 penguins_are_doing_time = 0;
1143 membar_storeload_storestore();
1144 atomic_dec(&smp_capture_registry);
1148 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1149 * can service tlb flush xcalls...
1151 extern void prom_world(int);
1153 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1155 clear_softint(1 << irq);
1159 __asm__ __volatile__("flushw");
1161 atomic_inc(&smp_capture_registry);
1162 membar_storeload_storestore();
1163 while (penguins_are_doing_time)
1165 atomic_dec(&smp_capture_registry);
1171 /* /proc/profile writes can call this, don't __init it please. */
1172 int setup_profiling_timer(unsigned int multiplier)
1177 void __init smp_prepare_cpus(unsigned int max_cpus)
1181 void __devinit smp_prepare_boot_cpu(void)
1185 void __init smp_setup_processor_id(void)
1187 if (tlb_type == spitfire)
1188 xcall_deliver_impl = spitfire_xcall_deliver;
1189 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1190 xcall_deliver_impl = cheetah_xcall_deliver;
1192 xcall_deliver_impl = hypervisor_xcall_deliver;
1195 void __devinit smp_fill_in_sib_core_maps(void)
1199 for_each_present_cpu(i) {
1202 cpus_clear(cpu_core_map[i]);
1203 if (cpu_data(i).core_id == 0) {
1204 cpu_set(i, cpu_core_map[i]);
1208 for_each_present_cpu(j) {
1209 if (cpu_data(i).core_id ==
1210 cpu_data(j).core_id)
1211 cpu_set(j, cpu_core_map[i]);
1215 for_each_present_cpu(i) {
1218 cpus_clear(per_cpu(cpu_sibling_map, i));
1219 if (cpu_data(i).proc_id == -1) {
1220 cpu_set(i, per_cpu(cpu_sibling_map, i));
1224 for_each_present_cpu(j) {
1225 if (cpu_data(i).proc_id ==
1226 cpu_data(j).proc_id)
1227 cpu_set(j, per_cpu(cpu_sibling_map, i));
1232 int __cpuinit __cpu_up(unsigned int cpu)
1234 int ret = smp_boot_one_cpu(cpu);
1237 cpu_set(cpu, smp_commenced_mask);
1238 while (!cpu_isset(cpu, cpu_online_map))
1240 if (!cpu_isset(cpu, cpu_online_map)) {
1243 /* On SUN4V, writes to %tick and %stick are
1246 if (tlb_type != hypervisor)
1247 smp_synchronize_one_tick(cpu);
1253 #ifdef CONFIG_HOTPLUG_CPU
1254 void cpu_play_dead(void)
1256 int cpu = smp_processor_id();
1257 unsigned long pstate;
1261 if (tlb_type == hypervisor) {
1262 struct trap_per_cpu *tb = &trap_block[cpu];
1264 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1265 tb->cpu_mondo_pa, 0);
1266 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1267 tb->dev_mondo_pa, 0);
1268 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1269 tb->resum_mondo_pa, 0);
1270 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1271 tb->nonresum_mondo_pa, 0);
1274 cpu_clear(cpu, smp_commenced_mask);
1275 membar_safe("#Sync");
1277 local_irq_disable();
1279 __asm__ __volatile__(
1280 "rdpr %%pstate, %0\n\t"
1281 "wrpr %0, %1, %%pstate"
1289 int __cpu_disable(void)
1291 int cpu = smp_processor_id();
1295 for_each_cpu_mask(i, cpu_core_map[cpu])
1296 cpu_clear(cpu, cpu_core_map[i]);
1297 cpus_clear(cpu_core_map[cpu]);
1299 for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
1300 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
1301 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1308 spin_lock(&call_lock);
1309 cpu_clear(cpu, cpu_online_map);
1310 spin_unlock(&call_lock);
1314 /* Make sure no interrupts point to this cpu. */
1319 local_irq_disable();
1324 void __cpu_die(unsigned int cpu)
1328 for (i = 0; i < 100; i++) {
1330 if (!cpu_isset(cpu, smp_commenced_mask))
1334 if (cpu_isset(cpu, smp_commenced_mask)) {
1335 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1337 #if defined(CONFIG_SUN_LDOMS)
1338 unsigned long hv_err;
1342 hv_err = sun4v_cpu_stop(cpu);
1343 if (hv_err == HV_EOK) {
1344 cpu_clear(cpu, cpu_present_map);
1347 } while (--limit > 0);
1349 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1357 void __init smp_cpus_done(unsigned int max_cpus)
1361 void smp_send_reschedule(int cpu)
1363 xcall_deliver((u64) &xcall_receive_signal, 0, 0,
1364 &cpumask_of_cpu(cpu));
1367 void smp_receive_signal_client(int irq, struct pt_regs *regs)
1369 clear_softint(1 << irq);
1372 /* This is a nop because we capture all other cpus
1373 * anyways when making the PROM active.
1375 void smp_send_stop(void)
1379 unsigned long __per_cpu_base __read_mostly;
1380 unsigned long __per_cpu_shift __read_mostly;
1382 EXPORT_SYMBOL(__per_cpu_base);
1383 EXPORT_SYMBOL(__per_cpu_shift);
1385 void __init real_setup_per_cpu_areas(void)
1387 unsigned long paddr, goal, size, i;
1390 /* Copy section for each CPU (we discard the original) */
1391 goal = PERCPU_ENOUGH_ROOM;
1393 __per_cpu_shift = PAGE_SHIFT;
1394 for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1397 paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
1399 prom_printf("Cannot allocate per-cpu memory.\n");
1404 __per_cpu_base = ptr - __per_cpu_start;
1406 for (i = 0; i < NR_CPUS; i++, ptr += size)
1407 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1409 /* Setup %g5 for the boot cpu. */
1410 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());