1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
41 #include <asm/sections.h>
43 extern void calibrate_delay(void);
45 /* Please don't make this stuff initdata!!! --DaveM */
46 static unsigned char boot_cpu_id;
48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
50 static cpumask_t smp_commenced_mask;
51 static cpumask_t cpu_callout_map;
53 void smp_info(struct seq_file *m)
57 seq_printf(m, "State:\n");
58 for (i = 0; i < NR_CPUS; i++) {
61 "CPU%d:\t\tonline\n", i);
65 void smp_bogo(struct seq_file *m)
69 for (i = 0; i < NR_CPUS; i++)
72 "Cpu%dBogo\t: %lu.%02lu\n"
73 "Cpu%dClkTck\t: %016lx\n",
74 i, cpu_data(i).udelay_val / (500000/HZ),
75 (cpu_data(i).udelay_val / (5000/HZ)) % 100,
76 i, cpu_data(i).clock_tick);
79 void __init smp_store_cpu_info(int id)
83 /* multiplier and counter set by
84 smp_setup_percpu_timer() */
85 cpu_data(id).udelay_val = loops_per_jiffy;
87 cpu_find_by_mid(id, &cpu_node);
88 cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
89 "clock-frequency", 0);
91 cpu_data(id).idle_volume = 1;
93 cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
95 cpu_data(id).dcache_line_size =
96 prom_getintdefault(cpu_node, "dcache-line-size", 32);
97 cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
99 cpu_data(id).icache_line_size =
100 prom_getintdefault(cpu_node, "icache-line-size", 32);
101 cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
103 cpu_data(id).ecache_line_size =
104 prom_getintdefault(cpu_node, "ecache-line-size", 64);
105 printk("CPU[%d]: Caches "
106 "D[sz(%d):line_sz(%d)] "
107 "I[sz(%d):line_sz(%d)] "
108 "E[sz(%d):line_sz(%d)]\n",
110 cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
111 cpu_data(id).icache_size, cpu_data(id).icache_line_size,
112 cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
115 static void smp_setup_percpu_timer(void);
117 static volatile unsigned long callin_flag = 0;
119 void __init smp_callin(void)
121 int cpuid = hard_smp_processor_id();
123 __local_per_cpu_offset = __per_cpu_offset(cpuid);
127 smp_setup_percpu_timer();
129 if (cheetah_pcache_forced_on)
130 cheetah_enable_pcache();
135 smp_store_cpu_info(cpuid);
137 __asm__ __volatile__("membar #Sync\n\t"
138 "flush %%g6" : : : "memory");
140 /* Clear this or we will die instantly when we
141 * schedule back to this idler...
143 current_thread_info()->new_child = 0;
145 /* Attach to the address space of init_task. */
146 atomic_inc(&init_mm.mm_count);
147 current->active_mm = &init_mm;
149 while (!cpu_isset(cpuid, smp_commenced_mask))
152 cpu_set(cpuid, cpu_online_map);
154 /* idle thread is expected to have preempt disabled */
160 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
161 panic("SMP bolixed\n");
164 static unsigned long current_tick_offset __read_mostly;
166 /* This tick register synchronization scheme is taken entirely from
167 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
169 * The only change I've made is to rework it so that the master
170 * initiates the synchonization instead of the slave. -DaveM
174 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
176 #define NUM_ROUNDS 64 /* magic value */
177 #define NUM_ITERS 5 /* likewise */
179 static DEFINE_SPINLOCK(itc_sync_lock);
180 static unsigned long go[SLAVE + 1];
182 #define DEBUG_TICK_SYNC 0
184 static inline long get_delta (long *rt, long *master)
186 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
187 unsigned long tcenter, t0, t1, tm;
190 for (i = 0; i < NUM_ITERS; i++) {
191 t0 = tick_ops->get_tick();
194 while (!(tm = go[SLAVE]))
198 t1 = tick_ops->get_tick();
200 if (t1 - t0 < best_t1 - best_t0)
201 best_t0 = t0, best_t1 = t1, best_tm = tm;
204 *rt = best_t1 - best_t0;
205 *master = best_tm - best_t0;
207 /* average best_t0 and best_t1 without overflow: */
208 tcenter = (best_t0/2 + best_t1/2);
209 if (best_t0 % 2 + best_t1 % 2 == 2)
211 return tcenter - best_tm;
214 void smp_synchronize_tick_client(void)
216 long i, delta, adj, adjust_latency = 0, done = 0;
217 unsigned long flags, rt, master_time_stamp, bound;
220 long rt; /* roundtrip time */
221 long master; /* master's timestamp */
222 long diff; /* difference between midpoint and master's timestamp */
223 long lat; /* estimate of itc adjustment latency */
232 local_irq_save(flags);
234 for (i = 0; i < NUM_ROUNDS; i++) {
235 delta = get_delta(&rt, &master_time_stamp);
237 done = 1; /* let's lock on to this... */
243 adjust_latency += -delta;
244 adj = -delta + adjust_latency/4;
248 tick_ops->add_tick(adj, current_tick_offset);
252 t[i].master = master_time_stamp;
254 t[i].lat = adjust_latency/4;
258 local_irq_restore(flags);
261 for (i = 0; i < NUM_ROUNDS; i++)
262 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
263 t[i].rt, t[i].master, t[i].diff, t[i].lat);
266 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
267 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
270 static void smp_start_sync_tick_client(int cpu);
272 static void smp_synchronize_one_tick(int cpu)
274 unsigned long flags, i;
278 smp_start_sync_tick_client(cpu);
280 /* wait for client to be ready */
284 /* now let the client proceed into his loop */
288 spin_lock_irqsave(&itc_sync_lock, flags);
290 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
295 go[SLAVE] = tick_ops->get_tick();
299 spin_unlock_irqrestore(&itc_sync_lock, flags);
302 extern unsigned long sparc64_cpu_startup;
304 /* The OBP cpu startup callback truncates the 3rd arg cookie to
305 * 32-bits (I think) so to be safe we have it read the pointer
306 * contained here so we work on >4GB machines. -DaveM
308 static struct thread_info *cpu_new_thread = NULL;
310 static int __devinit smp_boot_one_cpu(unsigned int cpu)
312 unsigned long entry =
313 (unsigned long)(&sparc64_cpu_startup);
314 unsigned long cookie =
315 (unsigned long)(&cpu_new_thread);
316 struct task_struct *p;
317 int timeout, ret, cpu_node;
321 cpu_new_thread = task_thread_info(p);
322 cpu_set(cpu, cpu_callout_map);
324 cpu_find_by_mid(cpu, &cpu_node);
325 prom_startcpu(cpu_node, entry, cookie);
327 for (timeout = 0; timeout < 5000000; timeout++) {
335 printk("Processor %d is stuck.\n", cpu);
336 cpu_clear(cpu, cpu_callout_map);
339 cpu_new_thread = NULL;
344 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
349 if (this_is_starfire) {
350 /* map to real upaid */
351 cpu = (((cpu & 0x3c) << 1) |
352 ((cpu & 0x40) >> 4) |
356 target = (cpu << 14) | 0x70;
358 /* Ok, this is the real Spitfire Errata #54.
359 * One must read back from a UDB internal register
360 * after writes to the UDB interrupt dispatch, but
361 * before the membar Sync for that write.
362 * So we use the high UDB control register (ASI 0x7f,
363 * ADDR 0x20) for the dummy read. -DaveM
366 __asm__ __volatile__(
367 "wrpr %1, %2, %%pstate\n\t"
368 "stxa %4, [%0] %3\n\t"
369 "stxa %5, [%0+%8] %3\n\t"
371 "stxa %6, [%0+%8] %3\n\t"
373 "stxa %%g0, [%7] %3\n\t"
376 "ldxa [%%g1] 0x7f, %%g0\n\t"
379 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
380 "r" (data0), "r" (data1), "r" (data2), "r" (target),
381 "r" (0x10), "0" (tmp)
384 /* NOTE: PSTATE_IE is still clear. */
387 __asm__ __volatile__("ldxa [%%g0] %1, %0"
389 : "i" (ASI_INTR_DISPATCH_STAT));
391 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
398 } while (result & 0x1);
399 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
402 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
403 smp_processor_id(), result);
410 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
415 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
416 for_each_cpu_mask(i, mask)
417 spitfire_xcall_helper(data0, data1, data2, pstate, i);
420 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
421 * packet, but we have no use for that. However we do take advantage of
422 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
424 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
427 int nack_busy_id, is_jbus;
429 if (cpus_empty(mask))
432 /* Unfortunately, someone at Sun had the brilliant idea to make the
433 * busy/nack fields hard-coded by ITID number for this Ultra-III
434 * derivative processor.
436 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
437 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
438 (ver >> 32) == __SERRANO_ID);
440 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
443 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
444 : : "r" (pstate), "i" (PSTATE_IE));
446 /* Setup the dispatch data registers. */
447 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
448 "stxa %1, [%4] %6\n\t"
449 "stxa %2, [%5] %6\n\t"
452 : "r" (data0), "r" (data1), "r" (data2),
453 "r" (0x40), "r" (0x50), "r" (0x60),
460 for_each_cpu_mask(i, mask) {
461 u64 target = (i << 14) | 0x70;
464 target |= (nack_busy_id << 24);
465 __asm__ __volatile__(
466 "stxa %%g0, [%0] %1\n\t"
469 : "r" (target), "i" (ASI_INTR_W));
474 /* Now, poll for completion. */
479 stuck = 100000 * nack_busy_id;
481 __asm__ __volatile__("ldxa [%%g0] %1, %0"
482 : "=r" (dispatch_stat)
483 : "i" (ASI_INTR_DISPATCH_STAT));
484 if (dispatch_stat == 0UL) {
485 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
491 } while (dispatch_stat & 0x5555555555555555UL);
493 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
496 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
497 /* Busy bits will not clear, continue instead
498 * of freezing up on this cpu.
500 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
501 smp_processor_id(), dispatch_stat);
503 int i, this_busy_nack = 0;
505 /* Delay some random time with interrupts enabled
506 * to prevent deadlock.
508 udelay(2 * nack_busy_id);
510 /* Clear out the mask bits for cpus which did not
513 for_each_cpu_mask(i, mask) {
517 check_mask = (0x2UL << (2*i));
519 check_mask = (0x2UL <<
521 if ((dispatch_stat & check_mask) == 0)
531 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
533 /* XXX implement me */
536 /* Send cross call to all processors mentioned in MASK
539 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
541 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
542 int this_cpu = get_cpu();
544 cpus_and(mask, mask, cpu_online_map);
545 cpu_clear(this_cpu, mask);
547 if (tlb_type == spitfire)
548 spitfire_xcall_deliver(data0, data1, data2, mask);
549 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
550 cheetah_xcall_deliver(data0, data1, data2, mask);
552 hypervisor_xcall_deliver(data0, data1, data2, mask);
553 /* NOTE: Caller runs local copy on master. */
558 extern unsigned long xcall_sync_tick;
560 static void smp_start_sync_tick_client(int cpu)
562 cpumask_t mask = cpumask_of_cpu(cpu);
564 smp_cross_call_masked(&xcall_sync_tick,
568 /* Send cross call to all processors except self. */
569 #define smp_cross_call(func, ctx, data1, data2) \
570 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
572 struct call_data_struct {
573 void (*func) (void *info);
579 static DEFINE_SPINLOCK(call_lock);
580 static struct call_data_struct *call_data;
582 extern unsigned long xcall_call_function;
585 * You must not call this function with disabled interrupts or from a
586 * hardware interrupt handler or from a bottom half handler.
588 static int smp_call_function_mask(void (*func)(void *info), void *info,
589 int nonatomic, int wait, cpumask_t mask)
591 struct call_data_struct data;
592 int cpus = cpus_weight(mask) - 1;
598 /* Can deadlock when called with interrupts disabled */
599 WARN_ON(irqs_disabled());
603 atomic_set(&data.finished, 0);
606 spin_lock(&call_lock);
610 smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
613 * Wait for other cpus to complete function or at
614 * least snap the call data.
617 while (atomic_read(&data.finished) != cpus) {
624 spin_unlock(&call_lock);
629 spin_unlock(&call_lock);
630 printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
631 (long) num_online_cpus() - 1L,
632 (long) atomic_read(&data.finished));
636 int smp_call_function(void (*func)(void *info), void *info,
637 int nonatomic, int wait)
639 return smp_call_function_mask(func, info, nonatomic, wait,
643 void smp_call_function_client(int irq, struct pt_regs *regs)
645 void (*func) (void *info) = call_data->func;
646 void *info = call_data->info;
648 clear_softint(1 << irq);
649 if (call_data->wait) {
650 /* let initiator proceed only after completion */
652 atomic_inc(&call_data->finished);
654 /* let initiator proceed after getting data */
655 atomic_inc(&call_data->finished);
660 static void tsb_sync(void *info)
662 struct mm_struct *mm = info;
664 if (current->active_mm == mm)
665 tsb_context_switch(mm);
668 void smp_tsb_sync(struct mm_struct *mm)
670 smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
673 extern unsigned long xcall_flush_tlb_mm;
674 extern unsigned long xcall_flush_tlb_pending;
675 extern unsigned long xcall_flush_tlb_kernel_range;
676 extern unsigned long xcall_report_regs;
677 extern unsigned long xcall_receive_signal;
679 #ifdef DCACHE_ALIASING_POSSIBLE
680 extern unsigned long xcall_flush_dcache_page_cheetah;
682 extern unsigned long xcall_flush_dcache_page_spitfire;
684 #ifdef CONFIG_DEBUG_DCFLUSH
685 extern atomic_t dcpage_flushes;
686 extern atomic_t dcpage_flushes_xcall;
689 static __inline__ void __local_flush_dcache_page(struct page *page)
691 #ifdef DCACHE_ALIASING_POSSIBLE
692 __flush_dcache_page(page_address(page),
693 ((tlb_type == spitfire) &&
694 page_mapping(page) != NULL));
696 if (page_mapping(page) != NULL &&
697 tlb_type == spitfire)
698 __flush_icache_page(__pa(page_address(page)));
702 void smp_flush_dcache_page_impl(struct page *page, int cpu)
704 cpumask_t mask = cpumask_of_cpu(cpu);
707 if (tlb_type == hypervisor)
710 #ifdef CONFIG_DEBUG_DCFLUSH
711 atomic_inc(&dcpage_flushes);
714 this_cpu = get_cpu();
716 if (cpu == this_cpu) {
717 __local_flush_dcache_page(page);
718 } else if (cpu_online(cpu)) {
719 void *pg_addr = page_address(page);
722 if (tlb_type == spitfire) {
724 ((u64)&xcall_flush_dcache_page_spitfire);
725 if (page_mapping(page) != NULL)
726 data0 |= ((u64)1 << 32);
727 spitfire_xcall_deliver(data0,
731 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
732 #ifdef DCACHE_ALIASING_POSSIBLE
734 ((u64)&xcall_flush_dcache_page_cheetah);
735 cheetah_xcall_deliver(data0,
740 #ifdef CONFIG_DEBUG_DCFLUSH
741 atomic_inc(&dcpage_flushes_xcall);
748 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
750 void *pg_addr = page_address(page);
751 cpumask_t mask = cpu_online_map;
755 if (tlb_type == hypervisor)
758 this_cpu = get_cpu();
760 cpu_clear(this_cpu, mask);
762 #ifdef CONFIG_DEBUG_DCFLUSH
763 atomic_inc(&dcpage_flushes);
765 if (cpus_empty(mask))
767 if (tlb_type == spitfire) {
768 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
769 if (page_mapping(page) != NULL)
770 data0 |= ((u64)1 << 32);
771 spitfire_xcall_deliver(data0,
775 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
776 #ifdef DCACHE_ALIASING_POSSIBLE
777 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
778 cheetah_xcall_deliver(data0,
783 #ifdef CONFIG_DEBUG_DCFLUSH
784 atomic_inc(&dcpage_flushes_xcall);
787 __local_flush_dcache_page(page);
792 void smp_receive_signal(int cpu)
794 cpumask_t mask = cpumask_of_cpu(cpu);
796 if (cpu_online(cpu)) {
797 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
799 if (tlb_type == spitfire)
800 spitfire_xcall_deliver(data0, 0, 0, mask);
801 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
802 cheetah_xcall_deliver(data0, 0, 0, mask);
803 else if (tlb_type == hypervisor)
804 hypervisor_xcall_deliver(data0, 0, 0, mask);
808 void smp_receive_signal_client(int irq, struct pt_regs *regs)
810 /* Just return, rtrap takes care of the rest. */
811 clear_softint(1 << irq);
814 void smp_report_regs(void)
816 smp_cross_call(&xcall_report_regs, 0, 0, 0);
819 /* We know that the window frames of the user have been flushed
820 * to the stack before we get here because all callers of us
821 * are flush_tlb_*() routines, and these run after flush_cache_*()
822 * which performs the flushw.
824 * The SMP TLB coherency scheme we use works as follows:
826 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
827 * space has (potentially) executed on, this is the heuristic
828 * we use to avoid doing cross calls.
830 * Also, for flushing from kswapd and also for clones, we
831 * use cpu_vm_mask as the list of cpus to make run the TLB.
833 * 2) TLB context numbers are shared globally across all processors
834 * in the system, this allows us to play several games to avoid
837 * One invariant is that when a cpu switches to a process, and
838 * that processes tsk->active_mm->cpu_vm_mask does not have the
839 * current cpu's bit set, that tlb context is flushed locally.
841 * If the address space is non-shared (ie. mm->count == 1) we avoid
842 * cross calls when we want to flush the currently running process's
843 * tlb state. This is done by clearing all cpu bits except the current
844 * processor's in current->active_mm->cpu_vm_mask and performing the
845 * flush locally only. This will force any subsequent cpus which run
846 * this task to flush the context from the local tlb if the process
847 * migrates to another cpu (again).
849 * 3) For shared address spaces (threads) and swapping we bite the
850 * bullet for most cases and perform the cross call (but only to
851 * the cpus listed in cpu_vm_mask).
853 * The performance gain from "optimizing" away the cross call for threads is
854 * questionable (in theory the big win for threads is the massive sharing of
855 * address space state across processors).
858 /* This currently is only used by the hugetlb arch pre-fault
859 * hook on UltraSPARC-III+ and later when changing the pagesize
860 * bits of the context register for an address space.
862 void smp_flush_tlb_mm(struct mm_struct *mm)
864 u32 ctx = CTX_HWBITS(mm->context);
867 if (atomic_read(&mm->mm_users) == 1) {
868 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
869 goto local_flush_and_out;
872 smp_cross_call_masked(&xcall_flush_tlb_mm,
877 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
882 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
884 u32 ctx = CTX_HWBITS(mm->context);
887 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
888 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
890 smp_cross_call_masked(&xcall_flush_tlb_pending,
891 ctx, nr, (unsigned long) vaddrs,
894 __flush_tlb_pending(ctx, nr, vaddrs);
899 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
902 end = PAGE_ALIGN(end);
904 smp_cross_call(&xcall_flush_tlb_kernel_range,
907 __flush_tlb_kernel_range(start, end);
912 /* #define CAPTURE_DEBUG */
913 extern unsigned long xcall_capture;
915 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
916 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
917 static unsigned long penguins_are_doing_time;
919 void smp_capture(void)
921 int result = atomic_add_ret(1, &smp_capture_depth);
924 int ncpus = num_online_cpus();
927 printk("CPU[%d]: Sending penguins to jail...",
930 penguins_are_doing_time = 1;
931 membar_storestore_loadstore();
932 atomic_inc(&smp_capture_registry);
933 smp_cross_call(&xcall_capture, 0, 0, 0);
934 while (atomic_read(&smp_capture_registry) != ncpus)
942 void smp_release(void)
944 if (atomic_dec_and_test(&smp_capture_depth)) {
946 printk("CPU[%d]: Giving pardon to "
947 "imprisoned penguins\n",
950 penguins_are_doing_time = 0;
951 membar_storeload_storestore();
952 atomic_dec(&smp_capture_registry);
956 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
957 * can service tlb flush xcalls...
959 extern void prom_world(int);
961 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
963 clear_softint(1 << irq);
967 __asm__ __volatile__("flushw");
969 atomic_inc(&smp_capture_registry);
970 membar_storeload_storestore();
971 while (penguins_are_doing_time)
973 atomic_dec(&smp_capture_registry);
979 #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
980 #define prof_counter(__cpu) cpu_data(__cpu).counter
982 void smp_percpu_timer_interrupt(struct pt_regs *regs)
984 unsigned long compare, tick, pstate;
985 int cpu = smp_processor_id();
986 int user = user_mode(regs);
989 * Check for level 14 softint.
992 unsigned long tick_mask = tick_ops->softint_mask;
994 if (!(get_softint() & tick_mask)) {
995 extern void handler_irq(int, struct pt_regs *);
997 handler_irq(14, regs);
1000 clear_softint(tick_mask);
1004 profile_tick(CPU_PROFILING, regs);
1005 if (!--prof_counter(cpu)) {
1008 if (cpu == boot_cpu_id) {
1009 kstat_this_cpu.irqs[0]++;
1010 timer_tick_interrupt(regs);
1013 update_process_times(user);
1017 prof_counter(cpu) = prof_multiplier(cpu);
1020 /* Guarantee that the following sequences execute
1023 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1024 "wrpr %0, %1, %%pstate"
1028 compare = tick_ops->add_compare(current_tick_offset);
1029 tick = tick_ops->get_tick();
1031 /* Restore PSTATE_IE. */
1032 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1035 } while (time_after_eq(tick, compare));
1038 static void __init smp_setup_percpu_timer(void)
1040 int cpu = smp_processor_id();
1041 unsigned long pstate;
1043 prof_counter(cpu) = prof_multiplier(cpu) = 1;
1045 /* Guarantee that the following sequences execute
1048 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1049 "wrpr %0, %1, %%pstate"
1053 tick_ops->init_tick(current_tick_offset);
1055 /* Restore PSTATE_IE. */
1056 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1061 void __init smp_tick_init(void)
1063 boot_cpu_id = hard_smp_processor_id();
1064 current_tick_offset = timer_tick_offset;
1066 cpu_set(boot_cpu_id, cpu_online_map);
1067 prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1070 /* /proc/profile writes can call this, don't __init it please. */
1071 static DEFINE_SPINLOCK(prof_setup_lock);
1073 int setup_profiling_timer(unsigned int multiplier)
1075 unsigned long flags;
1078 if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1081 spin_lock_irqsave(&prof_setup_lock, flags);
1082 for (i = 0; i < NR_CPUS; i++)
1083 prof_multiplier(i) = multiplier;
1084 current_tick_offset = (timer_tick_offset / multiplier);
1085 spin_unlock_irqrestore(&prof_setup_lock, flags);
1090 /* Constrain the number of cpus to max_cpus. */
1091 void __init smp_prepare_cpus(unsigned int max_cpus)
1093 if (num_possible_cpus() > max_cpus) {
1097 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1098 if (mid != boot_cpu_id) {
1099 cpu_clear(mid, phys_cpu_present_map);
1100 if (num_possible_cpus() <= max_cpus)
1107 smp_store_cpu_info(boot_cpu_id);
1110 /* Set this up early so that things like the scheduler can init
1111 * properly. We use the same cpu mask for both the present and
1114 void __init smp_setup_cpu_possible_map(void)
1119 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1121 cpu_set(mid, phys_cpu_present_map);
1126 void __devinit smp_prepare_boot_cpu(void)
1128 int cpu = hard_smp_processor_id();
1130 if (cpu >= NR_CPUS) {
1131 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1135 current_thread_info()->cpu = cpu;
1136 __local_per_cpu_offset = __per_cpu_offset(cpu);
1138 cpu_set(smp_processor_id(), cpu_online_map);
1139 cpu_set(smp_processor_id(), phys_cpu_present_map);
1142 int __devinit __cpu_up(unsigned int cpu)
1144 int ret = smp_boot_one_cpu(cpu);
1147 cpu_set(cpu, smp_commenced_mask);
1148 while (!cpu_isset(cpu, cpu_online_map))
1150 if (!cpu_isset(cpu, cpu_online_map)) {
1153 smp_synchronize_one_tick(cpu);
1159 void __init smp_cpus_done(unsigned int max_cpus)
1161 unsigned long bogosum = 0;
1164 for (i = 0; i < NR_CPUS; i++) {
1166 bogosum += cpu_data(i).udelay_val;
1168 printk("Total of %ld processors activated "
1169 "(%lu.%02lu BogoMIPS).\n",
1170 (long) num_online_cpus(),
1171 bogosum/(500000/HZ),
1172 (bogosum/(5000/HZ))%100);
1175 void smp_send_reschedule(int cpu)
1177 smp_receive_signal(cpu);
1180 /* This is a nop because we capture all other cpus
1181 * anyways when making the PROM active.
1183 void smp_send_stop(void)
1187 unsigned long __per_cpu_base __read_mostly;
1188 unsigned long __per_cpu_shift __read_mostly;
1190 EXPORT_SYMBOL(__per_cpu_base);
1191 EXPORT_SYMBOL(__per_cpu_shift);
1193 void __init setup_per_cpu_areas(void)
1195 unsigned long goal, size, i;
1198 /* Copy section for each CPU (we discard the original) */
1199 goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1200 #ifdef CONFIG_MODULES
1201 if (goal < PERCPU_ENOUGH_ROOM)
1202 goal = PERCPU_ENOUGH_ROOM;
1204 __per_cpu_shift = 0;
1205 for (size = 1UL; size < goal; size <<= 1UL)
1208 ptr = alloc_bootmem(size * NR_CPUS);
1210 __per_cpu_base = ptr - __per_cpu_start;
1212 for (i = 0; i < NR_CPUS; i++, ptr += size)
1213 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);