err.no Git - linux-2.6/blob - arch/sparc64/kernel/pci_sun4v.c

   1 /* pci_sun4v.c: SUN4V specific PCI controller support.
   2  *
   3  * Copyright (C) 2006 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/interrupt.h>
  12
  13 #include <asm/pbm.h>
  14 #include <asm/iommu.h>
  15 #include <asm/irq.h>
  16 #include <asm/upa.h>
  17 #include <asm/pstate.h>
  18 #include <asm/oplib.h>
  19 #include <asm/hypervisor.h>
  20
  21 #include "pci_impl.h"
  22 #include "iommu_common.h"
  23
  24 #include "pci_sun4v.h"
  25
  26 static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
  27 {
  28         return NULL;
  29 }
  30
  31 static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
  32 {
  33 }
  34
  35 static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
  36 {
  37         return 0;
  38 }
  39
  40 static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
  41 {
  42 }
  43
  44 static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
  45 {
  46         return nelems;
  47 }
  48
  49 static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
  50 {
  51 }
  52
  53 static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
  54 {
  55 }
  56
  57 static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
  58 {
  59 }
  60
  61 struct pci_iommu_ops pci_sun4v_iommu_ops = {
  62         .alloc_consistent               = pci_4v_alloc_consistent,
  63         .free_consistent                = pci_4v_free_consistent,
  64         .map_single                     = pci_4v_map_single,
  65         .unmap_single                   = pci_4v_unmap_single,
  66         .map_sg                         = pci_4v_map_sg,
  67         .unmap_sg                       = pci_4v_unmap_sg,
  68         .dma_sync_single_for_cpu        = pci_4v_dma_sync_single_for_cpu,
  69         .dma_sync_sg_for_cpu            = pci_4v_dma_sync_sg_for_cpu,
  70 };
  71
  72 /* SUN4V PCI configuration space accessors. */
  73
  74 static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
  75                                   int where, int size, u32 *value)
  76 {
  77         struct pci_pbm_info *pbm = bus_dev->sysdata;
  78         unsigned long devhandle = pbm->devhandle;
  79         unsigned int bus = bus_dev->number;
  80         unsigned int device = PCI_SLOT(devfn);
  81         unsigned int func = PCI_FUNC(devfn);
  82         unsigned long ret;
  83
  84         ret = pci_sun4v_config_get(devhandle,
  85                                    HV_PCI_DEVICE_BUILD(bus, device, func),
  86                                    where, size);
  87         switch (size) {
  88         case 1:
  89                 *value = ret & 0xff;
  90                 break;
  91         case 2:
  92                 *value = ret & 0xffff;
  93                 break;
  94         case 4:
  95                 *value = ret & 0xffffffff;
  96                 break;
  97         };
  98
  99
 100         return PCIBIOS_SUCCESSFUL;
 101 }
 102
 103 static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 104                                    int where, int size, u32 value)
 105 {
 106         struct pci_pbm_info *pbm = bus_dev->sysdata;
 107         unsigned long devhandle = pbm->devhandle;
 108         unsigned int bus = bus_dev->number;
 109         unsigned int device = PCI_SLOT(devfn);
 110         unsigned int func = PCI_FUNC(devfn);
 111         unsigned long ret;
 112
 113         ret = pci_sun4v_config_put(devhandle,
 114                                    HV_PCI_DEVICE_BUILD(bus, device, func),
 115                                    where, size, value);
 116
 117         return PCIBIOS_SUCCESSFUL;
 118 }
 119
 120 static struct pci_ops pci_sun4v_ops = {
 121         .read =         pci_sun4v_read_pci_cfg,
 122         .write =        pci_sun4v_write_pci_cfg,
 123 };
 124
 125
 126 static void pci_sun4v_scan_bus(struct pci_controller_info *p)
 127 {
 128         /* XXX Implement me! XXX */
 129 }
 130
 131 static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
 132                                         struct pci_dev *pdev,
 133                                         unsigned int ino)
 134 {
 135         /* XXX Implement me! XXX */
 136         return 0;
 137 }
 138
 139 /* XXX correct? XXX */
 140 static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
 141 {
 142         struct pcidev_cookie *pcp = pdev->sysdata;
 143         struct pci_pbm_info *pbm = pcp->pbm;
 144         struct resource *res, *root;
 145         u32 reg;
 146         int where, size, is_64bit;
 147
 148         res = &pdev->resource[resource];
 149         if (resource < 6) {
 150                 where = PCI_BASE_ADDRESS_0 + (resource * 4);
 151         } else if (resource == PCI_ROM_RESOURCE) {
 152                 where = pdev->rom_base_reg;
 153         } else {
 154                 /* Somebody might have asked allocation of a non-standard resource */
 155                 return;
 156         }
 157
 158         is_64bit = 0;
 159         if (res->flags & IORESOURCE_IO)
 160                 root = &pbm->io_space;
 161         else {
 162                 root = &pbm->mem_space;
 163                 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
 164                     == PCI_BASE_ADDRESS_MEM_TYPE_64)
 165                         is_64bit = 1;
 166         }
 167
 168         size = res->end - res->start;
 169         pci_read_config_dword(pdev, where, &reg);
 170         reg = ((reg & size) |
 171                (((u32)(res->start - root->start)) & ~size));
 172         if (resource == PCI_ROM_RESOURCE) {
 173                 reg |= PCI_ROM_ADDRESS_ENABLE;
 174                 res->flags |= IORESOURCE_ROM_ENABLE;
 175         }
 176         pci_write_config_dword(pdev, where, reg);
 177
 178         /* This knows that the upper 32-bits of the address
 179          * must be zero.  Our PCI common layer enforces this.
 180          */
 181         if (is_64bit)
 182                 pci_write_config_dword(pdev, where + 4, 0);
 183 }
 184
 185 /* XXX correct? XXX */
 186 static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
 187                                       struct resource *res,
 188                                       struct resource *root)
 189 {
 190         res->start += root->start;
 191         res->end += root->start;
 192 }
 193
 194 /* Use ranges property to determine where PCI MEM, I/O, and Config
 195  * space are for this PCI bus module.
 196  */
 197 static void pci_sun4v_determine_mem_io_space(struct pci_pbm_info *pbm)
 198 {
 199         int i, saw_cfg, saw_mem, saw_io;
 200
 201         saw_cfg = saw_mem = saw_io = 0;
 202         for (i = 0; i < pbm->num_pbm_ranges; i++) {
 203                 struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
 204                 unsigned long a;
 205                 int type;
 206
 207                 type = (pr->child_phys_hi >> 24) & 0x3;
 208                 a = (((unsigned long)pr->parent_phys_hi << 32UL) |
 209                      ((unsigned long)pr->parent_phys_lo  <<  0UL));
 210
 211                 switch (type) {
 212                 case 0:
 213                         /* PCI config space, 16MB */
 214                         pbm->config_space = a;
 215                         saw_cfg = 1;
 216                         break;
 217
 218                 case 1:
 219                         /* 16-bit IO space, 16MB */
 220                         pbm->io_space.start = a;
 221                         pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
 222                         pbm->io_space.flags = IORESOURCE_IO;
 223                         saw_io = 1;
 224                         break;
 225
 226                 case 2:
 227                         /* 32-bit MEM space, 2GB */
 228                         pbm->mem_space.start = a;
 229                         pbm->mem_space.end = a + (0x80000000UL - 1UL);
 230                         pbm->mem_space.flags = IORESOURCE_MEM;
 231                         saw_mem = 1;
 232                         break;
 233
 234                 default:
 235                         break;
 236                 };
 237         }
 238
 239         if (!saw_cfg || !saw_io || !saw_mem) {
 240                 prom_printf("%s: Fatal error, missing %s PBM range.\n",
 241                             pbm->name,
 242                             ((!saw_cfg ?
 243                               "CFG" :
 244                               (!saw_io ?
 245                                "IO" : "MEM"))));
 246                 prom_halt();
 247         }
 248
 249         printk("%s: PCI CFG[%lx] IO[%lx] MEM[%lx]\n",
 250                pbm->name,
 251                pbm->config_space,
 252                pbm->io_space.start,
 253                pbm->mem_space.start);
 254 }
 255
 256 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
 257                                             struct pci_pbm_info *pbm)
 258 {
 259         pbm->io_space.name = pbm->mem_space.name = pbm->name;
 260
 261         request_resource(&ioport_resource, &pbm->io_space);
 262         request_resource(&iomem_resource, &pbm->mem_space);
 263         pci_register_legacy_regions(&pbm->io_space,
 264                                     &pbm->mem_space);
 265 }
 266
 267 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
 268 {
 269         /* XXX Implement me! XXX */
 270 }
 271
 272 static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node)
 273 {
 274         struct pci_pbm_info *pbm;
 275         struct linux_prom64_registers regs;
 276         unsigned int busrange[2];
 277         int err;
 278
 279         /* XXX */
 280         pbm = &p->pbm_A;
 281
 282         pbm->parent = p;
 283         pbm->prom_node = prom_node;
 284         pbm->pci_first_slot = 1;
 285
 286         prom_getproperty(prom_node, "reg", (char *)&regs, sizeof(regs));
 287         pbm->devhandle = (regs.phys_addr >> 32UL) & 0x0fffffff;
 288
 289         sprintf(pbm->name, "SUN4V-PCI%d PBM%c",
 290                 p->index, (pbm == &p->pbm_A ? 'A' : 'B'));
 291
 292         printk("%s: devhandle[%x]\n", pbm->name, pbm->devhandle);
 293
 294         prom_getstring(prom_node, "name",
 295                        pbm->prom_name, sizeof(pbm->prom_name));
 296
 297         err = prom_getproperty(prom_node, "ranges",
 298                                (char *) pbm->pbm_ranges,
 299                                sizeof(pbm->pbm_ranges));
 300         if (err == 0 || err == -1) {
 301                 prom_printf("%s: Fatal error, no ranges property.\n",
 302                             pbm->name);
 303                 prom_halt();
 304         }
 305
 306         pbm->num_pbm_ranges =
 307                 (err / sizeof(struct linux_prom_pci_ranges));
 308
 309         pci_sun4v_determine_mem_io_space(pbm);
 310         pbm_register_toplevel_resources(p, pbm);
 311
 312         err = prom_getproperty(prom_node, "interrupt-map",
 313                                (char *)pbm->pbm_intmap,
 314                                sizeof(pbm->pbm_intmap));
 315         if (err != -1) {
 316                 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
 317                 err = prom_getproperty(prom_node, "interrupt-map-mask",
 318                                        (char *)&pbm->pbm_intmask,
 319                                        sizeof(pbm->pbm_intmask));
 320                 if (err == -1) {
 321                         prom_printf("%s: Fatal error, no "
 322                                     "interrupt-map-mask.\n", pbm->name);
 323                         prom_halt();
 324                 }
 325         } else {
 326                 pbm->num_pbm_intmap = 0;
 327                 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
 328         }
 329
 330         err = prom_getproperty(prom_node, "bus-range",
 331                                (char *)&busrange[0],
 332                                sizeof(busrange));
 333         if (err == 0 || err == -1) {
 334                 prom_printf("%s: Fatal error, no bus-range.\n", pbm->name);
 335                 prom_halt();
 336         }
 337         pbm->pci_first_busno = busrange[0];
 338         pbm->pci_last_busno = busrange[1];
 339
 340         pci_sun4v_iommu_init(pbm);
 341 }
 342
 343 void sun4v_pci_init(int node, char *model_name)
 344 {
 345         struct pci_controller_info *p;
 346         struct pci_iommu *iommu;
 347
 348         p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
 349         if (!p) {
 350                 prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
 351                 prom_halt();
 352         }
 353         memset(p, 0, sizeof(*p));
 354
 355         iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
 356         if (!iommu) {
 357                 prom_printf("SCHIZO: Fatal memory allocation error.\n");
 358                 prom_halt();
 359         }
 360         memset(iommu, 0, sizeof(*iommu));
 361         p->pbm_A.iommu = iommu;
 362
 363         iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
 364         if (!iommu) {
 365                 prom_printf("SCHIZO: Fatal memory allocation error.\n");
 366                 prom_halt();
 367         }
 368         memset(iommu, 0, sizeof(*iommu));
 369         p->pbm_B.iommu = iommu;
 370
 371         p->next = pci_controller_root;
 372         pci_controller_root = p;
 373
 374         p->index = pci_num_controllers++;
 375         p->pbms_same_domain = 0;
 376
 377         p->scan_bus = pci_sun4v_scan_bus;
 378         p->irq_build = pci_sun4v_irq_build;
 379         p->base_address_update = pci_sun4v_base_address_update;
 380         p->resource_adjust = pci_sun4v_resource_adjust;
 381         p->pci_ops = &pci_sun4v_ops;
 382
 383         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
 384          * for memory space.
 385          */
 386         pci_memspace_mask = 0x7fffffffUL;
 387
 388         pci_sun4v_pbm_init(p, node);
 389
 390         prom_printf("sun4v_pci_init: Implement me.\n");
 391         prom_halt();
 392 }