1 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
3 * Copyright (C) 2001, 2002, 2003, 2007 David S. Miller (davem@davemloft.net)
6 #include <linux/kernel.h>
7 #include <linux/types.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
14 #include <asm/iommu.h>
17 #include <asm/pstate.h>
21 #include "iommu_common.h"
23 /* All SCHIZO registers are 64-bits. The following accessor
24 * routines are how they are accessed. The REG parameter
25 * is a physical address.
27 #define schizo_read(__reg) \
29 __asm__ __volatile__("ldxa [%1] %2, %0" \
31 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
35 #define schizo_write(__reg, __val) \
36 __asm__ __volatile__("stxa %0, [%1] %2" \
38 : "r" (__val), "r" (__reg), \
39 "i" (ASI_PHYS_BYPASS_EC_E) \
42 /* This is a convention that at least Excalibur and Merlin
43 * follow. I suppose the SCHIZO used in Starcat and friends
46 * The only way I could see this changing is if the newlink
47 * block requires more space in Schizo's address space than
48 * they predicted, thus requiring an address space reorg when
49 * the newer Schizo is taped out.
52 /* Streaming buffer control register. */
53 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
54 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
55 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
56 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
57 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
59 /* IOMMU control register. */
60 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
61 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
62 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
63 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
64 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
65 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
66 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
67 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
68 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
69 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
70 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
71 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
72 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
73 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
74 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
75 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
76 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
77 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
79 /* Schizo config space address format is nearly identical to
82 * 32 24 23 16 15 11 10 8 7 2 1 0
83 * ---------------------------------------------------------
84 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
85 * ---------------------------------------------------------
87 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
88 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
89 (((unsigned long)(BUS) << 16) | \
90 ((unsigned long)(DEVFN) << 8) | \
91 ((unsigned long)(REG)))
93 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
100 bus -= pbm->pci_first_busno;
102 (SCHIZO_CONFIG_BASE(pbm) |
103 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
106 /* Just make sure the bus number is in range. */
107 static int schizo_out_of_range(struct pci_pbm_info *pbm,
111 if (bus < pbm->pci_first_busno ||
112 bus > pbm->pci_last_busno)
117 /* SCHIZO PCI configuration space accessors. */
119 static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
120 int where, int size, u32 *value)
122 struct pci_pbm_info *pbm = bus_dev->sysdata;
123 unsigned char bus = bus_dev->number;
128 if (bus_dev == pbm->pci_bus && devfn == 0x00)
129 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
143 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
145 return PCIBIOS_SUCCESSFUL;
147 if (schizo_out_of_range(pbm, bus, devfn))
148 return PCIBIOS_SUCCESSFUL;
151 pci_config_read8((u8 *)addr, &tmp8);
157 printk("pci_read_config_word: misaligned reg [%x]\n",
159 return PCIBIOS_SUCCESSFUL;
161 pci_config_read16((u16 *)addr, &tmp16);
167 printk("pci_read_config_dword: misaligned reg [%x]\n",
169 return PCIBIOS_SUCCESSFUL;
171 pci_config_read32(addr, value);
174 return PCIBIOS_SUCCESSFUL;
177 static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
178 int where, int size, u32 value)
180 struct pci_pbm_info *pbm = bus_dev->sysdata;
181 unsigned char bus = bus_dev->number;
184 if (bus_dev == pbm->pci_bus && devfn == 0x00)
185 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
187 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
189 return PCIBIOS_SUCCESSFUL;
191 if (schizo_out_of_range(pbm, bus, devfn))
192 return PCIBIOS_SUCCESSFUL;
196 pci_config_write8((u8 *)addr, value);
201 printk("pci_write_config_word: misaligned reg [%x]\n",
203 return PCIBIOS_SUCCESSFUL;
205 pci_config_write16((u16 *)addr, value);
210 printk("pci_write_config_dword: misaligned reg [%x]\n",
212 return PCIBIOS_SUCCESSFUL;
215 pci_config_write32(addr, value);
217 return PCIBIOS_SUCCESSFUL;
220 static struct pci_ops schizo_ops = {
221 .read = schizo_read_pci_cfg,
222 .write = schizo_write_pci_cfg,
225 /* SCHIZO error handling support. */
226 enum schizo_error_type {
227 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
230 static DEFINE_SPINLOCK(stc_buf_lock);
231 static unsigned long stc_error_buf[128];
232 static unsigned long stc_tag_buf[16];
233 static unsigned long stc_line_buf[16];
235 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
236 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
237 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
238 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
239 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
241 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
242 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
243 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
245 #define SCHIZO_STCERR_WRITE 0x2UL
246 #define SCHIZO_STCERR_READ 0x1UL
248 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
249 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
250 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
251 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
253 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
254 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
255 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
256 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
257 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
258 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
260 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
261 enum schizo_error_type type)
263 struct strbuf *strbuf = &pbm->stc;
264 unsigned long regbase = pbm->pbm_regs;
265 unsigned long err_base, tag_base, line_base;
269 err_base = regbase + SCHIZO_STC_ERR;
270 tag_base = regbase + SCHIZO_STC_TAG;
271 line_base = regbase + SCHIZO_STC_LINE;
273 spin_lock(&stc_buf_lock);
275 /* This is __REALLY__ dangerous. When we put the
276 * streaming buffer into diagnostic mode to probe
277 * it's tags and error status, we _must_ clear all
278 * of the line tag valid bits before re-enabling
279 * the streaming buffer. If any dirty data lives
280 * in the STC when we do this, we will end up
281 * invalidating it before it has a chance to reach
284 control = schizo_read(strbuf->strbuf_control);
285 schizo_write(strbuf->strbuf_control,
286 (control | SCHIZO_STRBUF_CTRL_DENAB));
287 for (i = 0; i < 128; i++) {
290 val = schizo_read(err_base + (i * 8UL));
291 schizo_write(err_base + (i * 8UL), 0UL);
292 stc_error_buf[i] = val;
294 for (i = 0; i < 16; i++) {
295 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
296 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
297 schizo_write(tag_base + (i * 8UL), 0UL);
298 schizo_write(line_base + (i * 8UL), 0UL);
301 /* OK, state is logged, exit diagnostic mode. */
302 schizo_write(strbuf->strbuf_control, control);
304 for (i = 0; i < 16; i++) {
305 int j, saw_error, first, last;
310 for (j = first; j < last; j++) {
311 unsigned long errval = stc_error_buf[j];
314 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
317 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
318 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
321 if (saw_error != 0) {
322 unsigned long tagval = stc_tag_buf[i];
323 unsigned long lineval = stc_line_buf[i];
324 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
327 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
328 (tagval & SCHIZO_STCTAG_VPN),
329 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
330 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
332 /* XXX Should spit out per-bank error information... -DaveM */
333 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
337 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
338 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
339 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
340 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
341 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
342 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
346 spin_unlock(&stc_buf_lock);
349 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
350 * controller level errors.
353 #define SCHIZO_IOMMU_TAG 0xa580UL
354 #define SCHIZO_IOMMU_DATA 0xa600UL
356 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
357 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
358 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
359 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
360 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
361 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
362 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
364 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
365 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
366 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
368 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
369 enum schizo_error_type type)
371 struct iommu *iommu = pbm->iommu;
372 unsigned long iommu_tag[16];
373 unsigned long iommu_data[16];
378 spin_lock_irqsave(&iommu->lock, flags);
379 control = schizo_read(iommu->iommu_control);
380 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
384 /* Clear the error encountered bit. */
385 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
386 schizo_write(iommu->iommu_control, control);
388 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
390 type_string = "Protection Error";
393 type_string = "Invalid Error";
396 type_string = "TimeOut Error";
400 type_string = "ECC Error";
403 printk("%s: IOMMU Error, type[%s]\n",
404 pbm->name, type_string);
406 /* Put the IOMMU into diagnostic mode and probe
407 * it's TLB for entries with error status.
409 * It is very possible for another DVMA to occur
410 * while we do this probe, and corrupt the system
411 * further. But we are so screwed at this point
412 * that we are likely to crash hard anyways, so
413 * get as much diagnostic information to the
416 schizo_write(iommu->iommu_control,
417 control | SCHIZO_IOMMU_CTRL_DENAB);
419 base = pbm->pbm_regs;
421 for (i = 0; i < 16; i++) {
423 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
425 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
427 /* Now clear out the entry. */
428 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
429 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
432 /* Leave diagnostic mode. */
433 schizo_write(iommu->iommu_control, control);
435 for (i = 0; i < 16; i++) {
436 unsigned long tag, data;
439 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
442 data = iommu_data[i];
443 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
445 type_string = "Protection Error";
448 type_string = "Invalid Error";
451 type_string = "TimeOut Error";
455 type_string = "ECC Error";
458 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
459 "sz(%dK) vpg(%08lx)]\n",
460 pbm->name, i, type_string,
461 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
462 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
463 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
464 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
465 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
466 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
468 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
469 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
470 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
473 if (pbm->stc.strbuf_enabled)
474 __schizo_check_stc_error_pbm(pbm, type);
475 spin_unlock_irqrestore(&iommu->lock, flags);
478 static void schizo_check_iommu_error(struct pci_controller_info *p,
479 enum schizo_error_type type)
481 schizo_check_iommu_error_pbm(&p->pbm_A, type);
482 schizo_check_iommu_error_pbm(&p->pbm_B, type);
485 /* Uncorrectable ECC error status gathering. */
486 #define SCHIZO_UE_AFSR 0x10030UL
487 #define SCHIZO_UE_AFAR 0x10038UL
489 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
490 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
491 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
492 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
493 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
494 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
495 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
496 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
497 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
498 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
499 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
500 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
501 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
502 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
504 static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
506 struct pci_pbm_info *pbm = dev_id;
507 struct pci_controller_info *p = pbm->parent;
508 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
509 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
510 unsigned long afsr, afar, error_bits;
513 /* Latch uncorrectable error status. */
514 afar = schizo_read(afar_reg);
516 /* If either of the error pending bits are set in the
517 * AFSR, the error status is being actively updated by
518 * the hardware and we must re-read to get a clean value.
522 afsr = schizo_read(afsr_reg);
523 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
525 /* Clear the primary/secondary error status bits. */
527 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
528 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
531 schizo_write(afsr_reg, error_bits);
534 printk("PCI%d: Uncorrectable Error, primary error type[%s]\n",
536 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
538 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
540 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
541 "DMA Write" : "???")))));
542 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
544 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
545 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
546 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
547 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
549 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
550 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
551 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
552 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
553 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
554 printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar);
555 printk("PCI%d: UE Secondary errors [", p->index);
557 if (afsr & SCHIZO_UEAFSR_SPIO) {
561 if (afsr & SCHIZO_UEAFSR_SDMA) {
569 /* Interrogate IOMMU for error status. */
570 schizo_check_iommu_error(p, UE_ERR);
575 #define SCHIZO_CE_AFSR 0x10040UL
576 #define SCHIZO_CE_AFAR 0x10048UL
578 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
579 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
580 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
581 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
582 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
583 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
584 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
585 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
586 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
587 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
588 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
589 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
590 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
591 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
593 static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
595 struct pci_pbm_info *pbm = dev_id;
596 struct pci_controller_info *p = pbm->parent;
597 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
598 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
599 unsigned long afsr, afar, error_bits;
602 /* Latch error status. */
603 afar = schizo_read(afar_reg);
605 /* If either of the error pending bits are set in the
606 * AFSR, the error status is being actively updated by
607 * the hardware and we must re-read to get a clean value.
611 afsr = schizo_read(afsr_reg);
612 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
614 /* Clear primary/secondary error status bits. */
616 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
617 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
620 schizo_write(afsr_reg, error_bits);
623 printk("PCI%d: Correctable Error, primary error type[%s]\n",
625 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
627 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
629 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
630 "DMA Write" : "???")))));
632 /* XXX Use syndrome and afar to print out module string just like
633 * XXX UDB CE trap handler does... -DaveM
635 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
637 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
638 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
639 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
640 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
642 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
643 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
644 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
645 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
646 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
647 printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar);
648 printk("PCI%d: CE Secondary errors [", p->index);
650 if (afsr & SCHIZO_CEAFSR_SPIO) {
654 if (afsr & SCHIZO_CEAFSR_SDMA) {
665 #define SCHIZO_PCI_AFSR 0x2010UL
666 #define SCHIZO_PCI_AFAR 0x2018UL
668 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
669 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
670 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
671 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
672 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
673 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
674 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
675 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
676 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
677 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
678 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
679 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
680 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
681 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
682 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
683 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
684 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
686 #define SCHIZO_PCI_CTRL (0x2000UL)
687 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
688 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
689 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
690 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
691 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
692 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
693 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
694 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
695 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
696 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
697 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
698 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
699 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
700 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
701 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
702 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
703 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
704 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
705 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
706 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
707 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
708 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
709 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
710 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
711 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
712 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
713 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
715 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
717 unsigned long csr_reg, csr, csr_error_bits;
718 irqreturn_t ret = IRQ_NONE;
721 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
722 csr = schizo_read(csr_reg);
724 csr & (SCHIZO_PCICTRL_BUS_UNUS |
725 SCHIZO_PCICTRL_TTO_ERR |
726 SCHIZO_PCICTRL_RTRY_ERR |
727 SCHIZO_PCICTRL_DTO_ERR |
728 SCHIZO_PCICTRL_SBH_ERR |
729 SCHIZO_PCICTRL_SERR);
730 if (csr_error_bits) {
731 /* Clear the errors. */
732 schizo_write(csr_reg, csr);
735 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
736 printk("%s: Bus unusable error asserted.\n",
738 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
739 printk("%s: PCI TRDY# timeout error asserted.\n",
741 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
742 printk("%s: PCI excessive retry error asserted.\n",
744 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
745 printk("%s: PCI discard timeout error asserted.\n",
747 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
748 printk("%s: PCI streaming byte hole error asserted.\n",
750 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
751 printk("%s: PCI SERR signal asserted.\n",
755 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
756 if (stat & (PCI_STATUS_PARITY |
757 PCI_STATUS_SIG_TARGET_ABORT |
758 PCI_STATUS_REC_TARGET_ABORT |
759 PCI_STATUS_REC_MASTER_ABORT |
760 PCI_STATUS_SIG_SYSTEM_ERROR)) {
761 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
763 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
769 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
771 struct pci_pbm_info *pbm = dev_id;
772 struct pci_controller_info *p = pbm->parent;
773 unsigned long afsr_reg, afar_reg, base;
774 unsigned long afsr, afar, error_bits;
777 base = pbm->pbm_regs;
779 afsr_reg = base + SCHIZO_PCI_AFSR;
780 afar_reg = base + SCHIZO_PCI_AFAR;
782 /* Latch error status. */
783 afar = schizo_read(afar_reg);
784 afsr = schizo_read(afsr_reg);
786 /* Clear primary/secondary error status bits. */
788 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
789 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
790 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
791 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
792 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
793 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
795 return schizo_pcierr_intr_other(pbm);
796 schizo_write(afsr_reg, error_bits);
799 printk("%s: PCI Error, primary error type[%s]\n",
801 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
803 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
805 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
806 "Excessive Retries" :
807 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
809 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
811 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
812 "Bus Unusable" : "???"))))))));
813 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
815 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
816 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
817 ((afsr & SCHIZO_PCIAFSR_CFG) ?
819 ((afsr & SCHIZO_PCIAFSR_MEM) ?
821 ((afsr & SCHIZO_PCIAFSR_IO) ?
823 printk("%s: PCI AFAR [%016lx]\n",
825 printk("%s: PCI Secondary errors [",
828 if (afsr & SCHIZO_PCIAFSR_SMA) {
830 printk("(Master Abort)");
832 if (afsr & SCHIZO_PCIAFSR_STA) {
834 printk("(Target Abort)");
836 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
838 printk("(Excessive Retries)");
840 if (afsr & SCHIZO_PCIAFSR_SPERR) {
842 printk("(Parity Error)");
844 if (afsr & SCHIZO_PCIAFSR_STTO) {
848 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
850 printk("(Bus Unusable)");
856 /* For the error types shown, scan PBM's PCI bus for devices
857 * which have logged that error type.
860 /* If we see a Target Abort, this could be the result of an
861 * IOMMU translation error of some sort. It is extremely
862 * useful to log this information as usually it indicates
863 * a bug in the IOMMU support code or a PCI device driver.
865 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
866 schizo_check_iommu_error(p, PCI_ERR);
867 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
869 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
870 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
872 /* For excessive retries, PSYCHO/PBM will abort the device
873 * and there is no way to specifically check for excessive
874 * retries in the config space status registers. So what
875 * we hope is that we'll catch it via the master/target
879 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
880 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
885 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
887 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
889 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
890 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
891 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
892 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
893 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
894 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
895 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
896 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
897 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
898 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
899 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
900 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
901 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
902 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
903 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
904 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
905 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
906 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
907 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
908 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
909 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
910 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
911 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
912 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
913 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
914 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
915 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
916 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
917 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
918 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
919 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
921 /* We only expect UNMAP errors here. The rest of the Safari errors
922 * are marked fatal and thus cause a system reset.
924 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
926 struct pci_pbm_info *pbm = dev_id;
927 struct pci_controller_info *p = pbm->parent;
930 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
931 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG,
932 errlog & ~(SAFARI_ERRLOG_ERROUT));
934 if (!(errlog & BUS_ERROR_UNMAP)) {
935 printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
941 printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
943 schizo_check_iommu_error(p, SAFARI_ERR);
948 /* Nearly identical to PSYCHO equivalents... */
949 #define SCHIZO_ECC_CTRL 0x10020UL
950 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
951 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
952 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
954 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
955 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
956 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
957 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
959 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
963 if (pbm->ino_bitmap & (1UL << ino))
969 /* How the Tomatillo IRQs are routed around is pure guesswork here.
971 * All the Tomatillo devices I see in prtconf dumps seem to have only
972 * a single PCI bus unit attached to it. It would seem they are seperate
973 * devices because their PortID (ie. JBUS ID) values are all different
974 * and thus the registers are mapped to totally different locations.
976 * However, two Tomatillo's look "similar" in that the only difference
977 * in their PortID is the lowest bit.
979 * So if we were to ignore this lower bit, it certainly looks like two
980 * PCI bus units of the same Tomatillo. I still have not really
981 * figured this out...
983 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
985 struct of_device *op = of_find_device_by_node(pbm->prom_node);
986 u64 tmp, err_mask, err_no_mask;
988 /* Tomatillo IRQ property layout is:
996 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO))
997 request_irq(op->irqs[1], schizo_ue_intr, 0,
998 "TOMATILLO_UE", pbm);
1000 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO))
1001 request_irq(op->irqs[2], schizo_ce_intr, 0,
1002 "TOMATILLO_CE", pbm);
1004 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO))
1005 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1006 "TOMATILLO_PCIERR", pbm);
1007 else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO))
1008 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1009 "TOMATILLO_PCIERR", pbm);
1011 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO))
1012 request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1013 "TOMATILLO_SERR", pbm);
1015 /* Enable UE and CE interrupts for controller. */
1016 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1017 (SCHIZO_ECCCTRL_EE |
1019 SCHIZO_ECCCTRL_CE));
1021 /* Enable PCI Error interrupts and clear error
1024 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1025 SCHIZO_PCICTRL_TTO_ERR |
1026 SCHIZO_PCICTRL_RTRY_ERR |
1027 SCHIZO_PCICTRL_SERR |
1028 SCHIZO_PCICTRL_EEN);
1030 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
1032 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1034 tmp &= ~err_no_mask;
1035 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1037 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1038 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1039 SCHIZO_PCIAFSR_PTTO |
1040 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1041 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1042 SCHIZO_PCIAFSR_STTO);
1044 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1046 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
1047 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
1048 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
1049 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
1050 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
1051 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
1052 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
1053 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
1054 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
1056 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1057 (SCHIZO_SAFERRCTRL_EN | err_mask));
1059 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL,
1060 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1063 static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1065 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1066 u64 tmp, err_mask, err_no_mask;
1068 /* Schizo IRQ property layout is:
1076 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO))
1077 request_irq(op->irqs[1], schizo_ue_intr, 0,
1080 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO))
1081 request_irq(op->irqs[2], schizo_ce_intr, 0,
1084 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO))
1085 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1086 "SCHIZO_PCIERR", pbm);
1087 else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO))
1088 request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1089 "SCHIZO_PCIERR", pbm);
1091 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO))
1092 request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1093 "SCHIZO_SERR", pbm);
1095 /* Enable UE and CE interrupts for controller. */
1096 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1097 (SCHIZO_ECCCTRL_EE |
1099 SCHIZO_ECCCTRL_CE));
1101 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1102 SCHIZO_PCICTRL_ESLCK |
1103 SCHIZO_PCICTRL_TTO_ERR |
1104 SCHIZO_PCICTRL_RTRY_ERR |
1105 SCHIZO_PCICTRL_SBH_ERR |
1106 SCHIZO_PCICTRL_SERR |
1107 SCHIZO_PCICTRL_EEN);
1109 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1110 SCHIZO_PCICTRL_SBH_INT);
1112 /* Enable PCI Error interrupts and clear error
1113 * bits for each PBM.
1115 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1117 tmp &= ~err_no_mask;
1118 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1120 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR,
1121 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1122 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1123 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1124 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1125 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1126 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1128 /* Make all Safari error conditions fatal except unmapped
1129 * errors which we make generate interrupts.
1131 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1132 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1134 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1135 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1137 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1138 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1139 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1142 /* XXX Something wrong with some Excalibur systems
1143 * XXX Sun is shipping. The behavior on a 2-cpu
1144 * XXX machine is that both CPU1 parity error bits
1145 * XXX are set and are immediately set again when
1146 * XXX their error status bits are cleared. Just
1147 * XXX ignore them for now. -DaveM
1149 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1150 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1153 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1154 (SCHIZO_SAFERRCTRL_EN | err_mask));
1157 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1161 /* Set cache-line size to 64 bytes, this is actually
1162 * a nop but I do it for completeness.
1164 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1165 0, PCI_CACHE_LINE_SIZE);
1166 pci_config_write8(addr, 64 / sizeof(u32));
1168 /* Set PBM latency timer to 64 PCI clocks. */
1169 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1170 0, PCI_LATENCY_TIMER);
1171 pci_config_write8(addr, 64);
1174 static void schizo_scan_bus(struct pci_pbm_info *pbm)
1176 pbm_config_busmastering(pbm);
1177 pbm->is_66mhz_capable =
1178 (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
1181 pbm->pci_bus = pci_scan_one_pbm(pbm);
1183 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1184 tomatillo_register_error_handlers(pbm);
1186 schizo_register_error_handlers(pbm);
1189 #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1190 #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1191 #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1192 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1193 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1195 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1197 unsigned long base = pbm->pbm_regs;
1200 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1201 /* TOMATILLO lacks streaming cache. */
1205 /* SCHIZO has context flushing. */
1206 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1207 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1208 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1209 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1210 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1212 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1213 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1216 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1217 __pa(pbm->stc.strbuf_flushflag);
1219 /* Turn off LRU locking and diag mode, enable the
1220 * streaming buffer and leave the rerun-disable
1221 * setting however OBP set it.
1223 control = schizo_read(pbm->stc.strbuf_control);
1224 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1225 SCHIZO_STRBUF_CTRL_LENAB |
1226 SCHIZO_STRBUF_CTRL_DENAB);
1227 control |= SCHIZO_STRBUF_CTRL_ENAB;
1228 schizo_write(pbm->stc.strbuf_control, control);
1230 pbm->stc.strbuf_enabled = 1;
1233 #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1234 #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1235 #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1236 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1238 static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1240 struct iommu *iommu = pbm->iommu;
1241 unsigned long i, tagbase, database;
1242 struct property *prop;
1243 u32 vdma[2], dma_mask;
1247 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
1249 u32 *val = prop->value;
1254 /* No property, use default values. */
1255 vdma[0] = 0xc0000000;
1256 vdma[1] = 0x40000000;
1262 dma_mask |= 0x1fffffff;
1267 dma_mask |= 0x3fffffff;
1272 dma_mask |= 0x7fffffff;
1277 prom_printf("SCHIZO: strange virtual-dma size.\n");
1281 /* Register addresses, SCHIZO has iommu ctx flushing. */
1282 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1283 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1284 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1285 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1287 /* We use the main control/status register of SCHIZO as the write
1288 * completion register.
1290 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1293 * Invalidate TLB Entries.
1295 control = schizo_read(iommu->iommu_control);
1296 control |= SCHIZO_IOMMU_CTRL_DENAB;
1297 schizo_write(iommu->iommu_control, control);
1299 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1301 for(i = 0; i < 16; i++) {
1302 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1303 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1306 /* Leave diag mode enabled for full-flushing done
1309 pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
1311 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1313 control = schizo_read(iommu->iommu_control);
1314 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1317 control |= SCHIZO_IOMMU_TSBSZ_64K;
1320 control |= SCHIZO_IOMMU_TSBSZ_128K;
1324 control |= SCHIZO_IOMMU_CTRL_ENAB;
1325 schizo_write(iommu->iommu_control, control);
1328 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1329 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1331 #define SCHIZO_PCI_DIAG (0x2020UL)
1332 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1333 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1334 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1335 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1336 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1337 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1338 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1339 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1340 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1342 #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1343 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1344 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1345 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1346 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1347 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1348 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1349 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1350 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1351 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1352 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1353 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1354 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1355 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1356 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1357 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1359 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1360 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1362 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1364 struct property *prop;
1367 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1369 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1371 /* Enable arbiter for all PCI slots. */
1374 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1375 pbm->chip_version >= 0x2)
1376 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1378 prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL);
1380 tmp |= SCHIZO_PCICTRL_PARK;
1382 tmp &= ~SCHIZO_PCICTRL_PARK;
1384 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1385 pbm->chip_version <= 0x1)
1386 tmp |= SCHIZO_PCICTRL_DTO_INT;
1388 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1390 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1391 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1392 SCHIZO_PCICTRL_RDO_PREF |
1393 SCHIZO_PCICTRL_RDL_PREF);
1395 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1397 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1398 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1399 SCHIZO_PCIDIAG_D_RETRY |
1400 SCHIZO_PCIDIAG_D_INTSYNC);
1401 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1403 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1404 /* Clear prefetch lengths to workaround a bug in
1407 tmp = (TOMATILLO_IOC_PART_WPENAB |
1408 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1409 TOMATILLO_IOC_RDMULT_CPENAB |
1410 TOMATILLO_IOC_RDONE_CPENAB |
1411 TOMATILLO_IOC_RDLINE_CPENAB);
1413 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1418 static void schizo_pbm_init(struct pci_controller_info *p,
1419 struct device_node *dp, u32 portid,
1422 const struct linux_prom64_registers *regs;
1423 struct pci_pbm_info *pbm;
1424 const char *chipset_name;
1427 switch (chip_type) {
1428 case PBM_CHIP_TYPE_TOMATILLO:
1429 chipset_name = "TOMATILLO";
1432 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1433 chipset_name = "SCHIZO+";
1436 case PBM_CHIP_TYPE_SCHIZO:
1438 chipset_name = "SCHIZO";
1442 /* For SCHIZO, three OBP regs:
1443 * 1) PBM controller regs
1444 * 2) Schizo front-end controller regs (same for both PBMs)
1445 * 3) PBM PCI config space
1447 * For TOMATILLO, four OBP regs:
1448 * 1) PBM controller regs
1449 * 2) Tomatillo front-end controller regs
1450 * 3) PBM PCI config space
1453 regs = of_get_property(dp, "reg", NULL);
1455 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1461 pbm->next = pci_pbm_root;
1464 pbm->scan_bus = schizo_scan_bus;
1465 pbm->pci_ops = &schizo_ops;
1467 pbm->portid = portid;
1469 pbm->prom_node = dp;
1471 pbm->chip_type = chip_type;
1472 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1473 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
1475 pbm->pbm_regs = regs[0].phys_addr;
1476 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1478 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1479 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
1481 pbm->name = dp->full_name;
1483 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
1484 pbm->name, chipset_name,
1485 pbm->chip_version, pbm->chip_revision);
1487 schizo_pbm_hw_init(pbm);
1489 pci_determine_mem_io_space(pbm);
1491 pci_get_pbm_props(pbm);
1493 schizo_pbm_iommu_init(pbm);
1494 schizo_pbm_strbuf_init(pbm);
1497 static inline int portid_compare(u32 x, u32 y, int chip_type)
1499 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1507 static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
1509 struct pci_controller_info *p;
1510 struct pci_pbm_info *pbm;
1511 struct iommu *iommu;
1514 portid = of_getintprop_default(dp, "portid", 0xff);
1516 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1517 if (portid_compare(pbm->portid, portid, chip_type)) {
1518 schizo_pbm_init(pbm->parent, dp, portid, chip_type);
1523 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1527 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1531 p->pbm_A.iommu = iommu;
1533 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1537 p->pbm_B.iommu = iommu;
1539 p->index = pci_num_controllers++;
1541 /* Like PSYCHO we have a 2GB aligned area for memory space. */
1542 pci_memspace_mask = 0x7fffffffUL;
1544 schizo_pbm_init(p, dp, portid, chip_type);
1548 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1552 void schizo_init(struct device_node *dp, char *model_name)
1554 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO);
1557 void schizo_plus_init(struct device_node *dp, char *model_name)
1559 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
1562 void tomatillo_init(struct device_node *dp, char *model_name)
1564 __schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO);