1 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
15 #include <asm/iommu.h>
17 #include <asm/starfire.h>
19 #include <asm/of_device.h>
20 #include <asm/oplib.h>
23 #include "iommu_common.h"
25 /* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
29 #define psycho_read(__reg) \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
37 #define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
44 /* Misc. PSYCHO PCI controller register offsets and definitions. */
45 #define PSYCHO_CONTROL 0x0010UL
46 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55 #define PSYCHO_PCIA_CTRL 0x2000UL
56 #define PSYCHO_PCIB_CTRL 0x4000UL
57 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
70 /* U2P Programmer's Manual, page 13-55, configuration space
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
78 #define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
85 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
97 static int psycho_out_of_range(struct pci_pbm_info *pbm,
101 return ((bus == pbm->pci_first_busno) &&
102 PCI_SLOT(devfn) > 8);
105 /* PSYCHO PCI configuration space accessors. */
107 static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
108 int where, int size, u32 *value)
110 struct pci_pbm_info *pbm = bus_dev->sysdata;
111 unsigned char bus = bus_dev->number;
116 if (bus_dev == pbm->pci_bus && devfn == 0x00)
117 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
132 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
134 return PCIBIOS_SUCCESSFUL;
136 if (psycho_out_of_range(pbm, bus, devfn))
137 return PCIBIOS_SUCCESSFUL;
140 pci_config_read8((u8 *)addr, &tmp8);
146 printk("pci_read_config_word: misaligned reg [%x]\n",
148 return PCIBIOS_SUCCESSFUL;
150 pci_config_read16((u16 *)addr, &tmp16);
151 *value = (u32) tmp16;
156 printk("pci_read_config_dword: misaligned reg [%x]\n",
158 return PCIBIOS_SUCCESSFUL;
160 pci_config_read32(addr, value);
163 return PCIBIOS_SUCCESSFUL;
166 static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
167 int where, int size, u32 value)
169 struct pci_pbm_info *pbm = bus_dev->sysdata;
170 unsigned char bus = bus_dev->number;
173 if (bus_dev == pbm->pci_bus && devfn == 0x00)
174 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
176 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
178 return PCIBIOS_SUCCESSFUL;
180 if (psycho_out_of_range(pbm, bus, devfn))
181 return PCIBIOS_SUCCESSFUL;
185 pci_config_write8((u8 *)addr, value);
190 printk("pci_write_config_word: misaligned reg [%x]\n",
192 return PCIBIOS_SUCCESSFUL;
194 pci_config_write16((u16 *)addr, value);
199 printk("pci_write_config_dword: misaligned reg [%x]\n",
201 return PCIBIOS_SUCCESSFUL;
203 pci_config_write32(addr, value);
205 return PCIBIOS_SUCCESSFUL;
208 static struct pci_ops psycho_ops = {
209 .read = psycho_read_pci_cfg,
210 .write = psycho_write_pci_cfg,
213 /* PSYCHO error handling support. */
214 enum psycho_error_type {
215 UE_ERR, CE_ERR, PCI_ERR
218 /* Helper function of IOMMU error checking, which checks out
219 * the state of the streaming buffers. The IOMMU lock is
220 * held when this is called.
222 * For the PCI error case we know which PBM (and thus which
223 * streaming buffer) caused the error, but for the uncorrectable
224 * error case we do not. So we always check both streaming caches.
226 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
227 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
228 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
229 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
230 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
231 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
232 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
233 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
234 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
235 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
236 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
237 #define PSYCHO_STC_DATA_A 0xb000UL
238 #define PSYCHO_STC_DATA_B 0xc000UL
239 #define PSYCHO_STC_ERR_A 0xb400UL
240 #define PSYCHO_STC_ERR_B 0xc400UL
241 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
242 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
243 #define PSYCHO_STC_TAG_A 0xb800UL
244 #define PSYCHO_STC_TAG_B 0xc800UL
245 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
246 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
247 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
248 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
249 #define PSYCHO_STC_LINE_A 0xb900UL
250 #define PSYCHO_STC_LINE_B 0xc900UL
251 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
252 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
253 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
254 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
255 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
256 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
258 static DEFINE_SPINLOCK(stc_buf_lock);
259 static unsigned long stc_error_buf[128];
260 static unsigned long stc_tag_buf[16];
261 static unsigned long stc_line_buf[16];
263 static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
266 struct strbuf *strbuf = &pbm->stc;
267 unsigned long regbase = pbm->controller_regs;
268 unsigned long err_base, tag_base, line_base;
273 err_base = regbase + PSYCHO_STC_ERR_A;
274 tag_base = regbase + PSYCHO_STC_TAG_A;
275 line_base = regbase + PSYCHO_STC_LINE_A;
277 err_base = regbase + PSYCHO_STC_ERR_B;
278 tag_base = regbase + PSYCHO_STC_TAG_B;
279 line_base = regbase + PSYCHO_STC_LINE_B;
282 spin_lock(&stc_buf_lock);
284 /* This is __REALLY__ dangerous. When we put the
285 * streaming buffer into diagnostic mode to probe
286 * it's tags and error status, we _must_ clear all
287 * of the line tag valid bits before re-enabling
288 * the streaming buffer. If any dirty data lives
289 * in the STC when we do this, we will end up
290 * invalidating it before it has a chance to reach
293 control = psycho_read(strbuf->strbuf_control);
294 psycho_write(strbuf->strbuf_control,
295 (control | PSYCHO_STRBUF_CTRL_DENAB));
296 for (i = 0; i < 128; i++) {
299 val = psycho_read(err_base + (i * 8UL));
300 psycho_write(err_base + (i * 8UL), 0UL);
301 stc_error_buf[i] = val;
303 for (i = 0; i < 16; i++) {
304 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
305 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
306 psycho_write(tag_base + (i * 8UL), 0UL);
307 psycho_write(line_base + (i * 8UL), 0UL);
310 /* OK, state is logged, exit diagnostic mode. */
311 psycho_write(strbuf->strbuf_control, control);
313 for (i = 0; i < 16; i++) {
314 int j, saw_error, first, last;
319 for (j = first; j < last; j++) {
320 unsigned long errval = stc_error_buf[j];
323 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
326 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
327 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
330 if (saw_error != 0) {
331 unsigned long tagval = stc_tag_buf[i];
332 unsigned long lineval = stc_line_buf[i];
333 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
336 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
337 (tagval & PSYCHO_STCTAG_VPN),
338 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
339 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
340 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
344 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
345 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
346 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
347 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
348 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
349 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
353 spin_unlock(&stc_buf_lock);
356 static void __psycho_check_stc_error(struct pci_pbm_info *pbm,
359 enum psycho_error_type type)
361 __psycho_check_one_stc(pbm,
362 (pbm == &pbm->parent->pbm_A));
365 /* When an Uncorrectable Error or a PCI Error happens, we
366 * interrogate the IOMMU state to see if it is the cause.
368 #define PSYCHO_IOMMU_CONTROL 0x0200UL
369 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
370 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
371 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
372 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
373 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
374 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
375 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
376 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
377 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
378 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
379 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
380 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
381 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
382 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
383 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
384 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
385 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
386 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
387 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
388 #define PSYCHO_IOMMU_FLUSH 0x0210UL
389 #define PSYCHO_IOMMU_TAG 0xa580UL
390 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
391 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
392 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
393 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
394 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
395 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
396 #define PSYCHO_IOMMU_DATA 0xa600UL
397 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
398 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
399 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
400 static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
403 enum psycho_error_type type)
405 struct iommu *iommu = pbm->iommu;
406 unsigned long iommu_tag[16];
407 unsigned long iommu_data[16];
412 spin_lock_irqsave(&iommu->lock, flags);
413 control = psycho_read(iommu->iommu_control);
414 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
417 /* Clear the error encountered bit. */
418 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
419 psycho_write(iommu->iommu_control, control);
421 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
423 type_string = "Protection Error";
426 type_string = "Invalid Error";
429 type_string = "TimeOut Error";
433 type_string = "ECC Error";
436 printk("%s: IOMMU Error, type[%s]\n",
437 pbm->name, type_string);
439 /* Put the IOMMU into diagnostic mode and probe
440 * it's TLB for entries with error status.
442 * It is very possible for another DVMA to occur
443 * while we do this probe, and corrupt the system
444 * further. But we are so screwed at this point
445 * that we are likely to crash hard anyways, so
446 * get as much diagnostic information to the
449 psycho_write(iommu->iommu_control,
450 control | PSYCHO_IOMMU_CTRL_DENAB);
451 for (i = 0; i < 16; i++) {
452 unsigned long base = pbm->controller_regs;
455 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
457 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
459 /* Now clear out the entry. */
460 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
461 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
464 /* Leave diagnostic mode. */
465 psycho_write(iommu->iommu_control, control);
467 for (i = 0; i < 16; i++) {
468 unsigned long tag, data;
471 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
474 data = iommu_data[i];
475 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
477 type_string = "Protection Error";
480 type_string = "Invalid Error";
483 type_string = "TimeOut Error";
487 type_string = "ECC Error";
490 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
491 pbm->name, i, type_string,
492 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
493 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
494 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
495 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
496 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
498 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
499 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
500 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
503 __psycho_check_stc_error(pbm, afsr, afar, type);
504 spin_unlock_irqrestore(&iommu->lock, flags);
507 /* Uncorrectable Errors. Cause of the error and the address are
508 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
509 * relating to UPA interface transactions.
511 #define PSYCHO_UE_AFSR 0x0030UL
512 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
513 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
514 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
515 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
516 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
517 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
518 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
519 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
520 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
521 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
522 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
523 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
524 #define PSYCHO_UE_AFAR 0x0038UL
526 static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
528 struct pci_pbm_info *pbm = dev_id;
529 struct pci_controller_info *p = pbm->parent;
530 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
531 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
532 unsigned long afsr, afar, error_bits;
535 /* Latch uncorrectable error status. */
536 afar = psycho_read(afar_reg);
537 afsr = psycho_read(afsr_reg);
539 /* Clear the primary/secondary error status bits. */
541 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
542 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
545 psycho_write(afsr_reg, error_bits);
548 printk("%s: Uncorrectable Error, primary error type[%s]\n",
550 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
552 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
554 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
555 "DMA Write" : "???")))));
556 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
558 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
559 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
560 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
561 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
562 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
563 printk("%s: UE Secondary errors [", pbm->name);
565 if (afsr & PSYCHO_UEAFSR_SPIO) {
569 if (afsr & PSYCHO_UEAFSR_SDRD) {
571 printk("(DMA Read)");
573 if (afsr & PSYCHO_UEAFSR_SDWR) {
575 printk("(DMA Write)");
581 /* Interrogate both IOMMUs for error status. */
582 psycho_check_iommu_error(&p->pbm_A, afsr, afar, UE_ERR);
583 psycho_check_iommu_error(&p->pbm_B, afsr, afar, UE_ERR);
588 /* Correctable Errors. */
589 #define PSYCHO_CE_AFSR 0x0040UL
590 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
591 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
592 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
593 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
594 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
595 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
596 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
597 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
598 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
599 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
600 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
601 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
602 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
603 #define PSYCHO_CE_AFAR 0x0040UL
605 static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
607 struct pci_pbm_info *pbm = dev_id;
608 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
609 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
610 unsigned long afsr, afar, error_bits;
613 /* Latch error status. */
614 afar = psycho_read(afar_reg);
615 afsr = psycho_read(afsr_reg);
617 /* Clear primary/secondary error status bits. */
619 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
620 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
623 psycho_write(afsr_reg, error_bits);
626 printk("%s: Correctable Error, primary error type[%s]\n",
628 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
630 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
632 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
633 "DMA Write" : "???")))));
635 /* XXX Use syndrome and afar to print out module string just like
636 * XXX UDB CE trap handler does... -DaveM
638 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
639 "UPA_MID[%02lx] was_block(%d)\n",
641 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
642 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
643 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
644 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
645 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
646 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
647 printk("%s: CE Secondary errors [", pbm->name);
649 if (afsr & PSYCHO_CEAFSR_SPIO) {
653 if (afsr & PSYCHO_CEAFSR_SDRD) {
655 printk("(DMA Read)");
657 if (afsr & PSYCHO_CEAFSR_SDWR) {
659 printk("(DMA Write)");
668 /* PCI Errors. They are signalled by the PCI bus module since they
669 * are associated with a specific bus segment.
671 #define PSYCHO_PCI_AFSR_A 0x2010UL
672 #define PSYCHO_PCI_AFSR_B 0x4010UL
673 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
674 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
675 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
676 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
677 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
678 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
679 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
680 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
681 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
682 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
683 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
684 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
685 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
686 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
687 #define PSYCHO_PCI_AFAR_A 0x2018UL
688 #define PSYCHO_PCI_AFAR_B 0x4018UL
690 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
692 unsigned long csr_reg, csr, csr_error_bits;
693 irqreturn_t ret = IRQ_NONE;
697 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
699 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
701 csr = psycho_read(csr_reg);
703 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
704 if (csr_error_bits) {
705 /* Clear the errors. */
706 psycho_write(csr_reg, csr);
709 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
710 printk("%s: PCI streaming byte hole error asserted.\n",
712 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
713 printk("%s: PCI SERR signal asserted.\n", pbm->name);
716 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
717 if (stat & (PCI_STATUS_PARITY |
718 PCI_STATUS_SIG_TARGET_ABORT |
719 PCI_STATUS_REC_TARGET_ABORT |
720 PCI_STATUS_REC_MASTER_ABORT |
721 PCI_STATUS_SIG_SYSTEM_ERROR)) {
722 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
724 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
730 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
732 struct pci_pbm_info *pbm = dev_id;
733 struct pci_controller_info *p = pbm->parent;
734 unsigned long afsr_reg, afar_reg;
735 unsigned long afsr, afar, error_bits;
736 int is_pbm_a, reported;
738 is_pbm_a = (pbm == &pbm->parent->pbm_A);
740 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
741 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
743 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
744 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
747 /* Latch error status. */
748 afar = psycho_read(afar_reg);
749 afsr = psycho_read(afsr_reg);
751 /* Clear primary/secondary error status bits. */
753 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
754 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
755 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
756 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
758 return psycho_pcierr_intr_other(pbm, is_pbm_a);
759 psycho_write(afsr_reg, error_bits);
762 printk("%s: PCI Error, primary error type[%s]\n",
764 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
766 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
768 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
769 "Excessive Retries" :
770 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
771 "Parity Error" : "???"))))));
772 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
774 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
775 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
776 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
777 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
778 printk("%s: PCI Secondary errors [", pbm->name);
780 if (afsr & PSYCHO_PCIAFSR_SMA) {
782 printk("(Master Abort)");
784 if (afsr & PSYCHO_PCIAFSR_STA) {
786 printk("(Target Abort)");
788 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
790 printk("(Excessive Retries)");
792 if (afsr & PSYCHO_PCIAFSR_SPERR) {
794 printk("(Parity Error)");
800 /* For the error types shown, scan PBM's PCI bus for devices
801 * which have logged that error type.
804 /* If we see a Target Abort, this could be the result of an
805 * IOMMU translation error of some sort. It is extremely
806 * useful to log this information as usually it indicates
807 * a bug in the IOMMU support code or a PCI device driver.
809 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
810 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
811 pci_scan_for_target_abort(pbm, pbm->pci_bus);
813 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
814 pci_scan_for_master_abort(pbm, pbm->pci_bus);
816 /* For excessive retries, PSYCHO/PBM will abort the device
817 * and there is no way to specifically check for excessive
818 * retries in the config space status registers. So what
819 * we hope is that we'll catch it via the master/target
823 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
824 pci_scan_for_parity_error(pbm, pbm->pci_bus);
829 /* XXX What about PowerFail/PowerManagement??? -DaveM */
830 #define PSYCHO_ECC_CTRL 0x0020
831 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
832 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
833 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
834 static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
836 struct of_device *op = of_find_device_by_node(pbm->prom_node);
837 unsigned long base = pbm->controller_regs;
844 /* Psycho interrupt property order is:
845 * 0: PCIERR INO for this PBM
850 * 5: POWER MANAGEMENT
853 if (op->num_irqs < 6)
856 /* We really mean to ignore the return result here. Two
857 * PCI controller share the same interrupt numbers and
858 * drive the same front-end hardware. Whichever of the
859 * two get in here first will register the IRQ handler
860 * the second will just error out since we do not pass in
863 err = request_irq(op->irqs[1], psycho_ue_intr, 0,
865 err = request_irq(op->irqs[2], psycho_ce_intr, 0,
868 /* This one, however, ought not to fail. We can just warn
869 * about it since the system can still operate properly even
872 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
873 "PSYCHO_PCIERR", pbm);
875 printk(KERN_WARNING "%s: Could not register PCIERR, "
876 "err=%d\n", pbm->name, err);
878 /* Enable UE and CE interrupts for controller. */
879 psycho_write(base + PSYCHO_ECC_CTRL,
884 /* Enable PCI Error interrupts and clear error
887 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
888 tmp |= (PSYCHO_PCICTRL_SERR |
889 PSYCHO_PCICTRL_SBH_ERR |
891 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
892 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
894 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
895 tmp |= (PSYCHO_PCICTRL_SERR |
896 PSYCHO_PCICTRL_SBH_ERR |
898 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
899 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
902 /* PSYCHO boot time probing and initialization. */
903 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
907 /* Set cache-line size to 64 bytes, this is actually
908 * a nop but I do it for completeness.
910 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
911 0, PCI_CACHE_LINE_SIZE);
912 pci_config_write8(addr, 64 / sizeof(u32));
914 /* Set PBM latency timer to 64 PCI clocks. */
915 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
916 0, PCI_LATENCY_TIMER);
917 pci_config_write8(addr, 64);
920 static void psycho_scan_bus(struct pci_pbm_info *pbm)
922 pbm_config_busmastering(pbm);
923 pbm->is_66mhz_capable = 0;
924 pbm->pci_bus = pci_scan_one_pbm(pbm);
926 /* After the PCI bus scan is complete, we can register
927 * the error interrupt handlers.
929 psycho_register_error_handlers(pbm);
932 static void psycho_iommu_init(struct pci_pbm_info *pbm)
934 struct iommu *iommu = pbm->iommu;
938 /* Register addresses. */
939 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
940 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
941 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
942 /* PSYCHO's IOMMU lacks ctx flushing. */
943 iommu->iommu_ctxflush = 0;
945 /* We use the main control register of PSYCHO as the write
946 * completion register.
948 iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL;
951 * Invalidate TLB Entries.
953 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
954 control |= PSYCHO_IOMMU_CTRL_DENAB;
955 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
956 for(i = 0; i < 16; i++) {
957 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
958 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
961 /* Leave diag mode enabled for full-flushing done
964 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
966 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE,
967 __pa(iommu->page_table));
969 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
970 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
971 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
972 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
974 /* If necessary, hook us up for starfire IRQ translations. */
975 if (this_is_starfire)
976 starfire_hookup(pbm->portid);
979 #define PSYCHO_IRQ_RETRY 0x1a00UL
980 #define PSYCHO_PCIA_DIAG 0x2020UL
981 #define PSYCHO_PCIB_DIAG 0x4020UL
982 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
983 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
984 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
985 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
986 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
987 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
988 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
989 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
991 static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
995 psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5);
997 /* Enable arbiter for all PCI slots. */
998 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL);
999 tmp |= PSYCHO_PCICTRL_AEN;
1000 psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp);
1002 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL);
1003 tmp |= PSYCHO_PCICTRL_AEN;
1004 psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp);
1006 /* Disable DMA write / PIO read synchronization on
1007 * both PCI bus segments.
1008 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1010 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG);
1011 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1012 psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp);
1014 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG);
1015 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1016 psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp);
1019 static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
1022 unsigned long base = pbm->controller_regs;
1026 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1027 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1028 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1030 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1031 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1032 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1034 /* PSYCHO's streaming buffer lacks ctx flushing. */
1035 pbm->stc.strbuf_ctxflush = 0;
1036 pbm->stc.strbuf_ctxmatch_base = 0;
1038 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1039 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1042 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1043 __pa(pbm->stc.strbuf_flushflag);
1045 /* Enable the streaming buffer. We have to be careful
1046 * just in case OBP left it with LRU locking enabled.
1048 * It is possible to control if PBM will be rerun on
1049 * line misses. Currently I just retain whatever setting
1050 * OBP left us with. All checks so far show it having
1053 #undef PSYCHO_STRBUF_RERUN_ENABLE
1054 #undef PSYCHO_STRBUF_RERUN_DISABLE
1055 control = psycho_read(pbm->stc.strbuf_control);
1056 control |= PSYCHO_STRBUF_CTRL_ENAB;
1057 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1058 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1059 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1061 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1062 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1065 psycho_write(pbm->stc.strbuf_control, control);
1067 pbm->stc.strbuf_enabled = 1;
1070 #define PSYCHO_IOSPACE_A 0x002000000UL
1071 #define PSYCHO_IOSPACE_B 0x002010000UL
1072 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1073 #define PSYCHO_MEMSPACE_A 0x100000000UL
1074 #define PSYCHO_MEMSPACE_B 0x180000000UL
1075 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1077 static void psycho_pbm_init(struct pci_controller_info *p,
1078 struct device_node *dp, int is_pbm_a)
1080 struct property *prop;
1081 struct pci_pbm_info *pbm;
1088 pbm->next = pci_pbm_root;
1091 pbm->scan_bus = psycho_scan_bus;
1092 pbm->pci_ops = &psycho_ops;
1094 pbm->index = pci_num_pbms++;
1096 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
1097 pbm->chip_version = 0;
1098 prop = of_find_property(dp, "version#", NULL);
1100 pbm->chip_version = *(int *) prop->value;
1101 pbm->chip_revision = 0;
1102 prop = of_find_property(dp, "module-revision#", NULL);
1104 pbm->chip_revision = *(int *) prop->value;
1107 pbm->prom_node = dp;
1108 pbm->name = dp->full_name;
1110 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1112 pbm->chip_version, pbm->chip_revision);
1114 pci_determine_mem_io_space(pbm);
1116 pci_get_pbm_props(pbm);
1118 psycho_pbm_strbuf_init(pbm, is_pbm_a);
1121 #define PSYCHO_CONFIGSPACE 0x001000000UL
1123 void psycho_init(struct device_node *dp, char *model_name)
1125 struct linux_prom64_registers *pr_regs;
1126 struct pci_controller_info *p;
1127 struct pci_pbm_info *pbm;
1128 struct iommu *iommu;
1129 struct property *prop;
1134 prop = of_find_property(dp, "upa-portid", NULL);
1136 upa_portid = *(u32 *) prop->value;
1138 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1139 struct pci_controller_info *p = pbm->parent;
1141 if (p->pbm_A.portid == upa_portid) {
1142 is_pbm_a = (p->pbm_A.prom_node == NULL);
1143 psycho_pbm_init(p, dp, is_pbm_a);
1148 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1150 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1153 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1155 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1158 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1160 p->pbm_A.portid = upa_portid;
1161 p->pbm_B.portid = upa_portid;
1163 prop = of_find_property(dp, "reg", NULL);
1164 pr_regs = prop->value;
1166 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1167 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1169 p->pbm_A.config_space = p->pbm_B.config_space =
1170 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1173 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1174 * we need to adjust our MEM space mask.
1176 pci_memspace_mask = 0x7fffffffUL;
1178 psycho_controller_hwinit(&p->pbm_A);
1180 psycho_iommu_init(&p->pbm_A);
1182 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1183 psycho_pbm_init(p, dp, is_pbm_a);