1 /* pci.c: UltraSparc PCI controller support.
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
22 #include <asm/uaccess.h>
23 #include <asm/pgtable.h>
32 unsigned long pci_memspace_mask = 0xffffffffUL;
35 /* A "nop" PCI implementation. */
36 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
37 unsigned long off, unsigned long len,
42 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
43 unsigned long off, unsigned long len,
50 /* List of all PCI controllers found in the system. */
51 struct pci_pbm_info *pci_pbm_root = NULL;
53 /* Each PBM found gets a unique index. */
56 volatile int pci_poke_in_progress;
57 volatile int pci_poke_cpu = -1;
58 volatile int pci_poke_faulted;
60 static DEFINE_SPINLOCK(pci_poke_lock);
62 void pci_config_read8(u8 *addr, u8 *ret)
67 spin_lock_irqsave(&pci_poke_lock, flags);
68 pci_poke_cpu = smp_processor_id();
69 pci_poke_in_progress = 1;
71 __asm__ __volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
75 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
77 pci_poke_in_progress = 0;
79 if (!pci_poke_faulted)
81 spin_unlock_irqrestore(&pci_poke_lock, flags);
84 void pci_config_read16(u16 *addr, u16 *ret)
89 spin_lock_irqsave(&pci_poke_lock, flags);
90 pci_poke_cpu = smp_processor_id();
91 pci_poke_in_progress = 1;
93 __asm__ __volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
97 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
99 pci_poke_in_progress = 0;
101 if (!pci_poke_faulted)
103 spin_unlock_irqrestore(&pci_poke_lock, flags);
106 void pci_config_read32(u32 *addr, u32 *ret)
111 spin_lock_irqsave(&pci_poke_lock, flags);
112 pci_poke_cpu = smp_processor_id();
113 pci_poke_in_progress = 1;
114 pci_poke_faulted = 0;
115 __asm__ __volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
119 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
121 pci_poke_in_progress = 0;
123 if (!pci_poke_faulted)
125 spin_unlock_irqrestore(&pci_poke_lock, flags);
128 void pci_config_write8(u8 *addr, u8 val)
132 spin_lock_irqsave(&pci_poke_lock, flags);
133 pci_poke_cpu = smp_processor_id();
134 pci_poke_in_progress = 1;
135 pci_poke_faulted = 0;
136 __asm__ __volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
140 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 pci_poke_in_progress = 0;
144 spin_unlock_irqrestore(&pci_poke_lock, flags);
147 void pci_config_write16(u16 *addr, u16 val)
151 spin_lock_irqsave(&pci_poke_lock, flags);
152 pci_poke_cpu = smp_processor_id();
153 pci_poke_in_progress = 1;
154 pci_poke_faulted = 0;
155 __asm__ __volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
159 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 pci_poke_in_progress = 0;
163 spin_unlock_irqrestore(&pci_poke_lock, flags);
166 void pci_config_write32(u32 *addr, u32 val)
170 spin_lock_irqsave(&pci_poke_lock, flags);
171 pci_poke_cpu = smp_processor_id();
172 pci_poke_in_progress = 1;
173 pci_poke_faulted = 0;
174 __asm__ __volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
178 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
180 pci_poke_in_progress = 0;
182 spin_unlock_irqrestore(&pci_poke_lock, flags);
185 /* Probe for all PCI controllers in the system. */
186 extern void sabre_init(struct device_node *, const char *);
187 extern void psycho_init(struct device_node *, const char *);
188 extern void schizo_init(struct device_node *, const char *);
189 extern void schizo_plus_init(struct device_node *, const char *);
190 extern void tomatillo_init(struct device_node *, const char *);
191 extern void sun4v_pci_init(struct device_node *, const char *);
192 extern void fire_pci_init(struct device_node *, const char *);
196 void (*init)(struct device_node *, const char *);
197 } pci_controller_table[] __initdata = {
198 { "SUNW,sabre", sabre_init },
199 { "pci108e,a000", sabre_init },
200 { "pci108e,a001", sabre_init },
201 { "SUNW,psycho", psycho_init },
202 { "pci108e,8000", psycho_init },
203 { "SUNW,schizo", schizo_init },
204 { "pci108e,8001", schizo_init },
205 { "SUNW,schizo+", schizo_plus_init },
206 { "pci108e,8002", schizo_plus_init },
207 { "SUNW,tomatillo", tomatillo_init },
208 { "pci108e,a801", tomatillo_init },
209 { "SUNW,sun4v-pci", sun4v_pci_init },
210 { "pciex108e,80f0", fire_pci_init },
212 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
213 sizeof(pci_controller_table[0]))
215 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
219 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
220 if (!strncmp(model_name,
221 pci_controller_table[i].model_name,
223 pci_controller_table[i].init(dp, model_name);
231 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
235 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
236 if (!strncmp(model_name,
237 pci_controller_table[i].model_name,
245 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
247 struct device_node *dp;
250 for_each_node_by_name(dp, "pci") {
251 struct property *prop;
254 prop = of_find_property(dp, "model", &len);
256 prop = of_find_property(dp, "compatible", &len);
259 const char *model = prop->value;
262 /* Our value may be a multi-valued string in the
263 * case of some compatible properties. For sanity,
264 * only try the first one.
266 while (model[item_len] && len) {
271 if (handler(model, item_len, dp))
280 /* Is there some PCI controller in the system? */
281 int __init pcic_present(void)
283 return pci_controller_scan(pci_is_controller);
286 const struct pci_iommu_ops *pci_iommu_ops;
287 EXPORT_SYMBOL(pci_iommu_ops);
289 extern const struct pci_iommu_ops pci_sun4u_iommu_ops,
292 /* Find each controller in the system, attach and initialize
293 * software state structure for each and link into the
294 * pci_pbm_root. Setup the controller enough such
295 * that bus scanning can be done.
297 static void __init pci_controller_probe(void)
299 if (tlb_type == hypervisor)
300 pci_iommu_ops = &pci_sun4v_iommu_ops;
302 pci_iommu_ops = &pci_sun4u_iommu_ops;
304 printk("PCI: Probing for controllers.\n");
306 pci_controller_scan(pci_controller_init);
309 static int ofpci_verbose;
311 static int __init ofpci_debug(char *str)
315 get_option(&str, &val);
321 __setup("ofpci_debug=", ofpci_debug);
323 static unsigned long pci_parse_of_flags(u32 addr0)
325 unsigned long flags = 0;
327 if (addr0 & 0x02000000) {
328 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
329 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
330 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
331 if (addr0 & 0x40000000)
332 flags |= IORESOURCE_PREFETCH
333 | PCI_BASE_ADDRESS_MEM_PREFETCH;
334 } else if (addr0 & 0x01000000)
335 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
339 /* The of_device layer has translated all of the assigned-address properties
340 * into physical address resources, we only have to figure out the register
343 static void pci_parse_of_addrs(struct of_device *op,
344 struct device_node *node,
347 struct resource *op_res;
351 addrs = of_get_property(node, "assigned-addresses", &proplen);
355 printk(" parse addresses (%d bytes) @ %p\n",
357 op_res = &op->resource[0];
358 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
359 struct resource *res;
363 flags = pci_parse_of_flags(addrs[0]);
368 printk(" start: %lx, end: %lx, i: %x\n",
369 op_res->start, op_res->end, i);
371 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
372 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
373 } else if (i == dev->rom_base_reg) {
374 res = &dev->resource[PCI_ROM_RESOURCE];
375 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
377 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
380 res->start = op_res->start;
381 res->end = op_res->end;
383 res->name = pci_name(dev);
387 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
388 struct device_node *node,
389 struct pci_bus *bus, int devfn,
392 struct dev_archdata *sd;
397 dev = alloc_pci_dev();
401 sd = &dev->dev.archdata;
402 sd->iommu = pbm->iommu;
404 sd->host_controller = pbm;
405 sd->prom_node = node;
406 sd->op = of_find_device_by_node(node);
407 sd->msi_num = 0xffffffff;
409 type = of_get_property(node, "device_type", NULL);
414 printk(" create device, devfn: %x, type: %s\n",
419 dev->dev.parent = bus->bridge;
420 dev->dev.bus = &pci_bus_type;
422 dev->multifunction = 0; /* maybe a lie? */
424 if (host_controller) {
425 if (tlb_type != hypervisor) {
426 pci_read_config_word(dev, PCI_VENDOR_ID,
428 pci_read_config_word(dev, PCI_DEVICE_ID,
431 dev->vendor = PCI_VENDOR_ID_SUN;
432 dev->device = 0x80f0;
435 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
436 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
437 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
439 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
440 dev->device = of_getintprop_default(node, "device-id", 0xffff);
441 dev->subsystem_vendor =
442 of_getintprop_default(node, "subsystem-vendor-id", 0);
443 dev->subsystem_device =
444 of_getintprop_default(node, "subsystem-id", 0);
446 dev->cfg_size = pci_cfg_space_size(dev);
448 /* We can't actually use the firmware value, we have
449 * to read what is in the register right now. One
450 * reason is that in the case of IDE interfaces the
451 * firmware can sample the value before the the IDE
452 * interface is programmed into native mode.
454 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
455 dev->class = class >> 8;
456 dev->revision = class & 0xff;
458 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
459 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
462 printk(" class: 0x%x device name: %s\n",
463 dev->class, pci_name(dev));
465 /* I have seen IDE devices which will not respond to
466 * the bmdma simplex check reads if bus mastering is
469 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
472 dev->current_state = 4; /* unknown power state */
473 dev->error_state = pci_channel_io_normal;
475 if (host_controller) {
476 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
477 dev->rom_base_reg = PCI_ROM_ADDRESS1;
478 dev->irq = PCI_IRQ_NONE;
480 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
481 /* a PCI-PCI bridge */
482 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
483 dev->rom_base_reg = PCI_ROM_ADDRESS1;
484 } else if (!strcmp(type, "cardbus")) {
485 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
487 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
488 dev->rom_base_reg = PCI_ROM_ADDRESS;
490 dev->irq = sd->op->irqs[0];
491 if (dev->irq == 0xffffffff)
492 dev->irq = PCI_IRQ_NONE;
495 pci_parse_of_addrs(sd->op, node, dev);
498 printk(" adding to system ...\n");
500 pci_device_add(dev, bus);
505 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
507 u32 idx, first, last;
511 for (idx = 0; idx < 8; idx++) {
512 if ((map & (1 << idx)) != 0) {
524 static void pci_resource_adjust(struct resource *res,
525 struct resource *root)
527 res->start += root->start;
528 res->end += root->start;
531 /* For PCI bus devices which lack a 'ranges' property we interrogate
532 * the config space values to set the resources, just like the generic
533 * Linux PCI probing code does.
535 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
537 struct pci_pbm_info *pbm)
539 struct resource *res;
540 u8 io_base_lo, io_limit_lo;
541 u16 mem_base_lo, mem_limit_lo;
542 unsigned long base, limit;
544 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
545 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
546 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
547 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
549 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
550 u16 io_base_hi, io_limit_hi;
552 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
553 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
554 base |= (io_base_hi << 16);
555 limit |= (io_limit_hi << 16);
558 res = bus->resource[0];
560 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
564 res->end = limit + 0xfff;
565 pci_resource_adjust(res, &pbm->io_space);
568 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
569 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
570 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
571 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
573 res = bus->resource[1];
575 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
578 res->end = limit + 0xfffff;
579 pci_resource_adjust(res, &pbm->mem_space);
582 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
583 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
584 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
585 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
587 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
588 u32 mem_base_hi, mem_limit_hi;
590 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
591 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
594 * Some bridges set the base > limit by default, and some
595 * (broken) BIOSes do not initialize them. If we find
596 * this, just assume they are not being used.
598 if (mem_base_hi <= mem_limit_hi) {
599 base |= ((long) mem_base_hi) << 32;
600 limit |= ((long) mem_limit_hi) << 32;
604 res = bus->resource[2];
606 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
607 IORESOURCE_MEM | IORESOURCE_PREFETCH);
609 res->end = limit + 0xfffff;
610 pci_resource_adjust(res, &pbm->mem_space);
614 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
615 * a proper 'ranges' property.
617 static void __devinit apb_fake_ranges(struct pci_dev *dev,
619 struct pci_pbm_info *pbm)
621 struct resource *res;
625 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
626 apb_calc_first_last(map, &first, &last);
627 res = bus->resource[0];
628 res->start = (first << 21);
629 res->end = (last << 21) + ((1 << 21) - 1);
630 res->flags = IORESOURCE_IO;
631 pci_resource_adjust(res, &pbm->io_space);
633 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
634 apb_calc_first_last(map, &first, &last);
635 res = bus->resource[1];
636 res->start = (first << 21);
637 res->end = (last << 21) + ((1 << 21) - 1);
638 res->flags = IORESOURCE_MEM;
639 pci_resource_adjust(res, &pbm->mem_space);
642 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
643 struct device_node *node,
644 struct pci_bus *bus);
646 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
648 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
649 struct device_node *node,
653 const u32 *busrange, *ranges;
655 struct resource *res;
660 printk("of_scan_pci_bridge(%s)\n", node->full_name);
662 /* parse bus-range property */
663 busrange = of_get_property(node, "bus-range", &len);
664 if (busrange == NULL || len != 8) {
665 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
669 ranges = of_get_property(node, "ranges", &len);
671 if (ranges == NULL) {
672 const char *model = of_get_property(node, "model", NULL);
673 if (model && !strcmp(model, "SUNW,simba"))
677 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
679 printk(KERN_ERR "Failed to create pci bus for %s\n",
684 bus->primary = dev->bus->number;
685 bus->subordinate = busrange[1];
688 /* parse ranges property, or cook one up by hand for Simba */
689 /* PCI #address-cells == 3 and #size-cells == 2 always */
690 res = &dev->resource[PCI_BRIDGE_RESOURCES];
691 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
693 bus->resource[i] = res;
697 apb_fake_ranges(dev, bus, pbm);
699 } else if (ranges == NULL) {
700 pci_cfg_fake_ranges(dev, bus, pbm);
704 for (; len >= 32; len -= 32, ranges += 8) {
705 struct resource *root;
707 flags = pci_parse_of_flags(ranges[0]);
708 size = GET_64BIT(ranges, 6);
709 if (flags == 0 || size == 0)
711 if (flags & IORESOURCE_IO) {
712 res = bus->resource[0];
714 printk(KERN_ERR "PCI: ignoring extra I/O range"
715 " for bridge %s\n", node->full_name);
718 root = &pbm->io_space;
720 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
721 printk(KERN_ERR "PCI: too many memory ranges"
722 " for bridge %s\n", node->full_name);
725 res = bus->resource[i];
727 root = &pbm->mem_space;
730 res->start = GET_64BIT(ranges, 1);
731 res->end = res->start + size - 1;
734 /* Another way to implement this would be to add an of_device
735 * layer routine that can calculate a resource for a given
736 * range property value in a PCI device.
738 pci_resource_adjust(res, root);
741 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
744 printk(" bus name: %s\n", bus->name);
746 pci_of_scan_bus(pbm, node, bus);
749 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
750 struct device_node *node,
753 struct device_node *child;
759 printk("PCI: scan_bus[%s] bus no %d\n",
760 node->full_name, bus->number);
763 while ((child = of_get_next_child(node, child)) != NULL) {
765 printk(" * %s\n", child->full_name);
766 reg = of_get_property(child, "reg", ®len);
767 if (reg == NULL || reglen < 20)
769 devfn = (reg[0] >> 8) & 0xff;
771 /* create a new pci_dev for this device */
772 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
776 printk("PCI: dev header type: %x\n",
779 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
780 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
781 of_scan_pci_bridge(pbm, child, dev);
786 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
788 struct pci_dev *pdev;
789 struct device_node *dp;
791 pdev = to_pci_dev(dev);
792 dp = pdev->dev.archdata.prom_node;
794 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
797 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
799 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
802 struct pci_bus *child_bus;
805 list_for_each_entry(dev, &bus->devices, bus_list) {
806 /* we don't really care if we can create this file or
807 * not, but we need to assign the result of the call
808 * or the world will fall under alien invasion and
809 * everybody will be frozen on a spaceship ready to be
810 * eaten on alpha centauri by some green and jelly
813 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
815 list_for_each_entry(child_bus, &bus->children, node)
816 pci_bus_register_of_sysfs(child_bus);
819 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
824 static u8 fake_pci_config[] = {
825 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
826 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
827 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
828 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
829 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
830 0x00, /* Cacheline: 0x00 */
831 0x40, /* Latency: 0x40 */
832 0x00, /* Header-Type: 0x00 normal */
836 if (where >= 0 && where < sizeof(fake_pci_config) &&
837 (where + size) >= 0 &&
838 (where + size) < sizeof(fake_pci_config) &&
839 size <= sizeof(u32)) {
842 *value |= fake_pci_config[where + size];
846 return PCIBIOS_SUCCESSFUL;
849 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
854 return PCIBIOS_SUCCESSFUL;
857 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
859 struct device_node *node = pbm->prom_node;
860 struct pci_dev *host_pdev;
863 printk("PCI: Scanning PBM %s\n", node->full_name);
865 /* XXX parent device? XXX */
866 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
868 printk(KERN_ERR "Failed to create bus for %s\n",
872 bus->secondary = pbm->pci_first_busno;
873 bus->subordinate = pbm->pci_last_busno;
875 bus->resource[0] = &pbm->io_space;
876 bus->resource[1] = &pbm->mem_space;
878 /* Create the dummy host bridge and link it in. */
879 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
880 bus->self = host_pdev;
882 pci_of_scan_bus(pbm, node, bus);
883 pci_bus_add_devices(bus);
884 pci_bus_register_of_sysfs(bus);
889 static void __init pci_scan_each_controller_bus(void)
891 struct pci_pbm_info *pbm;
893 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
897 extern void power_init(void);
899 static int __init pcibios_init(void)
901 pci_controller_probe();
902 if (pci_pbm_root == NULL)
905 pci_scan_each_controller_bus();
914 subsys_initcall(pcibios_init);
916 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
918 struct pci_pbm_info *pbm = pbus->sysdata;
920 /* Generic PCI bus probing sets these to point at
921 * &io{port,mem}_resouce which is wrong for us.
923 pbus->resource[0] = &pbm->io_space;
924 pbus->resource[1] = &pbm->mem_space;
927 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
929 struct pci_pbm_info *pbm = pdev->bus->sysdata;
930 struct resource *root = NULL;
932 if (r->flags & IORESOURCE_IO)
933 root = &pbm->io_space;
934 if (r->flags & IORESOURCE_MEM)
935 root = &pbm->mem_space;
940 void pcibios_update_irq(struct pci_dev *pdev, int irq)
944 void pcibios_align_resource(void *data, struct resource *res,
945 resource_size_t size, resource_size_t align)
949 int pcibios_enable_device(struct pci_dev *dev, int mask)
954 pci_read_config_word(dev, PCI_COMMAND, &cmd);
957 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
958 struct resource *res = &dev->resource[i];
960 /* Only set up the requested stuff */
961 if (!(mask & (1<<i)))
964 if (res->flags & IORESOURCE_IO)
965 cmd |= PCI_COMMAND_IO;
966 if (res->flags & IORESOURCE_MEM)
967 cmd |= PCI_COMMAND_MEMORY;
971 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
973 /* Enable the appropriate bits in the PCI command register. */
974 pci_write_config_word(dev, PCI_COMMAND, cmd);
979 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
980 struct resource *res)
982 struct pci_pbm_info *pbm = pdev->bus->sysdata;
983 struct resource zero_res, *root;
987 zero_res.flags = res->flags;
989 if (res->flags & IORESOURCE_IO)
990 root = &pbm->io_space;
992 root = &pbm->mem_space;
994 pci_resource_adjust(&zero_res, root);
996 region->start = res->start - zero_res.start;
997 region->end = res->end - zero_res.start;
999 EXPORT_SYMBOL(pcibios_resource_to_bus);
1001 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
1002 struct pci_bus_region *region)
1004 struct pci_pbm_info *pbm = pdev->bus->sysdata;
1005 struct resource *root;
1007 res->start = region->start;
1008 res->end = region->end;
1010 if (res->flags & IORESOURCE_IO)
1011 root = &pbm->io_space;
1013 root = &pbm->mem_space;
1015 pci_resource_adjust(res, root);
1017 EXPORT_SYMBOL(pcibios_bus_to_resource);
1019 char * __devinit pcibios_setup(char *str)
1024 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
1026 /* If the user uses a host-bridge as the PCI device, he may use
1027 * this to perform a raw mmap() of the I/O or MEM space behind
1030 * This can be useful for execution of x86 PCI bios initialization code
1031 * on a PCI card, like the xfree86 int10 stuff does.
1033 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1034 enum pci_mmap_state mmap_state)
1036 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1037 unsigned long space_size, user_offset, user_size;
1039 if (mmap_state == pci_mmap_io) {
1040 space_size = (pbm->io_space.end -
1041 pbm->io_space.start) + 1;
1043 space_size = (pbm->mem_space.end -
1044 pbm->mem_space.start) + 1;
1047 /* Make sure the request is in range. */
1048 user_offset = vma->vm_pgoff << PAGE_SHIFT;
1049 user_size = vma->vm_end - vma->vm_start;
1051 if (user_offset >= space_size ||
1052 (user_offset + user_size) > space_size)
1055 if (mmap_state == pci_mmap_io) {
1056 vma->vm_pgoff = (pbm->io_space.start +
1057 user_offset) >> PAGE_SHIFT;
1059 vma->vm_pgoff = (pbm->mem_space.start +
1060 user_offset) >> PAGE_SHIFT;
1066 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
1067 * to the 32-bit pci bus offset for DEV requested by the user.
1069 * Basically, the user finds the base address for his device which he wishes
1070 * to mmap. They read the 32-bit value from the config space base register,
1071 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1072 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1074 * Returns negative error code on failure, zero on success.
1076 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1077 enum pci_mmap_state mmap_state)
1079 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
1080 unsigned long user32 = user_offset & pci_memspace_mask;
1081 unsigned long largest_base, this_base, addr32;
1084 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1085 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
1087 /* Figure out which base address this is for. */
1089 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1090 struct resource *rp = &dev->resource[i];
1097 if (i == PCI_ROM_RESOURCE) {
1098 if (mmap_state != pci_mmap_mem)
1101 if ((mmap_state == pci_mmap_io &&
1102 (rp->flags & IORESOURCE_IO) == 0) ||
1103 (mmap_state == pci_mmap_mem &&
1104 (rp->flags & IORESOURCE_MEM) == 0))
1108 this_base = rp->start;
1110 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
1112 if (mmap_state == pci_mmap_io)
1115 if (addr32 <= user32 && this_base > largest_base)
1116 largest_base = this_base;
1119 if (largest_base == 0UL)
1122 /* Now construct the final physical address. */
1123 if (mmap_state == pci_mmap_io)
1124 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1126 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1131 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1134 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1135 enum pci_mmap_state mmap_state)
1137 vma->vm_flags |= (VM_IO | VM_RESERVED);
1140 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1143 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1144 enum pci_mmap_state mmap_state)
1146 /* Our io_remap_pfn_range takes care of this, do nothing. */
1149 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1150 * for this architecture. The region in the process to map is described by vm_start
1151 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1152 * The pci device structure is provided so that architectures may make mapping
1153 * decisions on a per-device or per-bus basis.
1155 * Returns a negative error code on failure, zero on success.
1157 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1158 enum pci_mmap_state mmap_state,
1163 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1167 __pci_mmap_set_flags(dev, vma, mmap_state);
1168 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1170 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1171 ret = io_remap_pfn_range(vma, vma->vm_start,
1173 vma->vm_end - vma->vm_start,
1181 /* Return the domain nuber for this pci bus */
1183 int pci_domain_nr(struct pci_bus *pbus)
1185 struct pci_pbm_info *pbm = pbus->sysdata;
1188 if (pbm == NULL || pbm->parent == NULL) {
1196 EXPORT_SYMBOL(pci_domain_nr);
1198 #ifdef CONFIG_PCI_MSI
1199 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1201 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1204 if (!pbm->setup_msi_irq)
1207 return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1210 void arch_teardown_msi_irq(unsigned int virt_irq)
1212 struct msi_desc *entry = get_irq_msi(virt_irq);
1213 struct pci_dev *pdev = entry->dev;
1214 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1216 if (!pbm->teardown_msi_irq)
1219 return pbm->teardown_msi_irq(virt_irq, pdev);
1221 #endif /* !(CONFIG_PCI_MSI) */
1223 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1225 return pdev->dev.archdata.prom_node;
1227 EXPORT_SYMBOL(pci_device_to_OF_node);
1229 #endif /* !(CONFIG_PCI) */