1 /* irq.c: UltraSparc IRQ handling/init/registry.
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/module.h>
9 #include <linux/sched.h>
10 #include <linux/ptrace.h>
11 #include <linux/errno.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/signal.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/random.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/proc_fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/bootmem.h>
23 #include <linux/irq.h>
24 #include <linux/msi.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
33 #include <asm/iommu.h>
35 #include <asm/oplib.h>
37 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/uaccess.h>
41 #include <asm/cache.h>
42 #include <asm/cpudata.h>
43 #include <asm/auxio.h>
45 #include <asm/hypervisor.h>
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 * The IVEC handler does not need to act atomically, the PIL dispatch
56 * code uses CAS to get an atomic snapshot of the list and clear it
59 * If you make changes to ino_bucket, please update hand coded assembler
60 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
63 /* Next handler in per-CPU IRQ worklist. We know that
64 * bucket pointers have the high 32-bits clear, so to
65 * save space we only store the bits we need.
67 /*0x00*/unsigned int irq_chain;
69 /* Virtual interrupt number assigned to this INO. */
70 /*0x04*/unsigned int virt_irq;
73 #define NUM_IVECS (IMAP_INR + 1)
74 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
76 #define __irq_ino(irq) \
77 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
78 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
79 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
81 /* This has to be in the main kernel image, it cannot be
82 * turned into per-cpu data. The reason is that the main
83 * kernel image is locked into the TLB and this structure
84 * is accessed from the vectored interrupt trap handler. If
85 * access to this structure takes a TLB miss it could cause
86 * the 5-level sparc v9 trap stack to overflow.
88 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
92 unsigned int dev_handle;
94 } virt_to_real_irq_table[NR_IRQS];
96 static unsigned char virt_irq_alloc(unsigned int real_irq)
100 BUILD_BUG_ON(NR_IRQS >= 256);
102 for (ent = 1; ent < NR_IRQS; ent++) {
103 if (!virt_to_real_irq_table[ent].irq)
106 if (ent >= NR_IRQS) {
107 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
111 virt_to_real_irq_table[ent].irq = real_irq;
116 #ifdef CONFIG_PCI_MSI
117 static void virt_irq_free(unsigned int virt_irq)
119 unsigned int real_irq;
121 if (virt_irq >= NR_IRQS)
124 real_irq = virt_to_real_irq_table[virt_irq].irq;
125 virt_to_real_irq_table[virt_irq].irq = 0;
127 __bucket(real_irq)->virt_irq = 0;
131 static unsigned int virt_to_real_irq(unsigned char virt_irq)
133 return virt_to_real_irq_table[virt_irq].irq;
137 * /proc/interrupts printing:
140 int show_interrupts(struct seq_file *p, void *v)
142 int i = *(loff_t *) v, j;
143 struct irqaction * action;
148 for_each_online_cpu(j)
149 seq_printf(p, "CPU%d ",j);
154 spin_lock_irqsave(&irq_desc[i].lock, flags);
155 action = irq_desc[i].action;
158 seq_printf(p, "%3d: ",i);
160 seq_printf(p, "%10u ", kstat_irqs(i));
162 for_each_online_cpu(j)
163 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
165 seq_printf(p, " %9s", irq_desc[i].chip->typename);
166 seq_printf(p, " %s", action->name);
168 for (action=action->next; action; action = action->next)
169 seq_printf(p, ", %s", action->name);
173 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
178 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
182 if (this_is_starfire) {
183 tid = starfire_translate(imap, cpuid);
184 tid <<= IMAP_TID_SHIFT;
187 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
190 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
191 if ((ver >> 32UL) == __JALAPENO_ID ||
192 (ver >> 32UL) == __SERRANO_ID) {
193 tid = cpuid << IMAP_TID_SHIFT;
194 tid &= IMAP_TID_JBUS;
196 unsigned int a = cpuid & 0x1f;
197 unsigned int n = (cpuid >> 5) & 0x1f;
199 tid = ((a << IMAP_AID_SHIFT) |
200 (n << IMAP_NID_SHIFT));
201 tid &= (IMAP_AID_SAFARI |
205 tid = cpuid << IMAP_TID_SHIFT;
213 struct irq_handler_data {
217 void (*pre_handler)(unsigned int, void *, void *);
218 void *pre_handler_arg1;
219 void *pre_handler_arg2;
224 void sparc64_set_msi(unsigned int virt_irq, u32 msi)
226 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
232 u32 sparc64_get_msi(unsigned int virt_irq)
234 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
241 static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
243 unsigned int real_irq = virt_to_real_irq(virt_irq);
244 struct ino_bucket *bucket = NULL;
246 if (likely(real_irq))
247 bucket = __bucket(real_irq);
253 static int irq_choose_cpu(unsigned int virt_irq)
255 cpumask_t mask = irq_desc[virt_irq].affinity;
258 if (cpus_equal(mask, CPU_MASK_ALL)) {
259 static int irq_rover;
260 static DEFINE_SPINLOCK(irq_rover_lock);
263 /* Round-robin distribution... */
265 spin_lock_irqsave(&irq_rover_lock, flags);
267 while (!cpu_online(irq_rover)) {
268 if (++irq_rover >= NR_CPUS)
273 if (++irq_rover >= NR_CPUS)
275 } while (!cpu_online(irq_rover));
277 spin_unlock_irqrestore(&irq_rover_lock, flags);
281 cpus_and(tmp, cpu_online_map, mask);
286 cpuid = first_cpu(tmp);
292 static int irq_choose_cpu(unsigned int virt_irq)
294 return real_hard_smp_processor_id();
298 static void sun4u_irq_enable(unsigned int virt_irq)
300 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
303 unsigned long cpuid, imap, val;
306 cpuid = irq_choose_cpu(virt_irq);
309 tid = sun4u_compute_tid(imap, cpuid);
311 val = upa_readq(imap);
312 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
313 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
314 val |= tid | IMAP_VALID;
315 upa_writeq(val, imap);
319 static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask)
321 sun4u_irq_enable(virt_irq);
324 static void sun4u_irq_disable(unsigned int virt_irq)
326 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
329 unsigned long imap = data->imap;
330 unsigned long tmp = upa_readq(imap);
333 upa_writeq(tmp, imap);
337 static void sun4u_irq_end(unsigned int virt_irq)
339 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
340 struct irq_desc *desc = irq_desc + virt_irq;
342 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
346 upa_writeq(ICLR_IDLE, data->iclr);
349 static void sun4v_irq_enable(unsigned int virt_irq)
351 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
352 unsigned int ino = bucket - &ivector_table[0];
354 if (likely(bucket)) {
358 cpuid = irq_choose_cpu(virt_irq);
360 err = sun4v_intr_settarget(ino, cpuid);
362 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
363 "err(%d)\n", ino, cpuid, err);
364 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
366 printk(KERN_ERR "sun4v_intr_setstate(%x): "
367 "err(%d)\n", ino, err);
368 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
370 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
375 static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask)
377 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
378 unsigned int ino = bucket - &ivector_table[0];
380 if (likely(bucket)) {
384 cpuid = irq_choose_cpu(virt_irq);
386 err = sun4v_intr_settarget(ino, cpuid);
388 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
389 "err(%d)\n", ino, cpuid, err);
393 static void sun4v_irq_disable(unsigned int virt_irq)
395 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
396 unsigned int ino = bucket - &ivector_table[0];
398 if (likely(bucket)) {
401 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
403 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
404 "err(%d)\n", ino, err);
408 #ifdef CONFIG_PCI_MSI
409 static void sun4v_msi_enable(unsigned int virt_irq)
411 sun4v_irq_enable(virt_irq);
412 unmask_msi_irq(virt_irq);
415 static void sun4v_msi_disable(unsigned int virt_irq)
417 mask_msi_irq(virt_irq);
418 sun4v_irq_disable(virt_irq);
422 static void sun4v_irq_end(unsigned int virt_irq)
424 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
425 unsigned int ino = bucket - &ivector_table[0];
426 struct irq_desc *desc = irq_desc + virt_irq;
428 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
431 if (likely(bucket)) {
434 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
436 printk(KERN_ERR "sun4v_intr_setstate(%x): "
437 "err(%d)\n", ino, err);
441 static void sun4v_virq_enable(unsigned int virt_irq)
443 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
445 if (likely(bucket)) {
446 unsigned long cpuid, dev_handle, dev_ino;
449 cpuid = irq_choose_cpu(virt_irq);
451 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
452 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
454 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
456 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
458 dev_handle, dev_ino, cpuid, err);
459 err = sun4v_vintr_set_state(dev_handle, dev_ino,
462 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
463 "HV_INTR_STATE_IDLE): err(%d)\n",
464 dev_handle, dev_ino, err);
465 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
468 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
469 "HV_INTR_ENABLED): err(%d)\n",
470 dev_handle, dev_ino, err);
474 static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask)
476 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
478 if (likely(bucket)) {
479 unsigned long cpuid, dev_handle, dev_ino;
482 cpuid = irq_choose_cpu(virt_irq);
484 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
485 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
487 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
489 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
491 dev_handle, dev_ino, cpuid, err);
495 static void sun4v_virq_disable(unsigned int virt_irq)
497 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
499 if (likely(bucket)) {
500 unsigned long dev_handle, dev_ino;
503 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
504 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
506 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
509 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
510 "HV_INTR_DISABLED): err(%d)\n",
511 dev_handle, dev_ino, err);
515 static void sun4v_virq_end(unsigned int virt_irq)
517 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
518 struct irq_desc *desc = irq_desc + virt_irq;
520 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
523 if (likely(bucket)) {
524 unsigned long dev_handle, dev_ino;
527 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
528 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
530 err = sun4v_vintr_set_state(dev_handle, dev_ino,
533 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
534 "HV_INTR_STATE_IDLE): err(%d)\n",
535 dev_handle, dev_ino, err);
539 static void run_pre_handler(unsigned int virt_irq)
541 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
542 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
544 if (likely(data->pre_handler)) {
545 data->pre_handler(__irq_ino(__irq(bucket)),
546 data->pre_handler_arg1,
547 data->pre_handler_arg2);
551 static struct irq_chip sun4u_irq = {
553 .enable = sun4u_irq_enable,
554 .disable = sun4u_irq_disable,
555 .end = sun4u_irq_end,
556 .set_affinity = sun4u_set_affinity,
559 static struct irq_chip sun4u_irq_ack = {
560 .typename = "sun4u+ack",
561 .enable = sun4u_irq_enable,
562 .disable = sun4u_irq_disable,
563 .ack = run_pre_handler,
564 .end = sun4u_irq_end,
565 .set_affinity = sun4u_set_affinity,
568 static struct irq_chip sun4v_irq = {
570 .enable = sun4v_irq_enable,
571 .disable = sun4v_irq_disable,
572 .end = sun4v_irq_end,
573 .set_affinity = sun4v_set_affinity,
576 static struct irq_chip sun4v_irq_ack = {
577 .typename = "sun4v+ack",
578 .enable = sun4v_irq_enable,
579 .disable = sun4v_irq_disable,
580 .ack = run_pre_handler,
581 .end = sun4v_irq_end,
582 .set_affinity = sun4v_set_affinity,
585 #ifdef CONFIG_PCI_MSI
586 static struct irq_chip sun4v_msi = {
587 .typename = "sun4v+msi",
588 .mask = mask_msi_irq,
589 .unmask = unmask_msi_irq,
590 .enable = sun4v_msi_enable,
591 .disable = sun4v_msi_disable,
592 .ack = run_pre_handler,
593 .end = sun4v_irq_end,
594 .set_affinity = sun4v_set_affinity,
598 static struct irq_chip sun4v_virq = {
599 .typename = "vsun4v",
600 .enable = sun4v_virq_enable,
601 .disable = sun4v_virq_disable,
602 .end = sun4v_virq_end,
603 .set_affinity = sun4v_virt_set_affinity,
606 static struct irq_chip sun4v_virq_ack = {
607 .typename = "vsun4v+ack",
608 .enable = sun4v_virq_enable,
609 .disable = sun4v_virq_disable,
610 .ack = run_pre_handler,
611 .end = sun4v_virq_end,
612 .set_affinity = sun4v_virt_set_affinity,
615 void irq_install_pre_handler(int virt_irq,
616 void (*func)(unsigned int, void *, void *),
617 void *arg1, void *arg2)
619 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
620 struct irq_chip *chip;
622 data->pre_handler = func;
623 data->pre_handler_arg1 = arg1;
624 data->pre_handler_arg2 = arg2;
626 chip = get_irq_chip(virt_irq);
627 if (chip == &sun4u_irq_ack ||
628 chip == &sun4v_irq_ack ||
629 chip == &sun4v_virq_ack
630 #ifdef CONFIG_PCI_MSI
631 || chip == &sun4v_msi
636 chip = (chip == &sun4u_irq ?
638 (chip == &sun4v_irq ?
639 &sun4v_irq_ack : &sun4v_virq_ack));
640 set_irq_chip(virt_irq, chip);
643 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
645 struct ino_bucket *bucket;
646 struct irq_handler_data *data;
649 BUG_ON(tlb_type == hypervisor);
651 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
652 bucket = &ivector_table[ino];
653 if (!bucket->virt_irq) {
654 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
655 set_irq_chip(bucket->virt_irq, &sun4u_irq);
658 data = get_irq_chip_data(bucket->virt_irq);
662 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
663 if (unlikely(!data)) {
664 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
667 set_irq_chip_data(bucket->virt_irq, data);
673 return bucket->virt_irq;
676 static unsigned int sun4v_build_common(unsigned long sysino,
677 struct irq_chip *chip)
679 struct ino_bucket *bucket;
680 struct irq_handler_data *data;
682 BUG_ON(tlb_type != hypervisor);
684 bucket = &ivector_table[sysino];
685 if (!bucket->virt_irq) {
686 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
687 set_irq_chip(bucket->virt_irq, chip);
690 data = get_irq_chip_data(bucket->virt_irq);
694 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
695 if (unlikely(!data)) {
696 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
699 set_irq_chip_data(bucket->virt_irq, data);
701 /* Catch accidental accesses to these things. IMAP/ICLR handling
702 * is done by hypervisor calls on sun4v platforms, not by direct
709 return bucket->virt_irq;
712 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
714 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
716 return sun4v_build_common(sysino, &sun4v_irq);
719 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
721 unsigned long sysino, hv_err;
724 BUG_ON(devhandle & devino);
726 sysino = devhandle | devino;
727 BUG_ON(sysino & ~(IMAP_IGN | IMAP_INO));
729 hv_err = sun4v_vintr_set_cookie(devhandle, devino, sysino);
731 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
732 "err=%lu\n", devhandle, devino, hv_err);
736 virq = sun4v_build_common(sysino, &sun4v_virq);
738 virt_to_real_irq_table[virq].dev_handle = devhandle;
739 virt_to_real_irq_table[virq].dev_ino = devino;
744 #ifdef CONFIG_PCI_MSI
745 unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
746 unsigned int msi_start, unsigned int msi_end)
748 struct ino_bucket *bucket;
749 struct irq_handler_data *data;
750 unsigned long sysino;
753 BUG_ON(tlb_type != hypervisor);
755 /* Find a free devino in the given range. */
756 for (devino = msi_start; devino < msi_end; devino++) {
757 sysino = sun4v_devino_to_sysino(devhandle, devino);
758 bucket = &ivector_table[sysino];
759 if (!bucket->virt_irq)
762 if (devino >= msi_end)
765 sysino = sun4v_devino_to_sysino(devhandle, devino);
766 bucket = &ivector_table[sysino];
767 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
768 *virt_irq_p = bucket->virt_irq;
769 set_irq_chip(bucket->virt_irq, &sun4v_msi);
771 data = get_irq_chip_data(bucket->virt_irq);
775 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
776 if (unlikely(!data)) {
777 virt_irq_free(*virt_irq_p);
780 set_irq_chip_data(bucket->virt_irq, data);
788 void sun4v_destroy_msi(unsigned int virt_irq)
790 virt_irq_free(virt_irq);
794 void ack_bad_irq(unsigned int virt_irq)
796 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
797 unsigned int ino = 0xdeadbeef;
800 ino = bucket - &ivector_table[0];
802 printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
806 void handler_irq(int irq, struct pt_regs *regs)
808 struct ino_bucket *bucket;
809 struct pt_regs *old_regs;
811 clear_softint(1 << irq);
813 old_regs = set_irq_regs(regs);
817 bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
819 struct ino_bucket *next = __bucket(bucket->irq_chain);
821 bucket->irq_chain = 0;
822 __do_IRQ(bucket->virt_irq);
828 set_irq_regs(old_regs);
831 #ifdef CONFIG_HOTPLUG_CPU
832 void fixup_irqs(void)
836 for (irq = 0; irq < NR_IRQS; irq++) {
839 spin_lock_irqsave(&irq_desc[irq].lock, flags);
840 if (irq_desc[irq].action &&
841 !(irq_desc[irq].status & IRQ_PER_CPU)) {
842 if (irq_desc[irq].chip->set_affinity)
843 irq_desc[irq].chip->set_affinity(irq,
844 irq_desc[irq].affinity);
846 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
858 static struct sun5_timer *prom_timers;
859 static u64 prom_limit0, prom_limit1;
861 static void map_prom_timers(void)
863 struct device_node *dp;
864 const unsigned int *addr;
866 /* PROM timer node hangs out in the top level of device siblings... */
867 dp = of_find_node_by_path("/");
870 if (!strcmp(dp->name, "counter-timer"))
875 /* Assume if node is not present, PROM uses different tick mechanism
876 * which we should not care about.
879 prom_timers = (struct sun5_timer *) 0;
883 /* If PROM is really using this, it must be mapped by him. */
884 addr = of_get_property(dp, "address", NULL);
886 prom_printf("PROM does not have timer mapped, trying to continue.\n");
887 prom_timers = (struct sun5_timer *) 0;
890 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
893 static void kill_prom_timer(void)
898 /* Save them away for later. */
899 prom_limit0 = prom_timers->limit0;
900 prom_limit1 = prom_timers->limit1;
902 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
903 * We turn both off here just to be paranoid.
905 prom_timers->limit0 = 0;
906 prom_timers->limit1 = 0;
908 /* Wheee, eat the interrupt packet too... */
909 __asm__ __volatile__(
911 " ldxa [%%g0] %0, %%g1\n"
912 " ldxa [%%g2] %1, %%g1\n"
913 " stxa %%g0, [%%g0] %0\n"
916 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
920 void init_irqwork_curcpu(void)
922 int cpu = hard_smp_processor_id();
924 trap_block[cpu].irq_worklist = 0;
927 /* Please be very careful with register_one_mondo() and
928 * sun4v_register_mondo_queues().
930 * On SMP this gets invoked from the CPU trampoline before
931 * the cpu has fully taken over the trap table from OBP,
932 * and it's kernel stack + %g6 thread register state is
933 * not fully cooked yet.
935 * Therefore you cannot make any OBP calls, not even prom_printf,
936 * from these two routines.
938 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
940 unsigned long num_entries = (qmask + 1) / 64;
941 unsigned long status;
943 status = sun4v_cpu_qconf(type, paddr, num_entries);
944 if (status != HV_EOK) {
945 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
946 "err %lu\n", type, paddr, num_entries, status);
951 void __cpuinit sun4v_register_mondo_queues(int this_cpu)
953 struct trap_per_cpu *tb = &trap_block[this_cpu];
955 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
956 tb->cpu_mondo_qmask);
957 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
958 tb->dev_mondo_qmask);
959 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
961 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
965 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
967 unsigned long size = PAGE_ALIGN(qmask + 1);
968 void *p = __alloc_bootmem_low(size, size, 0);
970 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
977 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
979 unsigned long size = PAGE_ALIGN(qmask + 1);
980 void *p = __alloc_bootmem_low(size, size, 0);
983 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
990 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
995 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
997 page = alloc_bootmem_low_pages(PAGE_SIZE);
999 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1003 tb->cpu_mondo_block_pa = __pa(page);
1004 tb->cpu_list_pa = __pa(page + 64);
1008 /* Allocate mondo and error queues for all possible cpus. */
1009 static void __init sun4v_init_mondo_queues(void)
1013 for_each_possible_cpu(cpu) {
1014 struct trap_per_cpu *tb = &trap_block[cpu];
1016 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
1017 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
1018 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
1019 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
1020 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
1021 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
1022 tb->nonresum_qmask);
1024 init_cpu_send_mondo_info(tb);
1027 /* Load up the boot cpu's entries. */
1028 sun4v_register_mondo_queues(hard_smp_processor_id());
1031 static struct irqaction timer_irq_action = {
1035 /* Only invoked on boot processor. */
1036 void __init init_IRQ(void)
1040 memset(&ivector_table[0], 0, sizeof(ivector_table));
1042 if (tlb_type == hypervisor)
1043 sun4v_init_mondo_queues();
1045 /* We need to clear any IRQ's pending in the soft interrupt
1046 * registers, a spurious one could be left around from the
1047 * PROM timer which we just disabled.
1049 clear_softint(get_softint());
1051 /* Now that ivector table is initialized, it is safe
1052 * to receive IRQ vector traps. We will normally take
1053 * one or two right now, in case some device PROM used
1054 * to boot us wants to speak to us. We just ignore them.
1056 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
1057 "or %%g1, %0, %%g1\n\t"
1058 "wrpr %%g1, 0x0, %%pstate"
1063 irq_desc[0].action = &timer_irq_action;