1 /* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/config.h>
11 #include <asm/pstate.h>
12 #include <asm/ptrace.h>
14 #include <asm/spitfire.h>
16 #include <asm/processor.h>
19 #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
20 #define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
21 #define ETRAP_PSTATE2 \
22 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
25 * On entry, %g7 is return address - 0x4.
26 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
31 .globl etrap, etrap_irq, etraptl1
37 andcc %g1, TSTATE_PRIV, %g0
40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
41 wrpr %g0, 7, %cleanwin
43 sethi %hi(TASK_REGOFF), %g2
44 sethi %hi(TSTATE_PEF), %g3
45 or %g2, %lo(TASK_REGOFF), %g2
52 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
54 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
57 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
58 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
62 mov PRIMARY_CONTEXT, %l4
65 wrpr %g0, 0, %canrestore
68 stb %l5, [%l6 + TI_FPDEPTH]
70 wrpr %g3, 0, %otherwin
72 sethi %hi(sparc64_kern_pri_context), %g2
73 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
74 stxa %g3, [%l4] ASI_DMMU
75 sethi %hi(KERNBASE), %l4
77 wr %g0, ASI_AIUS, %asi
83 wrpr %g0, ETRAP_PSTATE1, %pstate
84 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
85 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
86 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
87 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
88 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
89 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
91 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
92 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
93 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
94 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
95 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
96 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
97 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
99 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
100 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
101 wrpr %g0, ETRAP_PSTATE2, %pstate
103 LOAD_PER_CPU_BASE(%g4, %g3, %l1)
105 ldx [%g6 + TI_TASK], %g4
107 3: ldub [%l6 + TI_FPDEPTH], %l5
108 add %l6, TI_FPSAVED + 1, %l4
111 stb %l5, [%l6 + TI_FPDEPTH]
116 etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
117 * We place this right after pt_regs on the trap stack.
128 sub %sp, ((4 * 8) * 4) + 8, %g2
133 stx %g3, [%g2 + STACK_BIAS + 0x00]
135 stx %g3, [%g2 + STACK_BIAS + 0x08]
137 stx %g3, [%g2 + STACK_BIAS + 0x10]
139 stx %g3, [%g2 + STACK_BIAS + 0x18]
143 stx %g3, [%g2 + STACK_BIAS + 0x20]
145 stx %g3, [%g2 + STACK_BIAS + 0x28]
147 stx %g3, [%g2 + STACK_BIAS + 0x30]
149 stx %g3, [%g2 + STACK_BIAS + 0x38]
153 stx %g3, [%g2 + STACK_BIAS + 0x40]
155 stx %g3, [%g2 + STACK_BIAS + 0x48]
157 stx %g3, [%g2 + STACK_BIAS + 0x50]
159 stx %g3, [%g2 + STACK_BIAS + 0x58]
163 stx %g3, [%g2 + STACK_BIAS + 0x60]
165 stx %g3, [%g2 + STACK_BIAS + 0x68]
167 stx %g3, [%g2 + STACK_BIAS + 0x70]
169 stx %g3, [%g2 + STACK_BIAS + 0x78]
172 stx %g1, [%g2 + STACK_BIAS + 0x80]
175 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
177 andcc %g1, TSTATE_PRIV, %g0
186 andcc %g1, TSTATE_PRIV, %g0
189 sub %sp, (STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS), %g2
190 wrpr %g0, 7, %cleanwin
193 sethi %hi(TASK_REGOFF), %g2
194 or %g2, %lo(TASK_REGOFF), %g2
199 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
202 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
203 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
204 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
208 rdpr %canrestore, %g3
211 wrpr %g0, 0, %canrestore
213 mov PRIMARY_CONTEXT, %l4
214 wrpr %g3, 0, %otherwin
216 sethi %hi(sparc64_kern_pri_context), %g2
217 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
218 stxa %g3, [%l4] ASI_DMMU
219 sethi %hi(KERNBASE), %l4
226 wrpr %g0, ETRAP_PSTATE1, %pstate
227 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
228 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
231 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
233 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
234 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
235 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
236 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
238 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
242 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
243 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
244 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
245 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
246 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
247 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
249 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
250 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
252 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
253 LOAD_PER_CPU_BASE(%g4, %g3, %l1)
254 ldx [%g6 + TI_TASK], %g4