2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * arch/sh64/mach-cayman/setup.c
10 * This file handles the architecture-dependent parts of initialization
12 * Copyright David J. Mckay.
15 * benedict.gaster@superh.com: 3rd May 2002
16 * Added support for ramdisk, removing statically linked romfs at the same time.
18 * lethal@linux-sh.org: 15th May 2003
19 * Use the generic procfs cpuinfo interface, just return a valid board name.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <asm/platform.h>
27 * Platform Dependent Interrupt Priorities.
30 /* Using defaults defined in irq.h */
31 #define RES NO_PRIORITY /* Disabled */
32 #define IR0 IRL0_PRIORITY /* IRLs */
33 #define IR1 IRL1_PRIORITY
34 #define IR2 IRL2_PRIORITY
35 #define IR3 IRL3_PRIORITY
36 #define PCA INTA_PRIORITY /* PCI Ints */
37 #define PCB INTB_PRIORITY
38 #define PCC INTC_PRIORITY
39 #define PCD INTD_PRIORITY
40 #define SER TOP_PRIORITY
41 #define ERR TOP_PRIORITY
42 #define PW0 TOP_PRIORITY
43 #define PW1 TOP_PRIORITY
44 #define PW2 TOP_PRIORITY
45 #define PW3 TOP_PRIORITY
46 #define DM0 NO_PRIORITY /* DMA Ints */
47 #define DM1 NO_PRIORITY
48 #define DM2 NO_PRIORITY
49 #define DM3 NO_PRIORITY
50 #define DAE NO_PRIORITY
51 #define TU0 TIMER_PRIORITY /* TMU Ints */
52 #define TU1 NO_PRIORITY
53 #define TU2 NO_PRIORITY
54 #define TI2 NO_PRIORITY
55 #define ATI NO_PRIORITY /* RTC Ints */
56 #define PRI NO_PRIORITY
57 #define CUI RTC_PRIORITY
58 #define ERI SCIF_PRIORITY /* SCIF Ints */
59 #define RXI SCIF_PRIORITY
60 #define BRI SCIF_PRIORITY
61 #define TXI SCIF_PRIORITY
62 #define ITI TOP_PRIORITY /* WDT Ints */
64 /* Setup for the SMSC FDC37C935 */
65 #define SMSC_SUPERIO_BASE 0x04000000
66 #define SMSC_CONFIG_PORT_ADDR 0x3f0
67 #define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
68 #define SMSC_DATA_PORT_ADDR 0x3f1
70 #define SMSC_ENTER_CONFIG_KEY 0x55
71 #define SMSC_EXIT_CONFIG_KEY 0xaa
73 #define SMCS_LOGICAL_DEV_INDEX 0x07
74 #define SMSC_DEVICE_ID_INDEX 0x20
75 #define SMSC_DEVICE_REV_INDEX 0x21
76 #define SMSC_ACTIVATE_INDEX 0x30
77 #define SMSC_PRIMARY_BASE_INDEX 0x60
78 #define SMSC_SECONDARY_BASE_INDEX 0x62
79 #define SMSC_PRIMARY_INT_INDEX 0x70
80 #define SMSC_SECONDARY_INT_INDEX 0x72
82 #define SMSC_IDE1_DEVICE 1
83 #define SMSC_KEYBOARD_DEVICE 7
84 #define SMSC_CONFIG_REGISTERS 8
86 #define SMSC_SUPERIO_READ_INDEXED(index) ({ \
87 outb((index), SMSC_INDEX_PORT_ADDR); \
88 inb(SMSC_DATA_PORT_ADDR); })
89 #define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \
90 outb((index), SMSC_INDEX_PORT_ADDR); \
91 outb((val), SMSC_DATA_PORT_ADDR); })
93 #define IDE1_PRIMARY_BASE 0x01f0
94 #define IDE1_SECONDARY_BASE 0x03f6
96 unsigned long smsc_superio_virt;
99 * Platform dependent structures: maps and parms block.
101 struct resource io_resources[] = {
102 /* To be updated with external devices */
105 struct resource kram_resources[] = {
106 /* These must be last in the array */
107 { .name = "Kernel code", .start = 0, .end = 0 },
108 /* These must be last in the array */
109 { .name = "Kernel data", .start = 0, .end = 0 }
112 struct resource xram_resources[] = {
113 /* To be updated with external devices */
116 struct resource rom_resources[] = {
117 /* To be updated with external devices */
120 struct sh64_platform platform_parms = {
121 .readonly_rootfs = 1,
122 .initial_root_dev = 0x0100,
124 .io_res_p = io_resources,
125 .io_res_count = ARRAY_SIZE(io_resources),
126 .kram_res_p = kram_resources,
127 .kram_res_count = ARRAY_SIZE(kram_resources),
128 .xram_res_p = xram_resources,
129 .xram_res_count = ARRAY_SIZE(xram_resources),
130 .rom_res_p = rom_resources,
131 .rom_res_count = ARRAY_SIZE(rom_resources),
134 int platform_int_priority[NR_INTC_IRQS] = {
135 IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ 0- 7 */
136 RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ 8-15 */
137 PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */
138 RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */
139 TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */
140 RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */
141 RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */
142 RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */
145 static int __init smsc_superio_setup(void)
147 unsigned char devid, devrev;
149 smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO");
150 if (!smsc_superio_virt) {
151 panic("Unable to remap SMSC SuperIO\n");
154 /* Initially the chip is in run state */
155 /* Put it into configuration state */
156 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
157 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
159 /* Read device ID info */
160 devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
161 devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
162 printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev);
164 /* Select the keyboard device */
165 SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
168 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
170 /* Select the interrupts */
171 /* On a PC keyboard is IRQ1, mouse is IRQ12 */
172 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX);
173 SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX);
177 * Only IDE1 exists on the Cayman
181 SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22);
183 SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
184 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
186 SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8,
187 SMSC_PRIMARY_BASE_INDEX + 0);
188 SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff,
189 SMSC_PRIMARY_BASE_INDEX + 1);
191 SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8,
192 SMSC_SECONDARY_BASE_INDEX + 0);
193 SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff,
194 SMSC_SECONDARY_BASE_INDEX + 1);
196 SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX);
198 SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS,
199 SMCS_LOGICAL_DEV_INDEX);
201 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
202 SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
203 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
204 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
207 /* Exit the configuration state */
208 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
213 /* This is grotty, but, because kernel is always referenced on the link line
214 * before any devices, this is safe.
216 __initcall(smsc_superio_setup);
218 void __init platform_setup(void)
220 /* Cayman platform leaves the decision to head.S, for now */
221 platform_parms.fpu_flags = fpu_in_use;
224 void __init platform_monitor(void)
229 void __init platform_reserve(void)
234 const char *get_system_type(void)
236 return "Hitachi Cayman";