2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * arch/sh64/mach-cayman/setup.c
10 * This file handles the architecture-dependent parts of initialization
12 * Copyright David J. Mckay.
15 * benedict.gaster@superh.com: 3rd May 2002
16 * Added support for ramdisk, removing statically linked romfs at the same time.
18 * lethal@linux-sh.org: 15th May 2003
19 * Use the generic procfs cpuinfo interface, just return a valid board name.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <asm/platform.h>
28 * Platform Dependent Interrupt Priorities.
31 /* Using defaults defined in irq.h */
32 #define RES NO_PRIORITY /* Disabled */
33 #define IR0 IRL0_PRIORITY /* IRLs */
34 #define IR1 IRL1_PRIORITY
35 #define IR2 IRL2_PRIORITY
36 #define IR3 IRL3_PRIORITY
37 #define PCA INTA_PRIORITY /* PCI Ints */
38 #define PCB INTB_PRIORITY
39 #define PCC INTC_PRIORITY
40 #define PCD INTD_PRIORITY
41 #define SER TOP_PRIORITY
42 #define ERR TOP_PRIORITY
43 #define PW0 TOP_PRIORITY
44 #define PW1 TOP_PRIORITY
45 #define PW2 TOP_PRIORITY
46 #define PW3 TOP_PRIORITY
47 #define DM0 NO_PRIORITY /* DMA Ints */
48 #define DM1 NO_PRIORITY
49 #define DM2 NO_PRIORITY
50 #define DM3 NO_PRIORITY
51 #define DAE NO_PRIORITY
52 #define TU0 TIMER_PRIORITY /* TMU Ints */
53 #define TU1 NO_PRIORITY
54 #define TU2 NO_PRIORITY
55 #define TI2 NO_PRIORITY
56 #define ATI NO_PRIORITY /* RTC Ints */
57 #define PRI NO_PRIORITY
58 #define CUI RTC_PRIORITY
59 #define ERI SCIF_PRIORITY /* SCIF Ints */
60 #define RXI SCIF_PRIORITY
61 #define BRI SCIF_PRIORITY
62 #define TXI SCIF_PRIORITY
63 #define ITI TOP_PRIORITY /* WDT Ints */
65 /* Setup for the SMSC FDC37C935 */
66 #define SMSC_SUPERIO_BASE 0x04000000
67 #define SMSC_CONFIG_PORT_ADDR 0x3f0
68 #define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
69 #define SMSC_DATA_PORT_ADDR 0x3f1
71 #define SMSC_ENTER_CONFIG_KEY 0x55
72 #define SMSC_EXIT_CONFIG_KEY 0xaa
74 #define SMCS_LOGICAL_DEV_INDEX 0x07
75 #define SMSC_DEVICE_ID_INDEX 0x20
76 #define SMSC_DEVICE_REV_INDEX 0x21
77 #define SMSC_ACTIVATE_INDEX 0x30
78 #define SMSC_PRIMARY_BASE_INDEX 0x60
79 #define SMSC_SECONDARY_BASE_INDEX 0x62
80 #define SMSC_PRIMARY_INT_INDEX 0x70
81 #define SMSC_SECONDARY_INT_INDEX 0x72
83 #define SMSC_IDE1_DEVICE 1
84 #define SMSC_KEYBOARD_DEVICE 7
85 #define SMSC_CONFIG_REGISTERS 8
87 #define SMSC_SUPERIO_READ_INDEXED(index) ({ \
88 outb((index), SMSC_INDEX_PORT_ADDR); \
89 inb(SMSC_DATA_PORT_ADDR); })
90 #define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \
91 outb((index), SMSC_INDEX_PORT_ADDR); \
92 outb((val), SMSC_DATA_PORT_ADDR); })
94 #define IDE1_PRIMARY_BASE 0x01f0
95 #define IDE1_SECONDARY_BASE 0x03f6
97 unsigned long smsc_superio_virt;
100 * Platform dependent structures: maps and parms block.
102 struct resource io_resources[] = {
103 /* To be updated with external devices */
106 struct resource kram_resources[] = {
107 /* These must be last in the array */
108 { .name = "Kernel code", .start = 0, .end = 0 },
109 /* These must be last in the array */
110 { .name = "Kernel data", .start = 0, .end = 0 }
113 struct resource xram_resources[] = {
114 /* To be updated with external devices */
117 struct resource rom_resources[] = {
118 /* To be updated with external devices */
121 struct sh64_platform platform_parms = {
122 .readonly_rootfs = 1,
123 .initial_root_dev = 0x0100,
125 .io_res_p = io_resources,
126 .io_res_count = ARRAY_SIZE(io_resources),
127 .kram_res_p = kram_resources,
128 .kram_res_count = ARRAY_SIZE(kram_resources),
129 .xram_res_p = xram_resources,
130 .xram_res_count = ARRAY_SIZE(xram_resources),
131 .rom_res_p = rom_resources,
132 .rom_res_count = ARRAY_SIZE(rom_resources),
135 int platform_int_priority[NR_INTC_IRQS] = {
136 IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ 0- 7 */
137 RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ 8-15 */
138 PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */
139 RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */
140 TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */
141 RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */
142 RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */
143 RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */
146 static int __init smsc_superio_setup(void)
148 unsigned char devid, devrev;
150 smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO");
151 if (!smsc_superio_virt) {
152 panic("Unable to remap SMSC SuperIO\n");
155 /* Initially the chip is in run state */
156 /* Put it into configuration state */
157 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
158 outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
160 /* Read device ID info */
161 devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
162 devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
163 printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev);
165 /* Select the keyboard device */
166 SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
169 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
171 /* Select the interrupts */
172 /* On a PC keyboard is IRQ1, mouse is IRQ12 */
173 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX);
174 SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX);
178 * Only IDE1 exists on the Cayman
182 SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22);
184 SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
185 SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
187 SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8,
188 SMSC_PRIMARY_BASE_INDEX + 0);
189 SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff,
190 SMSC_PRIMARY_BASE_INDEX + 1);
192 SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8,
193 SMSC_SECONDARY_BASE_INDEX + 0);
194 SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff,
195 SMSC_SECONDARY_BASE_INDEX + 1);
197 SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX);
199 SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS,
200 SMCS_LOGICAL_DEV_INDEX);
202 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
203 SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
204 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
205 SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
208 /* Exit the configuration state */
209 outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
214 /* This is grotty, but, because kernel is always referenced on the link line
215 * before any devices, this is safe.
217 __initcall(smsc_superio_setup);
219 void __init platform_setup(void)
221 /* Cayman platform leaves the decision to head.S, for now */
222 platform_parms.fpu_flags = fpu_in_use;
225 void __init platform_monitor(void)
230 void __init platform_reserve(void)
235 const char *get_system_type(void)
237 return "Hitachi Cayman";