2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * arch/sh64/kernel/traps.c
8 * Copyright (C) 2000, 2001 Paolo Alberelli
9 * Copyright (C) 2003, 2004 Paul Mundt
10 * Copyright (C) 2003, 2004 Richard Curnow
15 * 'Traps.c' handles hardware traps and faults after we have saved some
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/errno.h>
22 #include <linux/ptrace.h>
23 #include <linux/timer.h>
25 #include <linux/smp.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/spinlock.h>
29 #include <linux/kallsyms.h>
30 #include <linux/interrupt.h>
31 #include <linux/sysctl.h>
32 #include <linux/module.h>
33 #include <asm/system.h>
34 #include <asm/uaccess.h>
36 #include <asm/atomic.h>
37 #include <asm/processor.h>
38 #include <asm/pgtable.h>
40 #undef DEBUG_EXCEPTION
41 #ifdef DEBUG_EXCEPTION
42 /* implemented in ../lib/dbg.c */
43 extern void show_excp_regs(char *fname, int trapnr, int signr,
44 struct pt_regs *regs);
46 #define show_excp_regs(a, b, c, d)
49 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
50 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
52 #define DO_ERROR(trapnr, signr, str, name, tsk) \
53 asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
55 do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
60 void die(const char * str, struct pt_regs * regs, long err)
63 spin_lock_irq(&die_lock);
64 printk("%s: %lx\n", str, (err & 0xffffff));
66 spin_unlock_irq(&die_lock);
70 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
76 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
78 if (!user_mode(regs)) {
79 const struct exception_table_entry *fixup;
80 fixup = search_exception_tables(regs->pc);
82 regs->pc = fixup->fixup;
89 DO_ERROR(13, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
90 DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
93 /* Implement misaligned load/store handling for kernel (and optionally for user
94 mode too). Limitation : only SHmedia mode code is handled - there is no
95 handling at all for misaligned accesses occurring in SHcompact code yet. */
97 static int misaligned_fixup(struct pt_regs *regs);
99 asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
101 if (misaligned_fixup(regs) < 0) {
102 do_unhandled_exception(7, SIGSEGV, "address error(load)",
103 "do_address_error_load",
104 error_code, regs, current);
109 asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
111 if (misaligned_fixup(regs) < 0) {
112 do_unhandled_exception(8, SIGSEGV, "address error(store)",
113 "do_address_error_store",
114 error_code, regs, current);
119 #if defined(CONFIG_SH64_ID2815_WORKAROUND)
121 #define OPCODE_INVALID 0
122 #define OPCODE_USER_VALID 1
123 #define OPCODE_PRIV_VALID 2
125 /* getcon/putcon - requires checking which control register is referenced. */
126 #define OPCODE_CTRL_REG 3
128 /* Table of valid opcodes for SHmedia mode.
129 Form a 10-bit value by concatenating the major/minor opcodes i.e.
130 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
131 array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
132 LSBs==4'b0000 etc). */
133 static unsigned long shmedia_opcode_table[64] = {
134 0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
135 0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
136 0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
137 0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
138 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
139 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
140 0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
141 0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
144 void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
146 /* Workaround SH5-101 cut2 silicon defect #2815 :
147 in some situations, inter-mode branches from SHcompact -> SHmedia
148 which should take ITLBMISS or EXECPROT exceptions at the target
149 falsely take RESINST at the target instead. */
151 unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
152 unsigned long pc, aligned_pc;
156 char *exception_name = "reserved_instruction";
160 /* SHmedia : check for defect. This requires executable vmas
161 to be readable too. */
162 aligned_pc = pc & ~3;
163 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
164 get_user_error = -EFAULT;
166 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
168 if (get_user_error >= 0) {
169 unsigned long index, shift;
170 unsigned long major, minor, combined;
171 unsigned long reserved_field;
172 reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
173 major = (opcode >> 26) & 0x3f;
174 minor = (opcode >> 16) & 0xf;
175 combined = (major << 4) | minor;
178 if (reserved_field == 0) {
179 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
180 switch (opcode_state) {
184 case OPCODE_USER_VALID:
185 /* Restart the instruction : the branch to the instruction will now be from an RTE
186 not from SHcompact so the silicon defect won't be triggered. */
188 case OPCODE_PRIV_VALID:
189 if (!user_mode(regs)) {
190 /* Should only ever get here if a module has
191 SHcompact code inside it. If so, the same fix up is needed. */
192 return; /* same reason */
194 /* Otherwise, user mode trying to execute a privileged instruction -
195 fall through to trap. */
197 case OPCODE_CTRL_REG:
198 /* If in privileged mode, return as above. */
199 if (!user_mode(regs)) return;
200 /* In user mode ... */
201 if (combined == 0x9f) { /* GETCON */
202 unsigned long regno = (opcode >> 20) & 0x3f;
206 /* Otherwise, reserved or privileged control register, => trap */
207 } else if (combined == 0x1bf) { /* PUTCON */
208 unsigned long regno = (opcode >> 4) & 0x3f;
212 /* Otherwise, reserved or privileged control register, => trap */
218 /* Fall through to trap. */
222 /* fall through to normal resinst processing */
224 /* Error trying to read opcode. This typically means a
225 real fault, not a RESINST any more. So change the
228 exception_name = "address error (exec)";
233 do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
236 #else /* CONFIG_SH64_ID2815_WORKAROUND */
238 /* If the workaround isn't needed, this is just a straightforward reserved
240 DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
242 #endif /* CONFIG_SH64_ID2815_WORKAROUND */
244 /* Called with interrupts disabled */
245 asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
248 show_excp_regs(__FUNCTION__, -1, -1, regs);
249 die_if_kernel("exception", regs, ex);
252 int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
255 printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
257 die_if_kernel("unknown trapa", regs, scId);
262 void show_stack(struct task_struct *tsk, unsigned long *sp)
264 #ifdef CONFIG_KALLSYMS
265 extern void sh64_unwind(struct pt_regs *regs);
266 struct pt_regs *regs;
268 regs = tsk ? tsk->thread.kregs : NULL;
272 printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
276 void show_task(unsigned long *sp)
278 show_stack(NULL, sp);
281 void dump_stack(void)
285 /* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
286 EXPORT_SYMBOL(dump_stack);
288 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
289 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
291 show_excp_regs(fn_name, trapnr, signr, regs);
292 tsk->thread.error_code = error_code;
293 tsk->thread.trap_no = trapnr;
296 force_sig(signr, tsk);
298 die_if_no_fixup(str, regs, error_code);
301 static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
304 unsigned long aligned_pc;
305 unsigned long opcode;
309 aligned_pc = pc & ~3;
310 if (from_user_mode) {
311 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
312 get_user_error = -EFAULT;
314 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
315 *result_opcode = opcode;
317 return get_user_error;
319 /* If the fault was in the kernel, we can either read
320 * this directly, or if not, we fault.
322 *result_opcode = *(unsigned long *) aligned_pc;
325 } else if ((pc & 1) == 0) {
327 /* TODO : provide handling for this. We don't really support
328 user-mode SHcompact yet, and for a kernel fault, this would
329 have to come from a module built for SHcompact. */
337 static int address_is_sign_extended(__u64 a)
341 b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
342 return (b == a) ? 1 : 0;
344 #error "Sign extend check only works for NEFF==32"
348 static int generate_and_check_address(struct pt_regs *regs,
350 int displacement_not_indexed,
354 /* return -1 for fault, 0 for OK */
356 __u64 base_address, addr;
359 basereg = (opcode >> 20) & 0x3f;
360 base_address = regs->regs[basereg];
361 if (displacement_not_indexed) {
363 displacement = (opcode >> 10) & 0x3ff;
364 displacement = ((displacement << 54) >> 54); /* sign extend */
365 addr = (__u64)((__s64)base_address + (displacement << width_shift));
369 offsetreg = (opcode >> 10) & 0x3f;
370 offset = regs->regs[offsetreg];
371 addr = base_address + offset;
374 /* Check sign extended */
375 if (!address_is_sign_extended(addr)) {
379 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
380 /* Check accessible. For misaligned access in the kernel, assume the
381 address is always accessible (and if not, just fault when the
382 load/store gets done.) */
383 if (user_mode(regs)) {
384 if (addr >= TASK_SIZE) {
387 /* Do access_ok check later - it depends on whether it's a load or a store. */
395 /* Default value as for sh */
396 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
397 static int user_mode_unaligned_fixup_count = 10;
398 static int user_mode_unaligned_fixup_enable = 1;
401 static int kernel_mode_unaligned_fixup_count = 32;
403 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
406 unsigned char *p, *q;
407 p = (unsigned char *) (int) address;
408 q = (unsigned char *) &x;
412 if (do_sign_extend) {
413 *result = (__u64)(__s64) *(short *) &x;
419 static void misaligned_kernel_word_store(__u64 address, __u64 value)
422 unsigned char *p, *q;
423 p = (unsigned char *) (int) address;
424 q = (unsigned char *) &x;
431 static int misaligned_load(struct pt_regs *regs,
433 int displacement_not_indexed,
437 /* Return -1 for a fault, 0 for OK */
442 error = generate_and_check_address(regs, opcode,
443 displacement_not_indexed, width_shift, &address);
448 destreg = (opcode >> 4) & 0x3f;
449 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
450 if (user_mode(regs)) {
453 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
457 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
458 return -1; /* fault */
460 switch (width_shift) {
462 if (do_sign_extend) {
463 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
465 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
469 regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
472 regs->regs[destreg] = buffer;
475 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
476 width_shift, (unsigned long) regs->pc);
482 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
485 switch (width_shift) {
487 misaligned_kernel_word_load(address, do_sign_extend, ®s->regs[destreg]);
490 asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
491 asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
492 regs->regs[destreg] = lo | hi;
495 asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
496 asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
497 regs->regs[destreg] = lo | hi;
501 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
502 width_shift, (unsigned long) regs->pc);
511 static int misaligned_store(struct pt_regs *regs,
513 int displacement_not_indexed,
516 /* Return -1 for a fault, 0 for OK */
521 error = generate_and_check_address(regs, opcode,
522 displacement_not_indexed, width_shift, &address);
527 srcreg = (opcode >> 4) & 0x3f;
528 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
529 if (user_mode(regs)) {
532 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
536 switch (width_shift) {
538 *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
541 *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
544 buffer = regs->regs[srcreg];
547 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
548 width_shift, (unsigned long) regs->pc);
552 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
553 return -1; /* fault */
558 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
559 __u64 val = regs->regs[srcreg];
561 switch (width_shift) {
563 misaligned_kernel_word_store(address, val);
566 asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
567 asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
570 asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
571 asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
575 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
576 width_shift, (unsigned long) regs->pc);
585 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
586 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
588 static int misaligned_fpu_load(struct pt_regs *regs,
590 int displacement_not_indexed,
594 /* Return -1 for a fault, 0 for OK */
599 error = generate_and_check_address(regs, opcode,
600 displacement_not_indexed, width_shift, &address);
605 destreg = (opcode >> 4) & 0x3f;
606 if (user_mode(regs)) {
610 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
614 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
615 return -1; /* fault */
617 /* 'current' may be the current owner of the FPU state, so
618 context switch the registers into memory so they can be
619 indexed by register number. */
620 if (last_task_used_math == current) {
622 fpsave(¤t->thread.fpu.hard);
624 last_task_used_math = NULL;
628 buflo = *(__u32*) &buffer;
629 bufhi = *(1 + (__u32*) &buffer);
631 switch (width_shift) {
633 current->thread.fpu.hard.fp_regs[destreg] = buflo;
636 if (do_paired_load) {
637 current->thread.fpu.hard.fp_regs[destreg] = buflo;
638 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
640 #if defined(CONFIG_LITTLE_ENDIAN)
641 current->thread.fpu.hard.fp_regs[destreg] = bufhi;
642 current->thread.fpu.hard.fp_regs[destreg+1] = buflo;
644 current->thread.fpu.hard.fp_regs[destreg] = buflo;
645 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
650 printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
651 width_shift, (unsigned long) regs->pc);
656 die ("Misaligned FPU load inside kernel", regs, 0);
663 static int misaligned_fpu_store(struct pt_regs *regs,
665 int displacement_not_indexed,
669 /* Return -1 for a fault, 0 for OK */
674 error = generate_and_check_address(regs, opcode,
675 displacement_not_indexed, width_shift, &address);
680 srcreg = (opcode >> 4) & 0x3f;
681 if (user_mode(regs)) {
683 /* Initialise these to NaNs. */
684 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
686 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
690 /* 'current' may be the current owner of the FPU state, so
691 context switch the registers into memory so they can be
692 indexed by register number. */
693 if (last_task_used_math == current) {
695 fpsave(¤t->thread.fpu.hard);
697 last_task_used_math = NULL;
701 switch (width_shift) {
703 buflo = current->thread.fpu.hard.fp_regs[srcreg];
706 if (do_paired_load) {
707 buflo = current->thread.fpu.hard.fp_regs[srcreg];
708 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
710 #if defined(CONFIG_LITTLE_ENDIAN)
711 bufhi = current->thread.fpu.hard.fp_regs[srcreg];
712 buflo = current->thread.fpu.hard.fp_regs[srcreg+1];
714 buflo = current->thread.fpu.hard.fp_regs[srcreg];
715 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
720 printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
721 width_shift, (unsigned long) regs->pc);
725 *(__u32*) &buffer = buflo;
726 *(1 + (__u32*) &buffer) = bufhi;
727 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
728 return -1; /* fault */
732 die ("Misaligned FPU load inside kernel", regs, 0);
738 static int misaligned_fixup(struct pt_regs *regs)
740 unsigned long opcode;
744 #if !defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
745 /* Never fixup user mode misaligned accesses without this option enabled. */
748 if (!user_mode_unaligned_fixup_enable) return -1;
751 error = read_opcode(regs->pc, &opcode, user_mode(regs));
755 major = (opcode >> 26) & 0x3f;
756 minor = (opcode >> 16) & 0xf;
758 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
759 if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
760 --user_mode_unaligned_fixup_count;
761 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
762 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
763 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
766 if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
767 --kernel_mode_unaligned_fixup_count;
768 if (in_interrupt()) {
769 printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
770 (__u32)regs->pc, opcode);
772 printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
773 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
779 case (0x84>>2): /* LD.W */
780 error = misaligned_load(regs, opcode, 1, 1, 1);
782 case (0xb0>>2): /* LD.UW */
783 error = misaligned_load(regs, opcode, 1, 1, 0);
785 case (0x88>>2): /* LD.L */
786 error = misaligned_load(regs, opcode, 1, 2, 1);
788 case (0x8c>>2): /* LD.Q */
789 error = misaligned_load(regs, opcode, 1, 3, 0);
792 case (0xa4>>2): /* ST.W */
793 error = misaligned_store(regs, opcode, 1, 1);
795 case (0xa8>>2): /* ST.L */
796 error = misaligned_store(regs, opcode, 1, 2);
798 case (0xac>>2): /* ST.Q */
799 error = misaligned_store(regs, opcode, 1, 3);
802 case (0x40>>2): /* indexed loads */
804 case 0x1: /* LDX.W */
805 error = misaligned_load(regs, opcode, 0, 1, 1);
807 case 0x5: /* LDX.UW */
808 error = misaligned_load(regs, opcode, 0, 1, 0);
810 case 0x2: /* LDX.L */
811 error = misaligned_load(regs, opcode, 0, 2, 1);
813 case 0x3: /* LDX.Q */
814 error = misaligned_load(regs, opcode, 0, 3, 0);
822 case (0x60>>2): /* indexed stores */
824 case 0x1: /* STX.W */
825 error = misaligned_store(regs, opcode, 0, 1);
827 case 0x2: /* STX.L */
828 error = misaligned_store(regs, opcode, 0, 2);
830 case 0x3: /* STX.Q */
831 error = misaligned_store(regs, opcode, 0, 3);
839 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
840 case (0x94>>2): /* FLD.S */
841 error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
843 case (0x98>>2): /* FLD.P */
844 error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
846 case (0x9c>>2): /* FLD.D */
847 error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
849 case (0x1c>>2): /* floating indexed loads */
851 case 0x8: /* FLDX.S */
852 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
854 case 0xd: /* FLDX.P */
855 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
857 case 0x9: /* FLDX.D */
858 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
865 case (0xb4>>2): /* FLD.S */
866 error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
868 case (0xb8>>2): /* FLD.P */
869 error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
871 case (0xbc>>2): /* FLD.D */
872 error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
874 case (0x3c>>2): /* floating indexed stores */
876 case 0x8: /* FSTX.S */
877 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
879 case 0xd: /* FSTX.P */
880 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
882 case 0x9: /* FSTX.D */
883 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
901 regs->pc += 4; /* Skip the instruction that's just been emulated */
907 static ctl_table unaligned_table[] = {
909 .ctl_name = CTL_UNNUMBERED,
910 .procname = "kernel_reports",
911 .data = &kernel_mode_unaligned_fixup_count,
912 .maxlen = sizeof(int),
914 .proc_handler = &proc_dointvec
916 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
918 .ctl_name = CTL_UNNUMBERED,
919 .procname = "user_reports",
920 .data = &user_mode_unaligned_fixup_count,
921 .maxlen = sizeof(int),
923 .proc_handler = &proc_dointvec
926 .ctl_name = CTL_UNNUMBERED,
927 .procname = "user_enable",
928 .data = &user_mode_unaligned_fixup_enable,
929 .maxlen = sizeof(int),
931 .proc_handler = &proc_dointvec},
936 static ctl_table unaligned_root[] = {
938 .ctl_name = CTL_UNNUMBERED,
939 .procname = "unaligned_fixup",
946 static ctl_table sh64_root[] = {
948 .ctl_name = CTL_UNNUMBERED,
951 .child = unaligned_root
955 static struct ctl_table_header *sysctl_header;
956 static int __init init_sysctl(void)
958 sysctl_header = register_sysctl_table(sh64_root);
962 __initcall(init_sysctl);
965 asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
967 u64 peek_real_address_q(u64 addr);
968 u64 poke_real_address_q(u64 addr, u64 val);
969 unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
970 unsigned long long exp_cause;
971 /* It's not worth ioremapping the debug module registers for the amount
972 of access we make to them - just go direct to their physical
974 exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
975 if (exp_cause & ~4) {
976 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
977 (unsigned long)(exp_cause & 0xffffffff));
980 /* Clear all DEBUGINT causes */
981 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);