20 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
21 select CPU_HAS_FPU if !CPU_SH4AL_DSP
32 config CPU_SUBTYPE_ST40
43 prompt "Processor sub-type selection"
49 # SH-2 Processor Support
51 config CPU_SUBTYPE_SH7619
52 bool "Support SH7619 processor"
55 # SH-2A Processor Support
57 config CPU_SUBTYPE_SH7206
58 bool "Support SH7206 processor"
61 # SH-3 Processor Support
63 config CPU_SUBTYPE_SH7705
64 bool "Support SH7705 processor"
67 config CPU_SUBTYPE_SH7706
68 bool "Support SH7706 processor"
71 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
73 config CPU_SUBTYPE_SH7707
74 bool "Support SH7707 processor"
77 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
79 config CPU_SUBTYPE_SH7708
80 bool "Support SH7708 processor"
83 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
84 if you have a 100 Mhz SH-3 HD6417708R CPU.
86 config CPU_SUBTYPE_SH7709
87 bool "Support SH7709 processor"
90 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
92 config CPU_SUBTYPE_SH7710
93 bool "Support SH7710 processor"
97 Select SH7710 if you have a SH3-DSP SH7710 CPU.
99 config CPU_SUBTYPE_SH7712
100 bool "Support SH7712 processor"
104 Select SH7712 if you have a SH3-DSP SH7712 CPU.
106 config CPU_SUBTYPE_SH7720
107 bool "Support SH7720 processor"
111 Select SH7720 if you have a SH3-DSP SH7720 CPU.
113 # SH-4 Processor Support
115 config CPU_SUBTYPE_SH7750
116 bool "Support SH7750 processor"
119 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
121 config CPU_SUBTYPE_SH7091
122 bool "Support SH7091 processor"
125 Select SH7091 if you have an SH-4 based Sega device (such as
126 the Dreamcast, Naomi, and Naomi 2).
128 config CPU_SUBTYPE_SH7750R
129 bool "Support SH7750R processor"
132 config CPU_SUBTYPE_SH7750S
133 bool "Support SH7750S processor"
136 config CPU_SUBTYPE_SH7751
137 bool "Support SH7751 processor"
140 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
141 or if you have a HD6417751R CPU.
143 config CPU_SUBTYPE_SH7751R
144 bool "Support SH7751R processor"
147 config CPU_SUBTYPE_SH7760
148 bool "Support SH7760 processor"
151 config CPU_SUBTYPE_SH4_202
152 bool "Support SH4-202 processor"
155 # ST40 Processor Support
157 config CPU_SUBTYPE_ST40STB1
158 bool "Support ST40STB1/ST40RA processors"
159 select CPU_SUBTYPE_ST40
161 Select ST40STB1 if you have a ST40RA CPU.
162 This was previously called the ST40STB1, hence the option name.
164 config CPU_SUBTYPE_ST40GX1
165 bool "Support ST40GX1 processor"
166 select CPU_SUBTYPE_ST40
168 Select ST40GX1 if you have a ST40GX1 CPU.
170 # SH-4A Processor Support
172 config CPU_SUBTYPE_SH7770
173 bool "Support SH7770 processor"
176 config CPU_SUBTYPE_SH7780
177 bool "Support SH7780 processor"
180 config CPU_SUBTYPE_SH7785
181 bool "Support SH7785 processor"
184 select ARCH_SPARSEMEM_ENABLE
185 select SYS_SUPPORTS_NUMA
187 config CPU_SUBTYPE_SHX3
188 bool "Support SH-X3 processor"
191 select ARCH_SPARSEMEM_ENABLE
192 select SYS_SUPPORTS_NUMA
194 # SH4AL-DSP Processor Support
196 config CPU_SUBTYPE_SH7343
197 bool "Support SH7343 processor"
200 config CPU_SUBTYPE_SH7722
201 bool "Support SH7722 processor"
204 select ARCH_SPARSEMEM_ENABLE
205 select SYS_SUPPORTS_NUMA
209 menu "Memory management options"
215 bool "Support for memory management hardware"
219 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
220 boot on these systems, this option must not be set.
222 On other systems (such as the SH-3 and 4) where an MMU exists,
223 turning this off will boot the kernel on these machines with the
224 MMU implicitly switched off.
228 default "0x80000000" if MMU
232 hex "Physical memory start address"
235 Computers built with Hitachi SuperH processors always
236 map the ROM starting at address zero. But the processor
237 does not specify the range that RAM takes.
239 The physical memory (RAM) start address will be automatically
240 set to 08000000. Other platforms, such as the Solution Engine
241 boards typically map RAM at 0C000000.
243 Tweak this only when porting to a new machine which does not
244 already have a defconfig. Changing it from the known correct
245 value on any of the known systems will only lead to disaster.
248 hex "Physical memory size"
251 This sets the default memory size assumed by your SH kernel. It can
252 be overridden as normal by the 'mem=' argument on the kernel command
253 line. If unsure, consult your board specifications or just leave it
254 as 0x00400000 which was the default value before this became
258 bool "Support 32-bit physical addressing through PMB"
259 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
262 If you say Y here, physical addressing will be extended to
263 32-bits through the SH-4A PMB. If this is not set, legacy
264 29-bit physical addressing will be used.
267 bool "Enable extended TLB mode"
268 depends on CPU_SHX2 && MMU && EXPERIMENTAL
270 Selecting this option will enable the extended mode of the SH-X2
271 TLB. For legacy SH-X behaviour and interoperability, say N. For
272 all of the fun new features and a willingless to submit bug reports,
276 bool "Support vsyscall page"
280 This will enable support for the kernel mapping a vDSO page
281 in process space, and subsequently handing down the entry point
282 to the libc through the ELF auxiliary vector.
284 From the kernel side this is used for the signal trampoline.
285 For systems with an MMU that can afford to give up a page,
286 (the default value) say Y.
289 bool "Non Uniform Memory Access (NUMA) Support"
290 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
293 Some SH systems have many various memories scattered around
294 the address space, each with varying latencies. This enables
295 support for these blocks by binding them to nodes and allowing
296 memory policies to be used for prioritizing and controlling
297 allocation behaviour.
301 default "3" if CPU_SUBTYPE_SHX3
303 depends on NEED_MULTIPLE_NODES
305 config ARCH_FLATMEM_ENABLE
309 config ARCH_SPARSEMEM_ENABLE
311 select SPARSEMEM_STATIC
313 config ARCH_SPARSEMEM_DEFAULT
316 config MAX_ACTIVE_REGIONS
318 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
319 default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
322 config ARCH_POPULATES_NODE_MAP
325 config ARCH_SELECT_MEMORY_MODEL
328 config ARCH_ENABLE_MEMORY_HOTPLUG
332 config ARCH_MEMORY_PROBE
334 depends on MEMORY_HOTPLUG
337 prompt "Kernel page size"
338 default PAGE_SIZE_4KB
343 This is the default page size used by all SuperH CPUs.
347 depends on EXPERIMENTAL && X2TLB
349 This enables 8kB pages as supported by SH-X2 and later MMUs.
351 config PAGE_SIZE_64KB
353 depends on EXPERIMENTAL && CPU_SH4
355 This enables support for 64kB pages, possible on all SH-4
356 CPUs and later. Highly experimental, not recommended.
361 prompt "HugeTLB page size"
362 depends on HUGETLB_PAGE && CPU_SH4 && MMU
363 default HUGETLB_PAGE_SIZE_64K
365 config HUGETLB_PAGE_SIZE_64K
368 config HUGETLB_PAGE_SIZE_256K
372 config HUGETLB_PAGE_SIZE_1MB
375 config HUGETLB_PAGE_SIZE_4MB
379 config HUGETLB_PAGE_SIZE_64MB
389 menu "Cache configuration"
391 config SH7705_CACHE_32KB
392 bool "Enable 32KB cache size for SH7705"
393 depends on CPU_SUBTYPE_SH7705
396 config SH_DIRECT_MAPPED
397 bool "Use direct-mapped caching"
400 Selecting this option will configure the caches to be direct-mapped,
401 even if the cache supports a 2 or 4-way mode. This is useful primarily
402 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
403 SH4-202, SH4-501, etc.)
405 Turn this option off for platforms that do not have a direct-mapped
406 cache, and you have no need to run the caches in such a configuration.
410 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
411 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
413 config CACHE_WRITEBACK
415 depends on CPU_SH2A || CPU_SH3 || CPU_SH4
417 config CACHE_WRITETHROUGH
420 Selecting this option will configure the caches in write-through
421 mode, as opposed to the default write-back configuration.
423 Since there's sill some aliasing issues on SH-4, this option will
424 unfortunately still require the majority of flushing functions to
425 be implemented to deal with aliasing.