20 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
31 config CPU_SUBTYPE_ST40
34 select CPU_HAS_INTC2_IRQ
43 prompt "Processor sub-type selection"
49 # SH-2 Processor Support
51 config CPU_SUBTYPE_SH7619
52 bool "Support SH7619 processor"
54 select CPU_HAS_IPR_IRQ
56 # SH-2A Processor Support
58 config CPU_SUBTYPE_SH7206
59 bool "Support SH7206 processor"
61 select CPU_HAS_IPR_IRQ
63 # SH-3 Processor Support
65 config CPU_SUBTYPE_SH7705
66 bool "Support SH7705 processor"
68 select CPU_HAS_INTC_IRQ
70 config CPU_SUBTYPE_SH7706
71 bool "Support SH7706 processor"
73 select CPU_HAS_INTC_IRQ
75 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
77 config CPU_SUBTYPE_SH7707
78 bool "Support SH7707 processor"
80 select CPU_HAS_INTC_IRQ
82 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
84 config CPU_SUBTYPE_SH7708
85 bool "Support SH7708 processor"
87 select CPU_HAS_INTC_IRQ
89 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
90 if you have a 100 Mhz SH-3 HD6417708R CPU.
92 config CPU_SUBTYPE_SH7709
93 bool "Support SH7709 processor"
95 select CPU_HAS_INTC_IRQ
97 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
99 config CPU_SUBTYPE_SH7710
100 bool "Support SH7710 processor"
102 select CPU_HAS_INTC_IRQ
105 Select SH7710 if you have a SH3-DSP SH7710 CPU.
107 config CPU_SUBTYPE_SH7712
108 bool "Support SH7712 processor"
110 select CPU_HAS_INTC_IRQ
113 Select SH7712 if you have a SH3-DSP SH7712 CPU.
115 # SH-4 Processor Support
117 config CPU_SUBTYPE_SH7750
118 bool "Support SH7750 processor"
120 select CPU_HAS_INTC_IRQ
122 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
124 config CPU_SUBTYPE_SH7091
125 bool "Support SH7091 processor"
127 select CPU_HAS_INTC_IRQ
129 Select SH7091 if you have an SH-4 based Sega device (such as
130 the Dreamcast, Naomi, and Naomi 2).
132 config CPU_SUBTYPE_SH7750R
133 bool "Support SH7750R processor"
135 select CPU_HAS_INTC_IRQ
137 config CPU_SUBTYPE_SH7750S
138 bool "Support SH7750S processor"
140 select CPU_HAS_INTC_IRQ
142 config CPU_SUBTYPE_SH7751
143 bool "Support SH7751 processor"
145 select CPU_HAS_INTC_IRQ
147 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
148 or if you have a HD6417751R CPU.
150 config CPU_SUBTYPE_SH7751R
151 bool "Support SH7751R processor"
153 select CPU_HAS_INTC_IRQ
155 config CPU_SUBTYPE_SH7760
156 bool "Support SH7760 processor"
158 select CPU_HAS_INTC_IRQ
160 config CPU_SUBTYPE_SH4_202
161 bool "Support SH4-202 processor"
164 # ST40 Processor Support
166 config CPU_SUBTYPE_ST40STB1
167 bool "Support ST40STB1/ST40RA processors"
168 select CPU_SUBTYPE_ST40
170 Select ST40STB1 if you have a ST40RA CPU.
171 This was previously called the ST40STB1, hence the option name.
173 config CPU_SUBTYPE_ST40GX1
174 bool "Support ST40GX1 processor"
175 select CPU_SUBTYPE_ST40
177 Select ST40GX1 if you have a ST40GX1 CPU.
179 # SH-4A Processor Support
181 config CPU_SUBTYPE_SH7770
182 bool "Support SH7770 processor"
185 config CPU_SUBTYPE_SH7780
186 bool "Support SH7780 processor"
188 select CPU_HAS_INTC_IRQ
190 config CPU_SUBTYPE_SH7785
191 bool "Support SH7785 processor"
194 select CPU_HAS_INTC_IRQ
196 config CPU_SUBTYPE_SHX3
197 bool "Support SH-X3 processor"
200 select CPU_HAS_INTC_IRQ
201 select ARCH_SPARSEMEM_ENABLE
202 select SYS_SUPPORTS_NUMA
204 # SH4AL-DSP Processor Support
206 config CPU_SUBTYPE_SH7343
207 bool "Support SH7343 processor"
210 config CPU_SUBTYPE_SH7722
211 bool "Support SH7722 processor"
214 select CPU_HAS_INTC_IRQ
215 select ARCH_SPARSEMEM_ENABLE
216 select SYS_SUPPORTS_NUMA
220 menu "Memory management options"
226 bool "Support for memory management hardware"
230 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
231 boot on these systems, this option must not be set.
233 On other systems (such as the SH-3 and 4) where an MMU exists,
234 turning this off will boot the kernel on these machines with the
235 MMU implicitly switched off.
239 default "0x80000000" if MMU
243 hex "Physical memory start address"
246 Computers built with Hitachi SuperH processors always
247 map the ROM starting at address zero. But the processor
248 does not specify the range that RAM takes.
250 The physical memory (RAM) start address will be automatically
251 set to 08000000. Other platforms, such as the Solution Engine
252 boards typically map RAM at 0C000000.
254 Tweak this only when porting to a new machine which does not
255 already have a defconfig. Changing it from the known correct
256 value on any of the known systems will only lead to disaster.
259 hex "Physical memory size"
262 This sets the default memory size assumed by your SH kernel. It can
263 be overridden as normal by the 'mem=' argument on the kernel command
264 line. If unsure, consult your board specifications or just leave it
265 as 0x00400000 which was the default value before this became
269 bool "Support 32-bit physical addressing through PMB"
270 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
273 If you say Y here, physical addressing will be extended to
274 32-bits through the SH-4A PMB. If this is not set, legacy
275 29-bit physical addressing will be used.
278 bool "Enable extended TLB mode"
279 depends on CPU_SHX2 && MMU && EXPERIMENTAL
281 Selecting this option will enable the extended mode of the SH-X2
282 TLB. For legacy SH-X behaviour and interoperability, say N. For
283 all of the fun new features and a willingless to submit bug reports,
287 bool "Support vsyscall page"
291 This will enable support for the kernel mapping a vDSO page
292 in process space, and subsequently handing down the entry point
293 to the libc through the ELF auxiliary vector.
295 From the kernel side this is used for the signal trampoline.
296 For systems with an MMU that can afford to give up a page,
297 (the default value) say Y.
300 bool "Non Uniform Memory Access (NUMA) Support"
301 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
304 Some SH systems have many various memories scattered around
305 the address space, each with varying latencies. This enables
306 support for these blocks by binding them to nodes and allowing
307 memory policies to be used for prioritizing and controlling
308 allocation behaviour.
313 depends on NEED_MULTIPLE_NODES
315 config ARCH_FLATMEM_ENABLE
319 config ARCH_SPARSEMEM_ENABLE
321 select SPARSEMEM_STATIC
323 config ARCH_SPARSEMEM_DEFAULT
326 config MAX_ACTIVE_REGIONS
328 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
329 default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
332 config ARCH_POPULATES_NODE_MAP
335 config ARCH_SELECT_MEMORY_MODEL
338 config ARCH_ENABLE_MEMORY_HOTPLUG
342 config ARCH_MEMORY_PROBE
344 depends on MEMORY_HOTPLUG
347 prompt "Kernel page size"
348 default PAGE_SIZE_4KB
353 This is the default page size used by all SuperH CPUs.
357 depends on EXPERIMENTAL && X2TLB
359 This enables 8kB pages as supported by SH-X2 and later MMUs.
361 config PAGE_SIZE_64KB
363 depends on EXPERIMENTAL && CPU_SH4
365 This enables support for 64kB pages, possible on all SH-4
366 CPUs and later. Highly experimental, not recommended.
371 prompt "HugeTLB page size"
372 depends on HUGETLB_PAGE && CPU_SH4 && MMU
373 default HUGETLB_PAGE_SIZE_64K
375 config HUGETLB_PAGE_SIZE_64K
378 config HUGETLB_PAGE_SIZE_256K
382 config HUGETLB_PAGE_SIZE_1MB
385 config HUGETLB_PAGE_SIZE_4MB
389 config HUGETLB_PAGE_SIZE_64MB
399 menu "Cache configuration"
401 config SH7705_CACHE_32KB
402 bool "Enable 32KB cache size for SH7705"
403 depends on CPU_SUBTYPE_SH7705
406 config SH_DIRECT_MAPPED
407 bool "Use direct-mapped caching"
410 Selecting this option will configure the caches to be direct-mapped,
411 even if the cache supports a 2 or 4-way mode. This is useful primarily
412 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
413 SH4-202, SH4-501, etc.)
415 Turn this option off for platforms that do not have a direct-mapped
416 cache, and you have no need to run the caches in such a configuration.
420 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
421 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
423 config CACHE_WRITEBACK
425 depends on CPU_SH2A || CPU_SH3 || CPU_SH4
427 config CACHE_WRITETHROUGH
430 Selecting this option will configure the caches in write-through
431 mode, as opposed to the default write-back configuration.
433 Since there's sill some aliasing issues on SH-4, this option will
434 unfortunately still require the majority of flushing functions to
435 be implemented to deal with aliasing.