20 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
31 config CPU_SUBTYPE_ST40
42 prompt "Processor sub-type selection"
48 # SH-2 Processor Support
50 config CPU_SUBTYPE_SH7619
51 bool "Support SH7619 processor"
53 select CPU_HAS_IPR_IRQ
55 # SH-2A Processor Support
57 config CPU_SUBTYPE_SH7206
58 bool "Support SH7206 processor"
60 select CPU_HAS_IPR_IRQ
62 # SH-3 Processor Support
64 config CPU_SUBTYPE_SH7705
65 bool "Support SH7705 processor"
67 select CPU_HAS_INTC_IRQ
69 config CPU_SUBTYPE_SH7706
70 bool "Support SH7706 processor"
72 select CPU_HAS_INTC_IRQ
74 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
76 config CPU_SUBTYPE_SH7707
77 bool "Support SH7707 processor"
79 select CPU_HAS_INTC_IRQ
81 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
83 config CPU_SUBTYPE_SH7708
84 bool "Support SH7708 processor"
86 select CPU_HAS_INTC_IRQ
88 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
89 if you have a 100 Mhz SH-3 HD6417708R CPU.
91 config CPU_SUBTYPE_SH7709
92 bool "Support SH7709 processor"
94 select CPU_HAS_INTC_IRQ
96 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
98 config CPU_SUBTYPE_SH7710
99 bool "Support SH7710 processor"
101 select CPU_HAS_INTC_IRQ
104 Select SH7710 if you have a SH3-DSP SH7710 CPU.
106 config CPU_SUBTYPE_SH7712
107 bool "Support SH7712 processor"
109 select CPU_HAS_INTC_IRQ
112 Select SH7712 if you have a SH3-DSP SH7712 CPU.
114 config CPU_SUBTYPE_SH7720
115 bool "Support SH7720 processor"
117 select CPU_HAS_INTC_IRQ
120 Select SH7720 if you have a SH3-DSP SH7720 CPU.
122 # SH-4 Processor Support
124 config CPU_SUBTYPE_SH7750
125 bool "Support SH7750 processor"
127 select CPU_HAS_INTC_IRQ
129 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
131 config CPU_SUBTYPE_SH7091
132 bool "Support SH7091 processor"
134 select CPU_HAS_INTC_IRQ
136 Select SH7091 if you have an SH-4 based Sega device (such as
137 the Dreamcast, Naomi, and Naomi 2).
139 config CPU_SUBTYPE_SH7750R
140 bool "Support SH7750R processor"
142 select CPU_HAS_INTC_IRQ
144 config CPU_SUBTYPE_SH7750S
145 bool "Support SH7750S processor"
147 select CPU_HAS_INTC_IRQ
149 config CPU_SUBTYPE_SH7751
150 bool "Support SH7751 processor"
152 select CPU_HAS_INTC_IRQ
154 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
155 or if you have a HD6417751R CPU.
157 config CPU_SUBTYPE_SH7751R
158 bool "Support SH7751R processor"
160 select CPU_HAS_INTC_IRQ
162 config CPU_SUBTYPE_SH7760
163 bool "Support SH7760 processor"
165 select CPU_HAS_INTC_IRQ
167 config CPU_SUBTYPE_SH4_202
168 bool "Support SH4-202 processor"
171 # ST40 Processor Support
173 config CPU_SUBTYPE_ST40STB1
174 bool "Support ST40STB1/ST40RA processors"
175 select CPU_SUBTYPE_ST40
177 Select ST40STB1 if you have a ST40RA CPU.
178 This was previously called the ST40STB1, hence the option name.
180 config CPU_SUBTYPE_ST40GX1
181 bool "Support ST40GX1 processor"
182 select CPU_SUBTYPE_ST40
184 Select ST40GX1 if you have a ST40GX1 CPU.
186 # SH-4A Processor Support
188 config CPU_SUBTYPE_SH7770
189 bool "Support SH7770 processor"
192 config CPU_SUBTYPE_SH7780
193 bool "Support SH7780 processor"
195 select CPU_HAS_INTC_IRQ
197 config CPU_SUBTYPE_SH7785
198 bool "Support SH7785 processor"
201 select CPU_HAS_INTC_IRQ
203 config CPU_SUBTYPE_SHX3
204 bool "Support SH-X3 processor"
207 select CPU_HAS_INTC_IRQ
208 select ARCH_SPARSEMEM_ENABLE
209 select SYS_SUPPORTS_NUMA
211 # SH4AL-DSP Processor Support
213 config CPU_SUBTYPE_SH7343
214 bool "Support SH7343 processor"
217 config CPU_SUBTYPE_SH7722
218 bool "Support SH7722 processor"
221 select CPU_HAS_INTC_IRQ
222 select ARCH_SPARSEMEM_ENABLE
223 select SYS_SUPPORTS_NUMA
227 menu "Memory management options"
233 bool "Support for memory management hardware"
237 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
238 boot on these systems, this option must not be set.
240 On other systems (such as the SH-3 and 4) where an MMU exists,
241 turning this off will boot the kernel on these machines with the
242 MMU implicitly switched off.
246 default "0x80000000" if MMU
250 hex "Physical memory start address"
253 Computers built with Hitachi SuperH processors always
254 map the ROM starting at address zero. But the processor
255 does not specify the range that RAM takes.
257 The physical memory (RAM) start address will be automatically
258 set to 08000000. Other platforms, such as the Solution Engine
259 boards typically map RAM at 0C000000.
261 Tweak this only when porting to a new machine which does not
262 already have a defconfig. Changing it from the known correct
263 value on any of the known systems will only lead to disaster.
266 hex "Physical memory size"
269 This sets the default memory size assumed by your SH kernel. It can
270 be overridden as normal by the 'mem=' argument on the kernel command
271 line. If unsure, consult your board specifications or just leave it
272 as 0x00400000 which was the default value before this became
276 bool "Support 32-bit physical addressing through PMB"
277 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
280 If you say Y here, physical addressing will be extended to
281 32-bits through the SH-4A PMB. If this is not set, legacy
282 29-bit physical addressing will be used.
285 bool "Enable extended TLB mode"
286 depends on CPU_SHX2 && MMU && EXPERIMENTAL
288 Selecting this option will enable the extended mode of the SH-X2
289 TLB. For legacy SH-X behaviour and interoperability, say N. For
290 all of the fun new features and a willingless to submit bug reports,
294 bool "Support vsyscall page"
298 This will enable support for the kernel mapping a vDSO page
299 in process space, and subsequently handing down the entry point
300 to the libc through the ELF auxiliary vector.
302 From the kernel side this is used for the signal trampoline.
303 For systems with an MMU that can afford to give up a page,
304 (the default value) say Y.
307 bool "Non Uniform Memory Access (NUMA) Support"
308 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
311 Some SH systems have many various memories scattered around
312 the address space, each with varying latencies. This enables
313 support for these blocks by binding them to nodes and allowing
314 memory policies to be used for prioritizing and controlling
315 allocation behaviour.
319 default "3" if CPU_SUBTYPE_SHX3
321 depends on NEED_MULTIPLE_NODES
323 config ARCH_FLATMEM_ENABLE
327 config ARCH_SPARSEMEM_ENABLE
329 select SPARSEMEM_STATIC
331 config ARCH_SPARSEMEM_DEFAULT
334 config MAX_ACTIVE_REGIONS
336 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
337 default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
340 config ARCH_POPULATES_NODE_MAP
343 config ARCH_SELECT_MEMORY_MODEL
346 config ARCH_ENABLE_MEMORY_HOTPLUG
350 config ARCH_MEMORY_PROBE
352 depends on MEMORY_HOTPLUG
355 prompt "Kernel page size"
356 default PAGE_SIZE_4KB
361 This is the default page size used by all SuperH CPUs.
365 depends on EXPERIMENTAL && X2TLB
367 This enables 8kB pages as supported by SH-X2 and later MMUs.
369 config PAGE_SIZE_64KB
371 depends on EXPERIMENTAL && CPU_SH4
373 This enables support for 64kB pages, possible on all SH-4
374 CPUs and later. Highly experimental, not recommended.
379 prompt "HugeTLB page size"
380 depends on HUGETLB_PAGE && CPU_SH4 && MMU
381 default HUGETLB_PAGE_SIZE_64K
383 config HUGETLB_PAGE_SIZE_64K
386 config HUGETLB_PAGE_SIZE_256K
390 config HUGETLB_PAGE_SIZE_1MB
393 config HUGETLB_PAGE_SIZE_4MB
397 config HUGETLB_PAGE_SIZE_64MB
407 menu "Cache configuration"
409 config SH7705_CACHE_32KB
410 bool "Enable 32KB cache size for SH7705"
411 depends on CPU_SUBTYPE_SH7705
414 config SH_DIRECT_MAPPED
415 bool "Use direct-mapped caching"
418 Selecting this option will configure the caches to be direct-mapped,
419 even if the cache supports a 2 or 4-way mode. This is useful primarily
420 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
421 SH4-202, SH4-501, etc.)
423 Turn this option off for platforms that do not have a direct-mapped
424 cache, and you have no need to run the caches in such a configuration.
428 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
429 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
431 config CACHE_WRITEBACK
433 depends on CPU_SH2A || CPU_SH3 || CPU_SH4
435 config CACHE_WRITETHROUGH
438 Selecting this option will configure the caches in write-through
439 mode, as opposed to the default write-back configuration.
441 Since there's sill some aliasing issues on SH-4, this option will
442 unfortunately still require the majority of flushing functions to
443 be implemented to deal with aliasing.