5 select SH_WRITETHROUGH if !CPU_SH2A
21 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
31 config CPU_SUBTYPE_ST40
34 select CPU_HAS_INTC2_IRQ
43 prompt "Processor sub-type selection"
49 # SH-2 Processor Support
51 config CPU_SUBTYPE_SH7619
52 bool "Support SH7619 processor"
54 select CPU_HAS_IPR_IRQ
56 # SH-2A Processor Support
58 config CPU_SUBTYPE_SH7206
59 bool "Support SH7206 processor"
61 select CPU_HAS_IPR_IRQ
63 # SH-3 Processor Support
65 config CPU_SUBTYPE_SH7300
66 bool "Support SH7300 processor"
69 config CPU_SUBTYPE_SH7705
70 bool "Support SH7705 processor"
72 select CPU_HAS_IPR_IRQ
74 config CPU_SUBTYPE_SH7706
75 bool "Support SH7706 processor"
77 select CPU_HAS_IPR_IRQ
79 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
81 config CPU_SUBTYPE_SH7707
82 bool "Support SH7707 processor"
85 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
87 config CPU_SUBTYPE_SH7708
88 bool "Support SH7708 processor"
91 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
92 if you have a 100 Mhz SH-3 HD6417708R CPU.
94 config CPU_SUBTYPE_SH7709
95 bool "Support SH7709 processor"
97 select CPU_HAS_IPR_IRQ
99 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
101 config CPU_SUBTYPE_SH7710
102 bool "Support SH7710 processor"
104 select CPU_HAS_IPR_IRQ
106 Select SH7710 if you have a SH3-DSP SH7710 CPU.
108 config CPU_SUBTYPE_SH7712
109 bool "Support SH7712 processor"
111 select CPU_HAS_IPR_IRQ
113 Select SH7712 if you have a SH3-DSP SH7712 CPU.
115 # SH-4 Processor Support
117 config CPU_SUBTYPE_SH7750
118 bool "Support SH7750 processor"
120 select CPU_HAS_INTC_IRQ
122 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
124 config CPU_SUBTYPE_SH7091
125 bool "Support SH7091 processor"
127 select CPU_HAS_INTC_IRQ
129 Select SH7091 if you have an SH-4 based Sega device (such as
130 the Dreamcast, Naomi, and Naomi 2).
132 config CPU_SUBTYPE_SH7750R
133 bool "Support SH7750R processor"
135 select CPU_HAS_INTC_IRQ
137 config CPU_SUBTYPE_SH7750S
138 bool "Support SH7750S processor"
140 select CPU_HAS_INTC_IRQ
142 config CPU_SUBTYPE_SH7751
143 bool "Support SH7751 processor"
145 select CPU_HAS_INTC_IRQ
147 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
148 or if you have a HD6417751R CPU.
150 config CPU_SUBTYPE_SH7751R
151 bool "Support SH7751R processor"
153 select CPU_HAS_INTC_IRQ
155 config CPU_SUBTYPE_SH7760
156 bool "Support SH7760 processor"
158 select CPU_HAS_INTC2_IRQ
159 select CPU_HAS_IPR_IRQ
161 config CPU_SUBTYPE_SH4_202
162 bool "Support SH4-202 processor"
165 # ST40 Processor Support
167 config CPU_SUBTYPE_ST40STB1
168 bool "Support ST40STB1/ST40RA processors"
169 select CPU_SUBTYPE_ST40
171 Select ST40STB1 if you have a ST40RA CPU.
172 This was previously called the ST40STB1, hence the option name.
174 config CPU_SUBTYPE_ST40GX1
175 bool "Support ST40GX1 processor"
176 select CPU_SUBTYPE_ST40
178 Select ST40GX1 if you have a ST40GX1 CPU.
180 # SH-4A Processor Support
182 config CPU_SUBTYPE_SH7770
183 bool "Support SH7770 processor"
186 config CPU_SUBTYPE_SH7780
187 bool "Support SH7780 processor"
189 select CPU_HAS_INTC_IRQ
191 config CPU_SUBTYPE_SH7785
192 bool "Support SH7785 processor"
195 select CPU_HAS_INTC2_IRQ
197 config CPU_SUBTYPE_SHX3
198 bool "Support SH-X3 processor"
201 select CPU_HAS_INTC2_IRQ
203 # SH4AL-DSP Processor Support
205 config CPU_SUBTYPE_SH73180
206 bool "Support SH73180 processor"
209 config CPU_SUBTYPE_SH7343
210 bool "Support SH7343 processor"
213 config CPU_SUBTYPE_SH7722
214 bool "Support SH7722 processor"
217 select CPU_HAS_INTC_IRQ
218 select ARCH_SPARSEMEM_ENABLE
219 select SYS_SUPPORTS_NUMA
223 menu "Memory management options"
229 bool "Support for memory management hardware"
233 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
234 boot on these systems, this option must not be set.
236 On other systems (such as the SH-3 and 4) where an MMU exists,
237 turning this off will boot the kernel on these machines with the
238 MMU implicitly switched off.
242 default "0x80000000" if MMU
246 hex "Physical memory start address"
249 Computers built with Hitachi SuperH processors always
250 map the ROM starting at address zero. But the processor
251 does not specify the range that RAM takes.
253 The physical memory (RAM) start address will be automatically
254 set to 08000000. Other platforms, such as the Solution Engine
255 boards typically map RAM at 0C000000.
257 Tweak this only when porting to a new machine which does not
258 already have a defconfig. Changing it from the known correct
259 value on any of the known systems will only lead to disaster.
262 hex "Physical memory size"
265 This sets the default memory size assumed by your SH kernel. It can
266 be overridden as normal by the 'mem=' argument on the kernel command
267 line. If unsure, consult your board specifications or just leave it
268 as 0x00400000 which was the default value before this became
272 bool "Support 32-bit physical addressing through PMB"
273 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
276 If you say Y here, physical addressing will be extended to
277 32-bits through the SH-4A PMB. If this is not set, legacy
278 29-bit physical addressing will be used.
281 bool "Enable extended TLB mode"
282 depends on CPU_SHX2 && MMU && EXPERIMENTAL
284 Selecting this option will enable the extended mode of the SH-X2
285 TLB. For legacy SH-X behaviour and interoperability, say N. For
286 all of the fun new features and a willingless to submit bug reports,
290 bool "Support vsyscall page"
294 This will enable support for the kernel mapping a vDSO page
295 in process space, and subsequently handing down the entry point
296 to the libc through the ELF auxiliary vector.
298 From the kernel side this is used for the signal trampoline.
299 For systems with an MMU that can afford to give up a page,
300 (the default value) say Y.
303 bool "Non Uniform Memory Access (NUMA) Support"
304 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
307 Some SH systems have many various memories scattered around
308 the address space, each with varying latencies. This enables
309 support for these blocks by binding them to nodes and allowing
310 memory policies to be used for prioritizing and controlling
311 allocation behaviour.
316 depends on NEED_MULTIPLE_NODES
318 config ARCH_FLATMEM_ENABLE
322 config ARCH_SPARSEMEM_ENABLE
324 select SPARSEMEM_STATIC
326 config ARCH_SPARSEMEM_DEFAULT
329 config MAX_ACTIVE_REGIONS
331 default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
334 config ARCH_POPULATES_NODE_MAP
337 config ARCH_SELECT_MEMORY_MODEL
340 config ARCH_ENABLE_MEMORY_HOTPLUG
344 config ARCH_MEMORY_PROBE
346 depends on MEMORY_HOTPLUG
349 prompt "Kernel page size"
350 default PAGE_SIZE_4KB
355 This is the default page size used by all SuperH CPUs.
359 depends on EXPERIMENTAL && X2TLB
361 This enables 8kB pages as supported by SH-X2 and later MMUs.
363 config PAGE_SIZE_64KB
365 depends on EXPERIMENTAL && CPU_SH4
367 This enables support for 64kB pages, possible on all SH-4
368 CPUs and later. Highly experimental, not recommended.
373 prompt "HugeTLB page size"
374 depends on HUGETLB_PAGE && CPU_SH4 && MMU
375 default HUGETLB_PAGE_SIZE_64K
377 config HUGETLB_PAGE_SIZE_64K
380 config HUGETLB_PAGE_SIZE_256K
384 config HUGETLB_PAGE_SIZE_1MB
387 config HUGETLB_PAGE_SIZE_4MB
391 config HUGETLB_PAGE_SIZE_64MB
401 menu "Cache configuration"
403 config SH7705_CACHE_32KB
404 bool "Enable 32KB cache size for SH7705"
405 depends on CPU_SUBTYPE_SH7705
408 config SH_DIRECT_MAPPED
409 bool "Use direct-mapped caching"
412 Selecting this option will configure the caches to be direct-mapped,
413 even if the cache supports a 2 or 4-way mode. This is useful primarily
414 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
415 SH4-202, SH4-501, etc.)
417 Turn this option off for platforms that do not have a direct-mapped
418 cache, and you have no need to run the caches in such a configuration.
420 config SH_WRITETHROUGH
421 bool "Use write-through caching"
423 Selecting this option will configure the caches in write-through
424 mode, as opposed to the default write-back configuration.
426 Since there's sill some aliasing issues on SH-4, this option will
427 unfortunately still require the majority of flushing functions to
428 be implemented to deal with aliasing.