2 * arch/sh/kernel/cpu/sh4/probe.c
4 * CPU Subtype Probing for SH-4.
6 * Copyright (C) 2001 - 2006 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
18 int __init detect_cpu_and_cache_system(void)
20 unsigned long pvr, prr, cvr;
23 static unsigned long sizes[16] = {
31 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
32 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
33 cvr = (ctrl_inl(CCN_CVR));
36 * Setup some sane SH-4 defaults for the icache
38 current_cpu_data.icache.way_incr = (1 << 13);
39 current_cpu_data.icache.entry_shift = 5;
40 current_cpu_data.icache.sets = 256;
41 current_cpu_data.icache.ways = 1;
42 current_cpu_data.icache.linesz = L1_CACHE_BYTES;
45 * And again for the dcache ..
47 current_cpu_data.dcache.way_incr = (1 << 14);
48 current_cpu_data.dcache.entry_shift = 5;
49 current_cpu_data.dcache.sets = 512;
50 current_cpu_data.dcache.ways = 1;
51 current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
54 * Setup some generic flags we can probe
55 * (L2 and DSP detection only work on SH-4A)
57 if (((pvr >> 16) & 0xff) == 0x10) {
58 if ((cvr & 0x02000000) == 0)
59 current_cpu_data.flags |= CPU_HAS_L2_CACHE;
60 if ((cvr & 0x10000000) == 0)
61 current_cpu_data.flags |= CPU_HAS_DSP;
63 current_cpu_data.flags |= CPU_HAS_LLSC;
66 /* FPU detection works for everyone */
67 if ((cvr & 0x20000000) == 1)
68 current_cpu_data.flags |= CPU_HAS_FPU;
70 /* Mask off the upper chip ID */
74 * Probe the underlying processor version/revision and
75 * adjust cpu_data setup accordingly.
79 current_cpu_data.type = CPU_SH7750;
80 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
84 current_cpu_data.type = CPU_SH7750S;
85 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
89 current_cpu_data.type = CPU_SH7751;
90 current_cpu_data.flags |= CPU_HAS_FPU;
93 current_cpu_data.type = CPU_SH73180;
94 current_cpu_data.icache.ways = 4;
95 current_cpu_data.dcache.ways = 4;
96 current_cpu_data.flags |= CPU_HAS_LLSC;
100 current_cpu_data.type = CPU_SH7770;
101 current_cpu_data.icache.ways = 4;
102 current_cpu_data.dcache.ways = 4;
104 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
109 current_cpu_data.type = CPU_SH7781;
111 current_cpu_data.type = CPU_SH7780;
113 current_cpu_data.icache.ways = 4;
114 current_cpu_data.dcache.ways = 4;
116 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
122 current_cpu_data.type = CPU_SH7343;
123 current_cpu_data.icache.ways = 4;
124 current_cpu_data.dcache.ways = 4;
125 current_cpu_data.flags |= CPU_HAS_LLSC;
129 current_cpu_data.type = CPU_SH7785;
130 current_cpu_data.icache.ways = 4;
131 current_cpu_data.dcache.ways = 4;
132 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
137 current_cpu_data.type = CPU_SH7722;
138 current_cpu_data.icache.ways = 4;
139 current_cpu_data.dcache.ways = 4;
140 current_cpu_data.flags |= CPU_HAS_LLSC;
144 current_cpu_data.type = CPU_ST40RA;
145 current_cpu_data.flags |= CPU_HAS_FPU;
148 current_cpu_data.type = CPU_ST40GX1;
149 current_cpu_data.flags |= CPU_HAS_FPU;
152 current_cpu_data.type = CPU_SH4_501;
153 current_cpu_data.icache.ways = 2;
154 current_cpu_data.dcache.ways = 2;
157 current_cpu_data.type = CPU_SH4_202;
158 current_cpu_data.icache.ways = 2;
159 current_cpu_data.dcache.ways = 2;
160 current_cpu_data.flags |= CPU_HAS_FPU;
162 case 0x500 ... 0x501:
165 current_cpu_data.type = CPU_SH7750R;
168 current_cpu_data.type = CPU_SH7751R;
171 current_cpu_data.type = CPU_SH7760;
175 current_cpu_data.icache.ways = 2;
176 current_cpu_data.dcache.ways = 2;
178 current_cpu_data.flags |= CPU_HAS_FPU;
182 current_cpu_data.type = CPU_SH_NONE;
186 #ifdef CONFIG_SH_DIRECT_MAPPED
187 current_cpu_data.icache.ways = 1;
188 current_cpu_data.dcache.ways = 1;
191 #ifdef CONFIG_CPU_HAS_PTEA
192 current_cpu_data.flags |= CPU_HAS_PTEA;
196 * On anything that's not a direct-mapped cache, look to the CVR
197 * for I/D-cache specifics.
199 if (current_cpu_data.icache.ways > 1) {
200 size = sizes[(cvr >> 20) & 0xf];
201 current_cpu_data.icache.way_incr = (size >> 1);
202 current_cpu_data.icache.sets = (size >> 6);
206 /* And the rest of the D-cache */
207 if (current_cpu_data.dcache.ways > 1) {
208 size = sizes[(cvr >> 16) & 0xf];
209 current_cpu_data.dcache.way_incr = (size >> 1);
210 current_cpu_data.dcache.sets = (size >> 6);
214 * Setup the L2 cache desc
216 * SH-4A's have an optional PIPT L2.
218 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
220 * Size calculation is much more sensible
221 * than it is for the L1.
223 * Sizes are 128KB, 258KB, 512KB, and 1MB.
225 size = (cvr & 0xf) << 17;
229 current_cpu_data.scache.way_incr = (1 << 16);
230 current_cpu_data.scache.entry_shift = 5;
231 current_cpu_data.scache.ways = 4;
232 current_cpu_data.scache.linesz = L1_CACHE_BYTES;
234 current_cpu_data.scache.entry_mask =
235 (current_cpu_data.scache.way_incr -
236 current_cpu_data.scache.linesz);
238 current_cpu_data.scache.sets = size /
239 (current_cpu_data.scache.linesz *
240 current_cpu_data.scache.ways);
242 current_cpu_data.scache.way_size =
243 (current_cpu_data.scache.sets *
244 current_cpu_data.scache.linesz);