2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007 Magnus Damm
6 * Based on intc2.c and ipr.c
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
22 #include <linux/interrupt.h>
24 #define _INTC_MK(fn, idx, bit, value) \
25 ((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
26 #define _INTC_FN(h) (h >> 24)
27 #define _INTC_VALUE(h) ((h >> 16) & 0xff)
28 #define _INTC_IDX(h) ((h >> 8) & 0xff)
29 #define _INTC_BIT(h) (h & 0xff)
31 #define _INTC_PTR(desc, member, data) \
32 (desc->member + _INTC_IDX(data))
34 static inline struct intc_desc *get_intc_desc(unsigned int irq)
36 struct irq_chip *chip = get_irq_chip(irq);
37 return (void *)((char *)chip - offsetof(struct intc_desc, chip));
40 static inline unsigned int set_field(unsigned int value,
41 unsigned int field_value,
45 value &= ~(((1 << width) - 1) << shift);
46 value |= field_value << shift;
50 static inline unsigned int set_prio_field(struct intc_desc *desc,
52 unsigned int priority,
55 unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
57 return set_field(value, priority, width, _INTC_BIT(data));
60 static void disable_prio_16(struct intc_desc *desc, unsigned int data)
62 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
64 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
67 static void enable_prio_16(struct intc_desc *desc, unsigned int data)
69 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
70 unsigned int prio = _INTC_VALUE(data);
72 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
75 static void disable_prio_32(struct intc_desc *desc, unsigned int data)
77 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
79 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
82 static void enable_prio_32(struct intc_desc *desc, unsigned int data)
84 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
85 unsigned int prio = _INTC_VALUE(data);
87 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
90 static void write_set_reg_8(struct intc_desc *desc, unsigned int data)
92 ctrl_outb(1 << _INTC_BIT(data),
93 _INTC_PTR(desc, mask_regs, data)->set_reg);
96 static void write_clr_reg_8(struct intc_desc *desc, unsigned int data)
98 ctrl_outb(1 << _INTC_BIT(data),
99 _INTC_PTR(desc, mask_regs, data)->clr_reg);
102 static void write_set_reg_32(struct intc_desc *desc, unsigned int data)
104 ctrl_outl(1 << _INTC_BIT(data),
105 _INTC_PTR(desc, mask_regs, data)->set_reg);
108 static void write_clr_reg_32(struct intc_desc *desc, unsigned int data)
110 ctrl_outl(1 << _INTC_BIT(data),
111 _INTC_PTR(desc, mask_regs, data)->clr_reg);
114 static void or_set_reg_16(struct intc_desc *desc, unsigned int data)
116 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
118 ctrl_outw(ctrl_inw(addr) | 1 << _INTC_BIT(data), addr);
121 static void and_set_reg_16(struct intc_desc *desc, unsigned int data)
123 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
125 ctrl_outw(ctrl_inw(addr) & ~(1 << _INTC_BIT(data)), addr);
128 static void or_set_reg_32(struct intc_desc *desc, unsigned int data)
130 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
132 ctrl_outl(ctrl_inl(addr) | 1 << _INTC_BIT(data), addr);
135 static void and_set_reg_32(struct intc_desc *desc, unsigned int data)
137 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
139 ctrl_outl(ctrl_inl(addr) & ~(1 << _INTC_BIT(data)), addr);
142 enum { REG_FN_ERROR=0,
143 REG_FN_DUAL_8, REG_FN_DUAL_32,
144 REG_FN_ENA_16, REG_FN_ENA_32,
145 REG_FN_PRIO_16, REG_FN_PRIO_32 };
148 void (*enable)(struct intc_desc *, unsigned int);
149 void (*disable)(struct intc_desc *, unsigned int);
151 [REG_FN_DUAL_8] = { write_clr_reg_8, write_set_reg_8 },
152 [REG_FN_DUAL_32] = { write_clr_reg_32, write_set_reg_32 },
153 [REG_FN_ENA_16] = { or_set_reg_16, and_set_reg_16 },
154 [REG_FN_ENA_32] = { or_set_reg_32, and_set_reg_32 },
155 [REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
156 [REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
159 static void intc_enable(unsigned int irq)
161 struct intc_desc *desc = get_intc_desc(irq);
162 unsigned int data = (unsigned int) get_irq_chip_data(irq);
164 intc_reg_fns[_INTC_FN(data)].enable(desc, data);
167 static void intc_disable(unsigned int irq)
169 struct intc_desc *desc = get_intc_desc(irq);
170 unsigned int data = (unsigned int) get_irq_chip_data(irq);
172 intc_reg_fns[_INTC_FN(data)].disable(desc, data);
175 static void set_sense_16(struct intc_desc *desc, unsigned int data)
177 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
178 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
179 unsigned int bit = _INTC_BIT(data);
180 unsigned int value = _INTC_VALUE(data);
182 ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
185 static void set_sense_32(struct intc_desc *desc, unsigned int data)
187 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
188 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
189 unsigned int bit = _INTC_BIT(data);
190 unsigned int value = _INTC_VALUE(data);
192 ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
195 #define VALID(x) (x | 0x80)
197 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
198 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
199 [IRQ_TYPE_EDGE_RISING] = VALID(1),
200 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
201 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
204 static int intc_set_sense(unsigned int irq, unsigned int type)
206 struct intc_desc *desc = get_intc_desc(irq);
207 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
208 unsigned int i, j, data, bit;
209 intc_enum enum_id = 0;
211 for (i = 0; i < desc->nr_vectors; i++) {
212 struct intc_vect *vect = desc->vectors + i;
214 if (evt2irq(vect->vect) != irq)
217 enum_id = vect->enum_id;
221 if (!enum_id || !value || !desc->sense_regs)
226 for (i = 0; i < desc->nr_sense_regs; i++) {
227 struct intc_sense_reg *sr = desc->sense_regs + i;
229 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
230 if (sr->enum_ids[j] != enum_id)
233 bit = sr->reg_width - ((j + 1) * sr->field_width);
234 data = _INTC_MK(0, i, bit, value);
236 switch(sr->reg_width) {
238 set_sense_16(desc, data);
241 set_sense_32(desc, data);
252 static unsigned int __init intc_find_dual_handler(unsigned int width)
256 return REG_FN_DUAL_8;
258 return REG_FN_DUAL_32;
265 static unsigned int __init intc_find_prio_handler(unsigned int width)
269 return REG_FN_PRIO_16;
271 return REG_FN_PRIO_32;
278 static unsigned int __init intc_find_ena_handler(unsigned int width)
282 return REG_FN_ENA_16;
284 return REG_FN_ENA_32;
291 static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id)
293 struct intc_group *g = desc->groups;
296 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
297 g = desc->groups + i;
299 for (j = 0; g->enum_ids[j]; j++) {
300 if (g->enum_ids[j] != enum_id)
310 static unsigned int __init intc_prio_value(struct intc_desc *desc,
311 intc_enum enum_id, int do_grps)
313 struct intc_prio *p = desc->priorities;
316 for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
317 p = desc->priorities + i;
319 if (p->enum_id != enum_id)
326 return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);
328 /* default to the lowest priority possible if no priority is set
329 * - this needs to be at least 2 for 5-bit priorities on 7780
335 static unsigned int __init intc_mask_data(struct intc_desc *desc,
336 intc_enum enum_id, int do_grps)
338 struct intc_mask_reg *mr = desc->mask_regs;
339 unsigned int i, j, fn;
341 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
342 mr = desc->mask_regs + i;
344 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
345 if (mr->enum_ids[j] != enum_id)
348 switch (mr->clr_reg) {
349 case 1: /* 1 = enabled interrupt - "enable" register */
350 fn = intc_find_ena_handler(mr->reg_width);
353 fn = intc_find_dual_handler(mr->reg_width);
356 if (fn == REG_FN_ERROR)
359 return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
364 return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0);
369 static unsigned int __init intc_prio_data(struct intc_desc *desc,
370 intc_enum enum_id, int do_grps)
372 struct intc_prio_reg *pr = desc->prio_regs;
373 unsigned int i, j, fn, bit, prio;
375 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
376 pr = desc->prio_regs + i;
378 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
379 if (pr->enum_ids[j] != enum_id)
382 fn = intc_find_prio_handler(pr->reg_width);
383 if (fn == REG_FN_ERROR)
386 prio = intc_prio_value(desc, enum_id, 1);
387 bit = pr->reg_width - ((j + 1) * pr->field_width);
391 return _INTC_MK(fn, i, bit, prio);
396 return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0);
401 static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
404 unsigned int data[2], primary;
406 /* Prefer single interrupt source bitmap over other combinations:
407 * 1. bitmap, single interrupt source
408 * 2. priority, single interrupt source
409 * 3. bitmap, multiple interrupt sources (groups)
410 * 4. priority, multiple interrupt sources (groups)
413 data[0] = intc_mask_data(desc, enum_id, 0);
414 data[1] = intc_prio_data(desc, enum_id, 0);
417 if (!data[0] && data[1])
420 data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1);
421 data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1);
426 BUG_ON(!data[primary]); /* must have primary masking method */
428 disable_irq_nosync(irq);
429 set_irq_chip_and_handler_name(irq, &desc->chip,
430 handle_level_irq, "level");
431 set_irq_chip_data(irq, (void *)data[primary]);
433 /* enable secondary masking method if present */
435 intc_reg_fns[_INTC_FN(data[!primary])].enable(desc,
438 /* irq should be disabled by default */
439 desc->chip.mask(irq);
442 void __init register_intc_controller(struct intc_desc *desc)
446 desc->chip.mask = intc_disable;
447 desc->chip.unmask = intc_enable;
448 desc->chip.mask_ack = intc_disable;
449 desc->chip.set_type = intc_set_sense;
451 for (i = 0; i < desc->nr_vectors; i++) {
452 struct intc_vect *vect = desc->vectors + i;
454 intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));