1 menu "Processor features"
4 prompt "Endianess selection"
5 default CPU_LITTLE_ENDIAN
7 Some SuperH machines can be configured for either little or big
8 endian byte order. These modes require different kernels.
10 config CPU_LITTLE_ENDIAN
20 depends on CPU_HAS_FPU
23 Selecting this option will enable support for SH processors that
24 have FPU units (ie, SH77xx).
26 This option must be set in order to enable the FPU.
29 bool "FPU emulation support"
30 depends on !SH_FPU && EXPERIMENTAL
33 Selecting this option will enable support for software FPU emulation.
34 Most SH-3 users will want to say Y here, whereas most SH-4 users will
39 depends on CPU_HAS_DSP
42 Selecting this option will enable support for SH processors that
43 have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
45 This option must be set in order to enable the DSP.
52 Selecting this option will allow the Linux kernel to use SH3 on-chip
57 config SH_STORE_QUEUES
58 bool "Support for Store Queues"
61 Selecting this option will enable an in-kernel API for manipulating
62 the store queues integrated in the SH-4 processors.
64 config SPECULATIVE_EXECUTION
65 bool "Speculative subroutine return"
66 depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
68 This enables support for a speculative instruction fetch for
69 subroutine return. There are various pitfalls associated with
70 this, as outlined in the SH7780 hardware manual.
77 config CPU_HAS_MASKREG_IRQ
80 config CPU_HAS_IPR_IRQ
86 This will enable the use of SR.RB register bank usage. Processors
87 that are lacking this bit must have another method in place for
88 accomplishing what is taken care of by the banked registers.
90 See <file:Documentation/sh/register-banks.txt> for further
91 information on SR.RB and register banking in the kernel in general.