2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
23 #include <linux/config.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
35 #include <asm/ppcdebug.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/abs_addr.h>
54 #include <asm/sections.h>
57 #define DBG(fmt...) udbg_printf(fmt)
63 * Note: pte --> Linux PTE
64 * HPTE --> PowerPC Hashed Page Table Entry
67 * htab_initialize is called with the MMU off (of course), but
68 * the kernel has been copied down to zero so it can directly
69 * reference global data. At this point it is very difficult
70 * to print debug info.
75 extern unsigned long dart_tablebase;
76 #endif /* CONFIG_U3_DART */
79 unsigned long htab_hash_mask;
81 extern unsigned long _SDR1;
86 static inline void loop_forever(void)
88 volatile unsigned long x = 1;
93 static inline void create_pte_mapping(unsigned long start, unsigned long end,
94 unsigned long mode, int large)
98 unsigned long tmp_mode;
103 vflags = HPTE_V_BOLTED | HPTE_V_LARGE;
106 vflags = HPTE_V_BOLTED;
109 for (addr = start; addr < end; addr += step) {
110 unsigned long vpn, hash, hpteg;
111 unsigned long vsid = get_kernel_vsid(addr);
112 unsigned long va = (vsid << 28) | (addr & 0xfffffff);
116 vpn = va >> HPAGE_SHIFT;
118 vpn = va >> PAGE_SHIFT;
123 /* Make non-kernel text non-executable */
124 if (!in_kernel_text(addr))
125 tmp_mode = mode | HW_NO_EXEC;
127 hash = hpt_hash(vpn, large);
129 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
131 #ifdef CONFIG_PPC_ISERIES
132 if (systemcfg->platform & PLATFORM_ISERIES_LPAR)
133 ret = iSeries_hpte_bolt_or_insert(hpteg, va,
134 virt_to_abs(addr) >> PAGE_SHIFT,
138 #ifdef CONFIG_PPC_PSERIES
139 if (systemcfg->platform & PLATFORM_LPAR)
140 ret = pSeries_lpar_hpte_insert(hpteg, va,
141 virt_to_abs(addr) >> PAGE_SHIFT,
145 #ifdef CONFIG_PPC_MULTIPLATFORM
146 ret = native_hpte_insert(hpteg, va,
147 virt_to_abs(addr) >> PAGE_SHIFT,
152 ppc64_terminate_msg(0x20, "create_pte_mapping");
158 void __init htab_initialize(void)
160 unsigned long table, htab_size_bytes;
161 unsigned long pteg_count;
162 unsigned long mode_rw;
163 int i, use_largepages = 0;
164 unsigned long base = 0, size = 0;
165 extern unsigned long tce_alloc_start, tce_alloc_end;
167 DBG(" -> htab_initialize()\n");
170 * Calculate the required size of the htab. We want the number of
171 * PTEGs to equal one half the number of real pages.
173 htab_size_bytes = 1UL << ppc64_pft_size;
174 pteg_count = htab_size_bytes >> 7;
176 /* For debug, make the HTAB 1/8 as big as it normally would be. */
177 ifppcdebug(PPCDBG_HTABSIZE) {
179 htab_size_bytes = pteg_count << 7;
182 htab_hash_mask = pteg_count - 1;
184 if (systemcfg->platform & PLATFORM_LPAR) {
185 /* Using a hypervisor which owns the htab */
189 /* Find storage for the HPT. Must be contiguous in
190 * the absolute address space.
192 table = lmb_alloc(htab_size_bytes, htab_size_bytes);
194 DBG("Hash table allocated at %lx, size: %lx\n", table,
198 ppc64_terminate_msg(0x20, "hpt space");
201 htab_address = abs_to_virt(table);
203 /* htab absolute addr + encoded htabsize */
204 _SDR1 = table + __ilog2(pteg_count) - 11;
206 /* Initialize the HPT with no entries */
207 memset((void *)table, 0, htab_size_bytes);
210 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
212 /* On U3 based machines, we need to reserve the DART area and
213 * _NOT_ map it to avoid cache paradoxes as it's remapped non
216 if (cpu_has_feature(CPU_FTR_16M_PAGE))
219 /* create bolted the linear mapping in the hash table */
220 for (i=0; i < lmb.memory.cnt; i++) {
221 base = lmb.memory.region[i].base + KERNELBASE;
222 size = lmb.memory.region[i].size;
224 DBG("creating mapping for region: %lx : %lx\n", base, size);
226 #ifdef CONFIG_U3_DART
227 /* Do not map the DART space. Fortunately, it will be aligned
228 * in such a way that it will not cross two lmb regions and will
229 * fit within a single 16Mb page.
230 * The DART space is assumed to be a full 16Mb region even if we
231 * only use 2Mb of that space. We will use more of it later for
232 * AGP GART. We have to use a full 16Mb large page.
234 DBG("DART base: %lx\n", dart_tablebase);
236 if (dart_tablebase != 0 && dart_tablebase >= base
237 && dart_tablebase < (base + size)) {
238 if (base != dart_tablebase)
239 create_pte_mapping(base, dart_tablebase, mode_rw,
241 if ((base + size) > (dart_tablebase + 16*MB))
242 create_pte_mapping(dart_tablebase + 16*MB, base + size,
243 mode_rw, use_largepages);
246 #endif /* CONFIG_U3_DART */
247 create_pte_mapping(base, base + size, mode_rw, use_largepages);
251 * If we have a memory_limit and we've allocated TCEs then we need to
252 * explicitly map the TCE area at the top of RAM. We also cope with the
253 * case that the TCEs start below memory_limit.
254 * tce_alloc_start/end are 16MB aligned so the mapping should work
255 * for either 4K or 16MB pages.
257 if (tce_alloc_start) {
258 tce_alloc_start += KERNELBASE;
259 tce_alloc_end += KERNELBASE;
261 if (base + size >= tce_alloc_start)
262 tce_alloc_start = base + size + 1;
264 create_pte_mapping(tce_alloc_start, tce_alloc_end,
265 mode_rw, use_largepages);
268 DBG(" <- htab_initialize()\n");
274 * Called by asm hashtable.S for doing lazy icache flush
276 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
280 if (!pfn_valid(pte_pfn(pte)))
283 page = pte_page(pte);
286 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
288 __flush_dcache_icache(page_address(page));
289 set_bit(PG_arch_1, &page->flags);
298 * 1 - normal page fault
299 * -1 - critical hash insertion error
301 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
305 struct mm_struct *mm;
312 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
315 switch (REGION_ID(ea)) {
322 vsid = get_vsid(mm->context.id, ea);
324 case VMALLOC_REGION_ID:
326 vsid = get_kernel_vsid(ea);
329 case KERNEL_REGION_ID:
331 * Should never get here - entire 0xC0... region is bolted.
332 * Send the problem up to do_page_fault
337 * Send the problem up to do_page_fault
348 tmp = cpumask_of_cpu(smp_processor_id());
349 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
352 /* Is this a huge page ? */
353 if (unlikely(in_hugepage_area(mm->context, ea)))
354 ret = hash_huge_page(mm, access, ea, vsid, local);
356 ptep = find_linux_pte(pgdir, ea);
359 ret = __hash_page(ea, access, vsid, ptep, trap, local);
365 void flush_hash_page(unsigned long va, pte_t pte, int local)
367 unsigned long vpn, hash, secondary, slot;
368 unsigned long huge = pte_huge(pte);
371 vpn = va >> HPAGE_SHIFT;
373 vpn = va >> PAGE_SHIFT;
374 hash = hpt_hash(vpn, huge);
375 secondary = (pte_val(pte) & _PAGE_SECONDARY) >> 15;
378 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
379 slot += (pte_val(pte) & _PAGE_GROUP_IX) >> 12;
381 ppc_md.hpte_invalidate(slot, va, huge, local);
384 void flush_hash_range(unsigned long number, int local)
386 if (ppc_md.flush_hash_range) {
387 ppc_md.flush_hash_range(number, local);
390 struct ppc64_tlb_batch *batch =
391 &__get_cpu_var(ppc64_tlb_batch);
393 for (i = 0; i < number; i++)
394 flush_hash_page(batch->vaddr[i], batch->pte[i], local);
398 static inline void make_bl(unsigned int *insn_addr, void *func)
400 unsigned long funcp = *((unsigned long *)func);
401 int offset = funcp - (unsigned long)insn_addr;
403 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
404 flush_icache_range((unsigned long)insn_addr, 4+
405 (unsigned long)insn_addr);
409 * low_hash_fault is called when we the low level hash code failed
410 * to instert a PTE due to an hypervisor error
412 void low_hash_fault(struct pt_regs *regs, unsigned long address)
414 if (user_mode(regs)) {
417 info.si_signo = SIGBUS;
419 info.si_code = BUS_ADRERR;
420 info.si_addr = (void __user *)address;
421 force_sig_info(SIGBUS, &info, current);
424 bad_page_fault(regs, address, SIGBUS);
427 void __init htab_finish_init(void)
429 extern unsigned int *htab_call_hpte_insert1;
430 extern unsigned int *htab_call_hpte_insert2;
431 extern unsigned int *htab_call_hpte_remove;
432 extern unsigned int *htab_call_hpte_updatepp;
434 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
435 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
436 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
437 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);