2 * arch/ppc64/kernel/u3_iommu.c
4 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
6 * Based on pSeries_iommu.c:
7 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
10 * Dynamic DMA mapping support, Apple U3 & IBM CPC925 "DART" iommu.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <linux/types.h>
31 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/vmalloc.h>
40 #include <asm/ppcdebug.h>
41 #include <asm/iommu.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/machdep.h>
44 #include <asm/abs_addr.h>
45 #include <asm/cacheflush.h>
51 extern int iommu_force_on;
53 /* Physical base address and size of the DART table */
54 unsigned long dart_tablebase; /* exported to htab_initialize */
55 static unsigned long dart_tablesize;
57 /* Virtual base address of the DART table */
58 static u32 *dart_vbase;
60 /* Mapped base address for the dart */
61 static unsigned int *dart;
63 /* Dummy val that entries are set to when unused */
64 static unsigned int dart_emptyval;
66 static struct iommu_table iommu_table_u3;
67 static int iommu_table_u3_inited;
68 static int dart_dirty;
72 static inline void dart_tlb_invalidate_all(void)
80 /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
81 * control register and wait for it to clear.
83 * Gotcha: Sometimes, the DART won't detect that the bit gets
84 * set. If so, clear it and set it again.
90 reg = in_be32((unsigned int *)dart+DARTCNTL);
91 reg |= DARTCNTL_FLUSHTLB;
92 out_be32((unsigned int *)dart+DARTCNTL, reg);
95 while ((in_be32((unsigned int *)dart+DARTCNTL) & DARTCNTL_FLUSHTLB) &&
99 if (l == (1L<<limit)) {
102 reg = in_be32((unsigned int *)dart+DARTCNTL);
103 reg &= ~DARTCNTL_FLUSHTLB;
104 out_be32((unsigned int *)dart+DARTCNTL, reg);
107 panic("U3-DART: TLB did not flush after waiting a long "
112 static void dart_flush(struct iommu_table *tbl)
115 dart_tlb_invalidate_all();
119 static void dart_build(struct iommu_table *tbl, long index,
120 long npages, unsigned long uaddr,
121 enum dma_data_direction direction)
126 DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
128 dp = ((unsigned int*)tbl->it_base) + index;
130 /* On U3, all memory is contigous, so we can move this
134 rpn = virt_to_abs(uaddr) >> PAGE_SHIFT;
136 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
146 static void dart_free(struct iommu_table *tbl, long index, long npages)
150 /* We don't worry about flushing the TLB cache. The only drawback of
151 * not doing it is that we won't catch buggy device drivers doing
152 * bad DMAs, but then no 32-bit architecture ever does either.
155 DBG("dart: free at: %lx, %lx\n", index, npages);
157 dp = ((unsigned int *)tbl->it_base) + index;
160 *(dp++) = dart_emptyval;
164 static int dart_init(struct device_node *dart_node)
166 unsigned int regword;
170 if (dart_tablebase == 0 || dart_tablesize == 0) {
171 printk(KERN_INFO "U3-DART: table not allocated, using direct DMA\n");
175 /* Make sure nothing from the DART range remains in the CPU cache
176 * from a previous mapping that existed before the kernel took
179 flush_dcache_phys_range(dart_tablebase, dart_tablebase + dart_tablesize);
181 /* Allocate a spare page to map all invalid DART pages. We need to do
182 * that to work around what looks like a problem with the HT bridge
183 * prefetching into invalid pages and corrupting data
185 tmp = lmb_alloc(PAGE_SIZE, PAGE_SIZE);
187 panic("U3-DART: Cannot allocate spare page!");
188 dart_emptyval = DARTMAP_VALID | ((tmp >> PAGE_SHIFT) & DARTMAP_RPNMASK);
190 /* Map in DART registers. FIXME: Use device node to get base address */
191 dart = ioremap(DART_BASE, 0x7000);
193 panic("U3-DART: Cannot map registers!");
195 /* Set initial control register contents: table base,
196 * table size and enable bit
198 regword = DARTCNTL_ENABLE |
199 ((dart_tablebase >> PAGE_SHIFT) << DARTCNTL_BASE_SHIFT) |
200 (((dart_tablesize >> PAGE_SHIFT) & DARTCNTL_SIZE_MASK)
201 << DARTCNTL_SIZE_SHIFT);
202 dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
204 /* Fill initial table */
205 for (i = 0; i < dart_tablesize/4; i++)
206 dart_vbase[i] = dart_emptyval;
208 /* Initialize DART with table base and enable it. */
209 out_be32((unsigned int *)dart, regword);
211 /* Invalidate DART to get rid of possible stale TLBs */
212 dart_tlb_invalidate_all();
214 printk(KERN_INFO "U3/CPC925 DART IOMMU initialized\n");
219 static void iommu_table_u3_setup(void)
221 iommu_table_u3.it_busno = 0;
222 iommu_table_u3.it_offset = 0;
223 /* it_size is in number of entries */
224 iommu_table_u3.it_size = dart_tablesize / sizeof(u32);
226 /* Initialize the common IOMMU code */
227 iommu_table_u3.it_base = (unsigned long)dart_vbase;
228 iommu_table_u3.it_index = 0;
229 iommu_table_u3.it_blocksize = 1;
230 iommu_init_table(&iommu_table_u3);
232 /* Reserve the last page of the DART to avoid possible prefetch
233 * past the DART mapped area
235 set_bit(iommu_table_u3.it_size - 1, iommu_table_u3.it_map);
238 static void iommu_dev_setup_u3(struct pci_dev *dev)
240 struct device_node *dn;
242 /* We only have one iommu table on the mac for now, which makes
243 * things simple. Setup all PCI devices to point to this table
245 * We must use pci_device_to_OF_node() to make sure that
246 * we get the real "final" pointer to the device in the
247 * pci_dev sysdata and not the temporary PHB one
249 dn = pci_device_to_OF_node(dev);
252 PCI_DN(dn)->iommu_table = &iommu_table_u3;
255 static void iommu_bus_setup_u3(struct pci_bus *bus)
257 struct device_node *dn;
259 if (!iommu_table_u3_inited) {
260 iommu_table_u3_inited = 1;
261 iommu_table_u3_setup();
264 dn = pci_bus_to_OF_node(bus);
267 PCI_DN(dn)->iommu_table = &iommu_table_u3;
270 static void iommu_dev_setup_null(struct pci_dev *dev) { }
271 static void iommu_bus_setup_null(struct pci_bus *bus) { }
273 void iommu_init_early_u3(void)
275 struct device_node *dn;
277 /* Find the DART in the device-tree */
278 dn = of_find_compatible_node(NULL, "dart", "u3-dart");
282 /* Setup low level TCE operations for the core IOMMU code */
283 ppc_md.tce_build = dart_build;
284 ppc_md.tce_free = dart_free;
285 ppc_md.tce_flush = dart_flush;
287 /* Initialize the DART HW */
289 /* If init failed, use direct iommu and null setup functions */
290 ppc_md.iommu_dev_setup = iommu_dev_setup_null;
291 ppc_md.iommu_bus_setup = iommu_bus_setup_null;
293 /* Setup pci_dma ops */
294 pci_direct_iommu_init();
296 ppc_md.iommu_dev_setup = iommu_dev_setup_u3;
297 ppc_md.iommu_bus_setup = iommu_bus_setup_u3;
299 /* Setup pci_dma ops */
305 void __init alloc_u3_dart_table(void)
307 /* Only reserve DART space if machine has more than 2GB of RAM
308 * or if requested with iommu=on on cmdline.
310 if (lmb_end_of_DRAM() <= 0x80000000ull && !iommu_force_on)
313 /* 512 pages (2MB) is max DART tablesize. */
314 dart_tablesize = 1UL << 21;
315 /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
316 * will blow up an entire large page anyway in the kernel mapping
318 dart_tablebase = (unsigned long)
319 abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L));
321 printk(KERN_INFO "U3-DART allocated at: %lx\n", dart_tablebase);